mirror of
https://github.com/ARMmbed/DAPLink.git
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170 lines
5.4 KiB
C
170 lines
5.4 KiB
C
/**
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* @file rt_HAL_CM.h
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* @brief
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*
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* DAPLink Interface Firmware
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* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* Definitions */
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#define INITIAL_xPSR 0x01000000
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#define DEMCR_TRCENA 0x01000000
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#define ITM_ITMENA 0x00000001
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#define MAGIC_WORD 0xE25A2EA5
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// ARMCC has deprecated use for ldrex and strex functions
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// from C so do not used them on any devices.
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#if (0)
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#define __USE_EXCLUSIVE_ACCESS
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#else
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#undef __USE_EXCLUSIVE_ACCESS
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#endif
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/* NVIC registers */
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#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
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#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
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#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
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#define NVIC_ISER ((volatile U32 *)0xE000E100)
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#define NVIC_ICER ((volatile U32 *)0xE000E180)
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#if (__TARGET_ARCH_6S_M)
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#define NVIC_IP ((volatile U32 *)0xE000E400)
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#else
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#define NVIC_IP ((volatile U8 *)0xE000E400)
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#endif
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#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
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#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
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#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
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#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
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#define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
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#define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
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#define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
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#define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
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#define OS_LOCK() NVIC_ST_CTRL = 0x0005
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#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
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#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
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#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
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#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
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#if (__TARGET_ARCH_6S_M)
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#define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
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NVIC_ISER[n>>5] = 1 << (n & 0x1F)
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#else
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#define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
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NVIC_ISER[n>>5] = 1 << (n & 0x1F)
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#endif
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#define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
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#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
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/* Core Debug registers */
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#define DEMCR (*((volatile U32 *)0xE000EDFC))
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/* ITM registers */
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#define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
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#define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
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#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
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#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
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#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
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#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
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/* Variables */
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extern BIT dbg_msg;
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/* Functions */
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#ifdef __USE_EXCLUSIVE_ACCESS
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#define rt_inc(p) while(__strex((__ldrex(p)+1),p))
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#define rt_dec(p) while(__strex((__ldrex(p)-1),p))
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#else
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#define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
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#define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
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#endif
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static inline U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
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U32 cnt,c2;
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#ifdef __USE_EXCLUSIVE_ACCESS
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do {
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if ((cnt = __ldrex(count)) == size) {
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__clrex();
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return (cnt); }
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} while (__strex(cnt+1, count));
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do {
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c2 = (cnt = __ldrex(first)) + 1;
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if (c2 == size) c2 = 0;
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} while (__strex(c2, first));
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#else
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__disable_irq();
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if ((cnt = *count) < size) {
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*count = cnt+1;
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c2 = (cnt = *first) + 1;
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if (c2 == size) c2 = 0;
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*first = c2;
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}
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__enable_irq ();
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#endif
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return (cnt);
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}
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static inline void rt_systick_init (void) {
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NVIC_ST_RELOAD = os_trv;
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NVIC_ST_CURRENT = 0;
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NVIC_ST_CTRL = 0x0007;
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NVIC_SYS_PRI3 |= 0xFF000000;
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}
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static inline void rt_svc_init (void) {
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#if !(__TARGET_ARCH_6S_M)
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int sh,prigroup;
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#endif
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NVIC_SYS_PRI3 |= 0x00FF0000;
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#if (__TARGET_ARCH_6S_M)
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NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
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#else
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sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
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prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
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if (prigroup >= sh) {
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sh = prigroup + 1;
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}
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NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
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#endif
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}
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extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
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extern void rt_set_PSP (U32 stack);
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extern U32 rt_get_PSP (void);
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extern void os_set_env (void);
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extern void *_alloc_box (void *box_mem);
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extern int _free_box (void *box_mem, void *box);
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extern void dbg_init (void);
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extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
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extern void dbg_task_switch (U32 task_id);
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#ifdef DBG_MSG
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#define DBG_INIT() dbg_init()
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#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
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#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
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dbg_task_switch(task_id)
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#else
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#define DBG_INIT()
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#define DBG_TASK_NOTIFY(p_tcb,create)
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#define DBG_TASK_SWITCH(task_id)
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#endif
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/*----------------------------------------------------------------------------
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* end of file
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*---------------------------------------------------------------------------*/
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