mirror of
https://github.com/FreeRTOS/FreeRTOS-Plus-TCP
synced 2025-10-23 10:07:43 +08:00
1ab6eb8885
* Update source location for coverity * Add coverage checker * Add build check with default configuration * Fix build combination and DNS error * uncrustified and fixed cmakelists * This commit updates version number in all files to Development-Branch * Update version number macros * This commit fixes a typo in version number macro * Added a 'critical section' to prevent a race condition in stream buffers * Uncrustify: triggered by comment. * Fixed unit-tests by adding mocked functions * Initial commit of file README.md * Update README.md * Fix the title of README file in coverity * Addressed issue comments * Update command * Add details about remaining exception * Move file to original location * Remove use of sudo in commands * Fix links; added coverity version note * Update README.md * Remove CMake installation instructions * Update manifest/history and copyright year * Update kernel version to 10.4.5 * Update remaining copyright year instances * Update the version number macros * Update license header titles * Remove kernel license header and add TCP header Co-authored-by: GitHub Action <action@github.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
951 lines
31 KiB
C
951 lines
31 KiB
C
/*
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* FreeRTOS+TCP <DEVELOPMENT BRANCH>
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* Copyright (C) 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://aws.amazon.com/freertos
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* http://www.FreeRTOS.org
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*/
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/* Standard includes. */
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "queue.h"
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#include "semphr.h"
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/* FreeRTOS+TCP includes. */
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#include "FreeRTOS_IP.h"
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#include "FreeRTOS_Sockets.h"
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#include "FreeRTOS_IP_Private.h"
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#include "FreeRTOS_ARP.h"
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#include "NetworkBufferManagement.h"
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#include "NetworkInterface.h"
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/* Some files from the Atmel Software Framework */
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/* gmac_SAM.[ch] is a combination of the gmac.[ch] for both SAM4E and SAME70. */
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#include "gmac_SAM.h"
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#include <sysclk.h>
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#include "phyHandling.h"
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/* This file is included to see if 'CONF_BOARD_ENABLE_CACHE' is defined. */
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#include "conf_board.h"
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/* Interrupt events to process. Currently only the Rx event is processed
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* although code for other events is included to allow for possible future
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* expansion. */
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#define EMAC_IF_RX_EVENT 1UL
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#define EMAC_IF_TX_EVENT 2UL
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#define EMAC_IF_ERR_EVENT 4UL
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#define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT )
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/* 1536 bytes is more than needed, 1524 would be enough.
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* But 1536 is a multiple of 32, which gives a great alignment for
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* cached memories. */
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#define NETWORK_BUFFER_SIZE 1536
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#ifndef EMAC_MAX_BLOCK_TIME_MS
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/* The task 'prvEMACHandlerTask()' will wake-up every 100 ms, to see
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* if something has to be done, mostly checking if the PHY has a
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* change in Link Status. */
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#define EMAC_MAX_BLOCK_TIME_MS 100ul
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#endif
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#if ( ipconfigZERO_COPY_RX_DRIVER == 0 )
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#error This driver works optimal if ipconfigZERO_COPY_RX_DRIVER is defined as 1
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#endif
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#if ( ipconfigZERO_COPY_TX_DRIVER == 0 )
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#error This driver works optimal if ipconfigZERO_COPY_TX_DRIVER is defined as 1
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#endif
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/* Default the size of the stack used by the EMAC deferred handler task to 4x
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* the size of the stack used by the idle task - but allow this to be overridden in
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* FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */
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#ifndef configEMAC_TASK_STACK_SIZE
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#define configEMAC_TASK_STACK_SIZE ( 4 * configMINIMAL_STACK_SIZE )
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#endif
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#ifndef niEMAC_HANDLER_TASK_PRIORITY
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#define niEMAC_HANDLER_TASK_PRIORITY configMAX_PRIORITIES - 1
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#endif
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#if ( __DCACHE_PRESENT != 0 ) && defined( CONF_BOARD_ENABLE_CACHE )
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#include "core_cm7.h"
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#warning This driver assumes the presence of DCACHE
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#define NETWORK_BUFFERS_CACHED 1
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#define CACHE_LINE_SIZE 32
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#define NETWORK_BUFFER_HEADER_SIZE ( ipconfigPACKET_FILLER_SIZE + 8 )
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static void cache_clean_invalidate()
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{
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/* If you application crashes here, make sure that SCB_EnableDCache() has been called. */
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SCB_CleanInvalidateDCache();
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}
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/*-----------------------------------------------------------*/
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static void cache_clean_invalidate_by_addr( uint32_t addr,
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uint32_t size )
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{
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/* SAME70 does not have clean/invalidate per area. */
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/* SCB_CleanInvalidateDCache_by_Addr( ( uint32_t * )addr, size); */
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SCB_CleanInvalidateDCache();
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}
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/*-----------------------------------------------------------*/
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static void cache_invalidate_by_addr( addr,
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size ) \
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{
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/* SAME70 does not have clean/invalidate per area. */
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/* SCB_InvalidateDCache_by_Addr( ( uint32_t * )addr, size); */
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SCB_InvalidateDCache();
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}
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/*-----------------------------------------------------------*/
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#else /* if ( __DCACHE_PRESENT != 0 ) && defined( CONF_BOARD_ENABLE_CACHE ) */
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#warning Sure there is no caching?
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#define cache_clean_invalidate() do {} while( 0 )
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#define cache_clean_invalidate_by_addr( addr, size ) do {} while( 0 )
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#define cache_invalidate_by_addr( addr, size ) do {} while( 0 )
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#endif /* if ( __DCACHE_PRESENT != 0 ) && defined( CONF_BOARD_ENABLE_CACHE ) */
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/*-----------------------------------------------------------*/
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/*
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* Update settings in GMAC for speed and duplex.
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*/
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static void prvEthernetUpdateConfig( BaseType_t xForce );
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/*
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* Access functions to the PHY's: read() and write() to be used by
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* phyHandling.c.
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*/
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static BaseType_t xPHY_Read( BaseType_t xAddress,
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BaseType_t xRegister,
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uint32_t * pulValue );
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static BaseType_t xPHY_Write( BaseType_t xAddress,
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BaseType_t xRegister,
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uint32_t ulValue );
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#if ( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 1 ) && ( ipconfigHAS_TX_CRC_OFFLOADING == 0 )
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void vGMACGenerateChecksum( uint8_t * apBuffer,
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size_t uxLength );
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#endif
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/*
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* Called from the ASF GMAC driver.
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*/
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void xRxCallback( uint32_t ulStatus );
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void xTxCallback( uint32_t ulStatus,
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uint8_t * puc_buffer );
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/*
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* A deferred interrupt handler task that processes GMAC interrupts.
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*/
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static void prvEMACHandlerTask( void * pvParameters );
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/*
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* Initialise the ASF GMAC driver.
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*/
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static BaseType_t prvGMACInit( void );
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/*
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* Try to obtain an Rx packet from the hardware.
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*/
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static uint32_t prvEMACRxPoll( void );
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/*
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* Handle transmission errors.
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*/
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static void hand_tx_errors( void );
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/*-----------------------------------------------------------*/
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/* Bit map of outstanding ETH interrupt events for processing. Currently only
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* the Rx interrupt is handled, although code is included for other events to
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* enable future expansion. */
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static volatile uint32_t ulISREvents;
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/* A copy of PHY register 1: 'PHY_REG_01_BMSR' */
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static volatile BaseType_t xGMACSwitchRequired;
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/* LLMNR multicast address. */
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static const uint8_t llmnr_mac_address[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC };
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/* The GMAC object as defined by the ASF drivers. */
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static gmac_device_t gs_gmac_dev;
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/* Holds the handle of the task used as a deferred interrupt processor. The
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* handle is used so direct notifications can be sent to the task for all EMAC/DMA
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* related interrupts. */
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TaskHandle_t xEMACTaskHandle = NULL;
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static QueueHandle_t xTxBufferQueue;
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int tx_release_count[ 4 ];
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/* xTXDescriptorSemaphore is a counting semaphore with
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* a maximum count of GMAC_TX_BUFFERS, which is the number of
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* DMA TX descriptors. */
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static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;
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/* For local use only: describe the PHY's properties: */
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const PhyProperties_t xPHYProperties =
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{
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#if ( ipconfigETHERNET_AN_ENABLE != 0 )
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.ucSpeed = PHY_SPEED_AUTO,
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.ucDuplex = PHY_DUPLEX_AUTO,
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#else
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#if ( ipconfigETHERNET_USE_100MB != 0 )
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.ucSpeed = PHY_SPEED_100,
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#else
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.ucSpeed = PHY_SPEED_10,
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#endif
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#if ( ipconfigETHERNET_USE_FULL_DUPLEX != 0 )
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.ucDuplex = PHY_DUPLEX_FULL,
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#else
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.ucDuplex = PHY_DUPLEX_HALF,
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#endif
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#endif /* if ( ipconfigETHERNET_AN_ENABLE != 0 ) */
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#if ( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 )
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.ucMDI_X = PHY_MDIX_AUTO,
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#elif ( ipconfigETHERNET_CROSSED_LINK != 0 )
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.ucMDI_X = PHY_MDIX_CROSSED,
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#else
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.ucMDI_X = PHY_MDIX_DIRECT,
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#endif
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};
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/* All PHY handling code has now been separated from the NetworkInterface.c,
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* see "../Common/phyHandling.c". */
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static EthernetPhy_t xPhyObject;
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/*-----------------------------------------------------------*/
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/*
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* GMAC interrupt handler.
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*/
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void GMAC_Handler( void )
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{
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xGMACSwitchRequired = pdFALSE;
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/* gmac_handler() may call xRxCallback() which may change
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* the value of xGMACSwitchRequired. */
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gmac_handler( &gs_gmac_dev );
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if( xGMACSwitchRequired != pdFALSE )
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{
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portEND_SWITCHING_ISR( xGMACSwitchRequired );
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}
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}
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/*-----------------------------------------------------------*/
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void xRxCallback( uint32_t ulStatus )
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{
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if( ( ( ulStatus & GMAC_RSR_REC ) != 0 ) && ( xEMACTaskHandle != NULL ) )
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{
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/* let the prvEMACHandlerTask know that there was an RX event. */
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ulISREvents |= EMAC_IF_RX_EVENT;
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/* Only an RX interrupt can wakeup prvEMACHandlerTask. */
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vTaskNotifyGiveFromISR( xEMACTaskHandle, ( BaseType_t * ) &xGMACSwitchRequired );
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}
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}
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/*-----------------------------------------------------------*/
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void returnTxBuffer( uint8_t * puc_buffer )
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{
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/* Called from a non-ISR context. */
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if( xTxBufferQueue != NULL )
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{
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xQueueSend( xTxBufferQueue, &puc_buffer, 0 );
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xTaskNotifyGive( xEMACTaskHandle );
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ulISREvents |= EMAC_IF_TX_EVENT;
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}
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}
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void xTxCallback( uint32_t ulStatus,
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uint8_t * puc_buffer )
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{
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if( ( xTxBufferQueue != NULL ) && ( xEMACTaskHandle != NULL ) )
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{
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/* let the prvEMACHandlerTask know that there was an TX event. */
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ulISREvents |= EMAC_IF_TX_EVENT;
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/* Wakeup prvEMACHandlerTask. */
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vTaskNotifyGiveFromISR( xEMACTaskHandle, ( BaseType_t * ) &xGMACSwitchRequired );
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xQueueSendFromISR( xTxBufferQueue, &puc_buffer, ( BaseType_t * ) &xGMACSwitchRequired );
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tx_release_count[ 2 ]++;
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}
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}
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/*-----------------------------------------------------------*/
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/*
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* The two standard defines 'GMAC_MAN_RW_TYPE' and 'GMAC_MAN_READ_ONLY'
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* are incorrect.
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* Therefore, use the following:
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*/
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#define GMAC_MAINTENANCE_READ_ACCESS ( 2 )
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#define GMAC_MAINTENANCE_WRITE_ACCESS ( 1 )
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static BaseType_t xPHY_Read( BaseType_t xAddress,
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BaseType_t xRegister,
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uint32_t * pulValue )
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{
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BaseType_t xReturn;
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UBaseType_t uxWasEnabled;
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/* Wait until bus idle */
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while( ( GMAC->GMAC_NSR & GMAC_NSR_IDLE ) == 0 )
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{
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}
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/* Write maintain register */
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/*
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* OP: Operation: 10 is read. 01 is write.
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*/
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uxWasEnabled = ( GMAC->GMAC_NCR & GMAC_NCR_MPE ) != 0u;
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if( uxWasEnabled == 0u )
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{
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/* Enable further GMAC maintenance. */
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GMAC->GMAC_NCR |= GMAC_NCR_MPE;
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}
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GMAC->GMAC_MAN = GMAC_MAN_WTN( GMAC_MAN_CODE_VALUE )
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| GMAC_MAN_CLTTO
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| GMAC_MAN_PHYA( xAddress )
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| GMAC_MAN_REGA( xRegister )
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| GMAC_MAN_OP( GMAC_MAINTENANCE_READ_ACCESS )
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| GMAC_MAN_DATA( ( uint16_t ) 0u );
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if( gmac_wait_phy( GMAC, MAC_PHY_RETRY_MAX ) == GMAC_TIMEOUT )
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{
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*pulValue = ( uint32_t ) 0xffffu;
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xReturn = -1;
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}
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else
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{
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/* Wait until bus idle */
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while( ( GMAC->GMAC_NSR & GMAC_NSR_IDLE ) == 0 )
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{
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}
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/* Return data */
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*pulValue = ( uint32_t ) ( GMAC->GMAC_MAN & GMAC_MAN_DATA_Msk );
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xReturn = 0;
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}
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if( uxWasEnabled == 0u )
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{
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/* Disable further GMAC maintenance. */
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GMAC->GMAC_NCR &= ~GMAC_NCR_MPE;
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}
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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static BaseType_t xPHY_Write( BaseType_t xAddress,
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BaseType_t xRegister,
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uint32_t ulValue )
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{
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BaseType_t xReturn;
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UBaseType_t uxWasEnabled;
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/* Wait until bus idle */
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while( ( GMAC->GMAC_NSR & GMAC_NSR_IDLE ) == 0 )
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{
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}
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/* Write maintain register */
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uxWasEnabled = ( GMAC->GMAC_NCR & GMAC_NCR_MPE ) != 0u;
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if( uxWasEnabled == 0u )
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{
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/* Enable further GMAC maintenance. */
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GMAC->GMAC_NCR |= GMAC_NCR_MPE;
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}
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GMAC->GMAC_MAN = GMAC_MAN_WTN( GMAC_MAN_CODE_VALUE )
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| GMAC_MAN_CLTTO
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| GMAC_MAN_PHYA( xAddress )
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| GMAC_MAN_REGA( xRegister )
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| GMAC_MAN_OP( GMAC_MAINTENANCE_WRITE_ACCESS )
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| GMAC_MAN_DATA( ( uint16_t ) ulValue );
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if( gmac_wait_phy( GMAC, MAC_PHY_RETRY_MAX ) == GMAC_TIMEOUT )
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{
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xReturn = -1;
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}
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else
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{
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xReturn = 0;
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}
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if( uxWasEnabled == 0u )
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{
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/* Disable further GMAC maintenance. */
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GMAC->GMAC_NCR &= ~GMAC_NCR_MPE;
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}
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xNetworkInterfaceInitialise( void )
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{
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const TickType_t x5_Seconds = 5000UL;
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if( xEMACTaskHandle == NULL )
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{
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prvGMACInit();
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cache_clean_invalidate();
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/* The handler task is created at the highest possible priority to
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* ensure the interrupt handler can return directly to it. */
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xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, niEMAC_HANDLER_TASK_PRIORITY, &xEMACTaskHandle );
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configASSERT( xEMACTaskHandle );
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}
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if( xTxBufferQueue == NULL )
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{
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xTxBufferQueue = xQueueCreate( GMAC_TX_BUFFERS, sizeof( void * ) );
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configASSERT( xTxBufferQueue );
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}
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if( xTXDescriptorSemaphore == NULL )
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{
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xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) GMAC_TX_BUFFERS, ( UBaseType_t ) GMAC_TX_BUFFERS );
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configASSERT( xTXDescriptorSemaphore );
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}
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/* When returning non-zero, the stack will become active and
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* start DHCP (in configured) */
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return xGetPhyLinkStatus();
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}
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/*-----------------------------------------------------------*/
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BaseType_t xGetPhyLinkStatus( void )
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{
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BaseType_t xReturn;
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if( xPhyObject.ulLinkStatusMask != 0 )
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{
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xReturn = pdPASS;
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}
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else
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{
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xReturn = pdFAIL;
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}
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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/** The GMAC TX errors to handle */
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#define GMAC_TX_ERRORS ( GMAC_TSR_TFC | GMAC_TSR_HRESP )
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static void hand_tx_errors( void )
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{
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/* Handle GMAC underrun or AHB errors. */
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if( gmac_get_tx_status( GMAC ) & GMAC_TX_ERRORS )
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{
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gmac_enable_transmit( GMAC, false );
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/* Reinit TX descriptors. */
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|
/* gmac_tx_init(ps_gmac_dev); */
|
|
gmac_reset_tx_mem( &gs_gmac_dev );
|
|
/* Clear error status. */
|
|
gmac_clear_tx_status( GMAC, GMAC_TX_ERRORS );
|
|
|
|
gmac_enable_transmit( GMAC, true );
|
|
}
|
|
}
|
|
|
|
volatile IPPacket_t * pxSendPacket;
|
|
|
|
BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor,
|
|
BaseType_t bReleaseAfterSend )
|
|
{
|
|
/* Do not wait too long for a free TX DMA buffer. */
|
|
const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u );
|
|
uint32_t ulTransmitSize;
|
|
|
|
ulTransmitSize = pxDescriptor->xDataLength;
|
|
|
|
pxSendPacket = ( IPPacket_t * ) pxDescriptor->pucEthernetBuffer;
|
|
|
|
if( ulTransmitSize > NETWORK_BUFFER_SIZE )
|
|
{
|
|
ulTransmitSize = NETWORK_BUFFER_SIZE;
|
|
}
|
|
|
|
/* A do{}while(0) loop is introduced to allow the use of multiple break
|
|
* statement. */
|
|
do
|
|
{
|
|
if( xPhyObject.ulLinkStatusMask == 0ul )
|
|
{
|
|
/* Do not attempt to send packets as long as the Link Status is low. */
|
|
break;
|
|
}
|
|
|
|
if( xTXDescriptorSemaphore == NULL )
|
|
{
|
|
/* Semaphore has not been created yet? */
|
|
break;
|
|
}
|
|
|
|
hand_tx_errors();
|
|
|
|
if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )
|
|
{
|
|
/* Time-out waiting for a free TX descriptor. */
|
|
tx_release_count[ 3 ]++;
|
|
break;
|
|
}
|
|
|
|
#if ( ipconfigZERO_COPY_TX_DRIVER != 0 )
|
|
{
|
|
/* Confirm that the pxDescriptor may be kept by the driver. */
|
|
configASSERT( bReleaseAfterSend != pdFALSE );
|
|
}
|
|
#endif /* ipconfigZERO_COPY_TX_DRIVER */
|
|
|
|
#if ( NETWORK_BUFFERS_CACHED != 0 )
|
|
{
|
|
uint32_t xlength = CACHE_LINE_SIZE * ( ( ulTransmitSize + NETWORK_BUFFER_HEADER_SIZE + CACHE_LINE_SIZE - 1 ) / CACHE_LINE_SIZE );
|
|
uint32_t xAddress = ( uint32_t ) ( pxDescriptor->pucEthernetBuffer - NETWORK_BUFFER_HEADER_SIZE );
|
|
cache_clean_invalidate_by_addr( xAddress, xlength );
|
|
}
|
|
#endif
|
|
|
|
gmac_dev_write( &gs_gmac_dev, ( void * ) pxDescriptor->pucEthernetBuffer, pxDescriptor->xDataLength );
|
|
|
|
#if ( ipconfigZERO_COPY_TX_DRIVER != 0 )
|
|
{
|
|
/* Confirm that the pxDescriptor may be kept by the driver. */
|
|
bReleaseAfterSend = pdFALSE;
|
|
}
|
|
#endif /* ipconfigZERO_COPY_TX_DRIVER */
|
|
/* Not interested in a call-back after TX. */
|
|
iptraceNETWORK_INTERFACE_TRANSMIT();
|
|
} while( ipFALSE_BOOL );
|
|
|
|
if( bReleaseAfterSend != pdFALSE )
|
|
{
|
|
vReleaseNetworkBufferAndDescriptor( pxDescriptor );
|
|
}
|
|
|
|
return pdTRUE;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvGMACInit( void )
|
|
{
|
|
uint32_t ncfgr;
|
|
|
|
gmac_options_t gmac_option;
|
|
|
|
gmac_enable_management( GMAC, true );
|
|
/* Enable further GMAC maintenance. */
|
|
GMAC->GMAC_NCR |= GMAC_NCR_MPE;
|
|
|
|
memset( &gmac_option, '\0', sizeof( gmac_option ) );
|
|
gmac_option.uc_copy_all_frame = 0;
|
|
gmac_option.uc_no_boardcast = 0;
|
|
memcpy( gmac_option.uc_mac_addr, ipLOCAL_MAC_ADDRESS, sizeof( gmac_option.uc_mac_addr ) );
|
|
|
|
gs_gmac_dev.p_hw = GMAC;
|
|
gmac_dev_init( GMAC, &gs_gmac_dev, &gmac_option );
|
|
|
|
NVIC_SetPriority( GMAC_IRQn, configMAC_INTERRUPT_PRIORITY );
|
|
NVIC_EnableIRQ( GMAC_IRQn );
|
|
|
|
{
|
|
/* Set MDC clock divider. */
|
|
gmac_set_mdc_clock( GMAC, sysclk_get_cpu_hz() );
|
|
|
|
vPhyInitialise( &xPhyObject, xPHY_Read, xPHY_Write );
|
|
xPhyDiscover( &xPhyObject );
|
|
xPhyConfigure( &xPhyObject, &xPHYProperties );
|
|
|
|
/* For a reset / reconfigure of the EMAC. */
|
|
prvEthernetUpdateConfig( pdTRUE );
|
|
|
|
/* Select Media Independent Interface type */
|
|
#if ( SAME70 != 0 )
|
|
{
|
|
/* Selecting RMII mode. */
|
|
GMAC->GMAC_UR &= ~GMAC_UR_RMII;
|
|
}
|
|
#else
|
|
{
|
|
gmac_select_mii_mode( GMAC, ETH_PHY_MODE );
|
|
}
|
|
#endif
|
|
|
|
gmac_enable_transmit( GMAC, true );
|
|
gmac_enable_receive( GMAC, true );
|
|
}
|
|
|
|
gmac_enable_management( GMAC, true );
|
|
|
|
gmac_set_address( GMAC, 1, ( uint8_t * ) llmnr_mac_address );
|
|
|
|
gmac_enable_management( GMAC, false );
|
|
/* Disable further GMAC maintenance. */
|
|
GMAC->GMAC_NCR &= ~GMAC_NCR_MPE;
|
|
|
|
return 1;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvEthernetUpdateConfig( BaseType_t xForce )
|
|
{
|
|
FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02lX Force %d\n",
|
|
xPhyObject.ulLinkStatusMask,
|
|
( int ) xForce ) );
|
|
|
|
if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) )
|
|
{
|
|
#if ( ipconfigETHERNET_AN_ENABLE != 0 )
|
|
{
|
|
UBaseType_t uxWasEnabled;
|
|
|
|
/* Restart the auto-negotiation. */
|
|
uxWasEnabled = ( GMAC->GMAC_NCR & GMAC_NCR_MPE ) != 0u;
|
|
|
|
if( uxWasEnabled == 0u )
|
|
{
|
|
/* Enable further GMAC maintenance. */
|
|
GMAC->GMAC_NCR |= GMAC_NCR_MPE;
|
|
}
|
|
|
|
xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) );
|
|
|
|
/* Configure the MAC with the Duplex Mode fixed by the
|
|
* auto-negotiation process. */
|
|
if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL )
|
|
{
|
|
gmac_enable_full_duplex( GMAC, pdTRUE );
|
|
}
|
|
else
|
|
{
|
|
gmac_enable_full_duplex( GMAC, pdFALSE );
|
|
}
|
|
|
|
/* Configure the MAC with the speed fixed by the
|
|
* auto-negotiation process. */
|
|
if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 )
|
|
{
|
|
gmac_set_speed( GMAC, pdFALSE );
|
|
}
|
|
else
|
|
{
|
|
gmac_set_speed( GMAC, pdTRUE );
|
|
}
|
|
|
|
if( uxWasEnabled == 0u )
|
|
{
|
|
/* Enable further GMAC maintenance. */
|
|
GMAC->GMAC_NCR &= ~GMAC_NCR_MPE;
|
|
}
|
|
}
|
|
#else /* if ( ipconfigETHERNET_AN_ENABLE != 0 ) */
|
|
{
|
|
if( xPHYProperties.ucDuplex == PHY_DUPLEX_FULL )
|
|
{
|
|
xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL;
|
|
gmac_enable_full_duplex( GMAC, pdTRUE );
|
|
}
|
|
else
|
|
{
|
|
xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF;
|
|
gmac_enable_full_duplex( GMAC, pdFALSE );
|
|
}
|
|
|
|
if( xPHYProperties.ucSpeed == PHY_SPEED_100 )
|
|
{
|
|
xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100;
|
|
gmac_set_speed( GMAC, pdTRUE );
|
|
}
|
|
else
|
|
{
|
|
xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10;
|
|
gmac_set_speed( GMAC, pdFALSE );
|
|
}
|
|
|
|
xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO;
|
|
|
|
/* Use predefined (fixed) configuration. */
|
|
xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) );
|
|
}
|
|
#endif /* if ( ipconfigETHERNET_AN_ENABLE != 0 ) */
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vGMACGenerateChecksum( uint8_t * pucBuffer,
|
|
size_t uxLength )
|
|
{
|
|
ProtocolPacket_t * xProtPacket = ( ProtocolPacket_t * ) pucBuffer;
|
|
|
|
if( xProtPacket->xTCPPacket.xEthernetHeader.usFrameType == ipIPv4_FRAME_TYPE )
|
|
{
|
|
IPHeader_t * pxIPHeader = &( xProtPacket->xTCPPacket.xIPHeader );
|
|
|
|
/* Calculate the IP header checksum. */
|
|
pxIPHeader->usHeaderChecksum = 0x00;
|
|
pxIPHeader->usHeaderChecksum = usGenerateChecksum( 0U, ( uint8_t * ) &( pxIPHeader->ucVersionHeaderLength ), ipSIZE_OF_IPv4_HEADER );
|
|
pxIPHeader->usHeaderChecksum = ~FreeRTOS_htons( pxIPHeader->usHeaderChecksum );
|
|
|
|
/* Calculate the TCP checksum for an outgoing packet. */
|
|
usGenerateProtocolChecksum( pucBuffer, uxLength, pdTRUE );
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static uint32_t prvEMACRxPoll( void )
|
|
{
|
|
unsigned char * pucUseBuffer;
|
|
uint32_t ulReceiveCount, ulResult, ulReturnValue = 0;
|
|
static NetworkBufferDescriptor_t * pxNextNetworkBufferDescriptor = NULL;
|
|
const UBaseType_t xMinDescriptorsToLeave = 2UL;
|
|
const TickType_t xBlockTime = pdMS_TO_TICKS( 100UL );
|
|
static IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL };
|
|
uint8_t * pucDMABuffer = NULL;
|
|
|
|
for( ; ; )
|
|
{
|
|
/* If pxNextNetworkBufferDescriptor was not left pointing at a valid
|
|
* descriptor then allocate one now. */
|
|
if( ( pxNextNetworkBufferDescriptor == NULL ) && ( uxGetNumberOfFreeNetworkBuffers() > xMinDescriptorsToLeave ) )
|
|
{
|
|
pxNextNetworkBufferDescriptor = pxGetNetworkBufferWithDescriptor( ipTOTAL_ETHERNET_FRAME_SIZE, xBlockTime );
|
|
}
|
|
|
|
if( pxNextNetworkBufferDescriptor != NULL )
|
|
{
|
|
/* Point pucUseBuffer to the buffer pointed to by the descriptor. */
|
|
pucUseBuffer = ( unsigned char * ) ( pxNextNetworkBufferDescriptor->pucEthernetBuffer - ipconfigPACKET_FILLER_SIZE );
|
|
}
|
|
else
|
|
{
|
|
/* As long as pxNextNetworkBufferDescriptor is NULL, the incoming
|
|
* messages will be flushed and ignored. */
|
|
pucUseBuffer = NULL;
|
|
}
|
|
|
|
/* Read the next packet from the hardware into pucUseBuffer. */
|
|
ulResult = gmac_dev_read( &gs_gmac_dev, pucUseBuffer, ipTOTAL_ETHERNET_FRAME_SIZE, &ulReceiveCount, &pucDMABuffer );
|
|
|
|
if( ( ulResult != GMAC_OK ) || ( ulReceiveCount == 0 ) )
|
|
{
|
|
/* No data from the hardware. */
|
|
break;
|
|
}
|
|
|
|
if( pxNextNetworkBufferDescriptor == NULL )
|
|
{
|
|
/* Data was read from the hardware, but no descriptor was available
|
|
* for it, so it will be dropped. */
|
|
iptraceETHERNET_RX_EVENT_LOST();
|
|
continue;
|
|
}
|
|
|
|
iptraceNETWORK_INTERFACE_RECEIVE();
|
|
#if ( ipconfigZERO_COPY_RX_DRIVER != 0 )
|
|
{
|
|
pxNextNetworkBufferDescriptor = pxPacketBuffer_to_NetworkBuffer( pucDMABuffer );
|
|
|
|
if( pxNextNetworkBufferDescriptor == NULL )
|
|
{
|
|
/* Strange: can not translate from a DMA buffer to a Network Buffer. */
|
|
break;
|
|
}
|
|
}
|
|
#endif /* ipconfigZERO_COPY_RX_DRIVER */
|
|
|
|
pxNextNetworkBufferDescriptor->xDataLength = ( size_t ) ulReceiveCount;
|
|
xRxEvent.pvData = ( void * ) pxNextNetworkBufferDescriptor;
|
|
|
|
/* Send the descriptor to the IP task for processing. */
|
|
if( xSendEventStructToIPTask( &xRxEvent, xBlockTime ) != pdTRUE )
|
|
{
|
|
/* The buffer could not be sent to the stack so must be released
|
|
* again. */
|
|
vReleaseNetworkBufferAndDescriptor( pxNextNetworkBufferDescriptor );
|
|
iptraceETHERNET_RX_EVENT_LOST();
|
|
FreeRTOS_printf( ( "prvEMACRxPoll: Can not queue return packet!\n" ) );
|
|
}
|
|
|
|
/* Now the buffer has either been passed to the IP-task,
|
|
* or it has been released in the code above. */
|
|
pxNextNetworkBufferDescriptor = NULL;
|
|
ulReturnValue++;
|
|
}
|
|
|
|
return ulReturnValue;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
extern uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * NETWORK_BUFFER_SIZE ];
|
|
void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] )
|
|
{
|
|
uint8_t * ucRAMBuffer = ucNetworkPackets;
|
|
uint32_t ulIndex;
|
|
|
|
for( ulIndex = 0; ulIndex < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ulIndex++ )
|
|
{
|
|
pxNetworkBuffers[ ulIndex ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING;
|
|
*( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ulIndex ] ) );
|
|
ucRAMBuffer += NETWORK_BUFFER_SIZE;
|
|
}
|
|
|
|
cache_clean_invalidate();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvEMACHandlerTask( void * pvParameters )
|
|
{
|
|
UBaseType_t uxCount;
|
|
UBaseType_t uxLowestSemCount = 0;
|
|
|
|
#if ( ipconfigZERO_COPY_TX_DRIVER != 0 )
|
|
NetworkBufferDescriptor_t * pxBuffer;
|
|
#endif
|
|
uint8_t * pucBuffer;
|
|
BaseType_t xResult = 0;
|
|
uint32_t xStatus;
|
|
const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( EMAC_MAX_BLOCK_TIME_MS );
|
|
|
|
/* Remove compiler warnings about unused parameters. */
|
|
( void ) pvParameters;
|
|
|
|
configASSERT( xEMACTaskHandle );
|
|
|
|
for( ; ; )
|
|
{
|
|
xResult = 0;
|
|
|
|
#if ( ipconfigHAS_PRINTF != 0 )
|
|
{
|
|
/* Call a function that monitors resources: the amount of free network
|
|
* buffers and the amount of free space on the heap. See FreeRTOS_IP.c
|
|
* for more detailed comments. */
|
|
vPrintResourceStats();
|
|
|
|
if( xTXDescriptorSemaphore != NULL )
|
|
{
|
|
UBaseType_t uxCurrentSemCount = uxSemaphoreGetCount( xTXDescriptorSemaphore );
|
|
|
|
if( uxLowestSemCount > uxCurrentSemCount )
|
|
{
|
|
uxLowestSemCount = uxCurrentSemCount;
|
|
FreeRTOS_printf( ( "TX DMA buffers: lowest %lu\n", uxLowestSemCount ) );
|
|
}
|
|
}
|
|
}
|
|
#endif /* ( ipconfigHAS_PRINTF != 0 ) */
|
|
|
|
if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 )
|
|
{
|
|
/* No events to process now, wait for the next. */
|
|
ulTaskNotifyTake( pdFALSE, ulMaxBlockTime );
|
|
}
|
|
|
|
if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 )
|
|
{
|
|
ulISREvents &= ~EMAC_IF_RX_EVENT;
|
|
|
|
/* Wait for the EMAC interrupt to indicate that another packet has been
|
|
* received. */
|
|
xResult = prvEMACRxPoll();
|
|
}
|
|
|
|
if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 )
|
|
{
|
|
/* Future extension: code to release TX buffers if zero-copy is used. */
|
|
ulISREvents &= ~EMAC_IF_TX_EVENT;
|
|
|
|
while( xQueueReceive( xTxBufferQueue, &pucBuffer, 0 ) != pdFALSE )
|
|
{
|
|
#if ( ipconfigZERO_COPY_TX_DRIVER != 0 )
|
|
{
|
|
pxBuffer = pxPacketBuffer_to_NetworkBuffer( pucBuffer );
|
|
|
|
if( pxBuffer != NULL )
|
|
{
|
|
vReleaseNetworkBufferAndDescriptor( pxBuffer );
|
|
tx_release_count[ 0 ]++;
|
|
}
|
|
else
|
|
{
|
|
tx_release_count[ 1 ]++;
|
|
}
|
|
}
|
|
#else /* if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) */
|
|
{
|
|
tx_release_count[ 0 ]++;
|
|
}
|
|
#endif /* if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) */
|
|
uxCount = uxQueueMessagesWaiting( ( QueueHandle_t ) xTXDescriptorSemaphore );
|
|
|
|
if( uxCount < GMAC_TX_BUFFERS )
|
|
{
|
|
/* Tell the counting semaphore that one more TX descriptor is available. */
|
|
xSemaphoreGive( xTXDescriptorSemaphore );
|
|
}
|
|
}
|
|
}
|
|
|
|
if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 )
|
|
{
|
|
/* Future extension: logging about errors that occurred. */
|
|
ulISREvents &= ~EMAC_IF_ERR_EVENT;
|
|
}
|
|
|
|
gmac_enable_management( GMAC, true );
|
|
|
|
if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 )
|
|
{
|
|
/* Something has changed to a Link Status, need re-check. */
|
|
prvEthernetUpdateConfig( pdFALSE );
|
|
}
|
|
|
|
gmac_enable_management( GMAC, false );
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|