初始化工程目录

.gitignore

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+build
+.xmake

.gitmodules

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+[submodule "sdk"]
+	path = sdk
+	url = https://gitee.com/openLuat/luatos-soc-2022.git

LICENSE

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+MIT License
+
+Copyright (c) 2023 何亚红
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

ReadMe.md

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+# 简介
+
+这是一个开发[Air780E](https://air780e.cn)的Demo.
+
+测试硬件采用合宙EVB-780E-H开发板。
+
+## 已知问题
+
+- C++静态类的构造函数不可用。
+- C++全局类的构造函数不可用。
+- C++异常可能出现问题(不确定),可编译但需要谨慎使用（若必须使用，请充分测试）。
+
+## 源代码下载
+
+由于本源代码包含第三方源代码,故直接下载可能有部分源代码缺失，需要通过以下方法解决:
+
+- 在进行git clone 使用--recurse-submodules参数。
+
+- 若已通过git clone下载,则在源代码目录中执行以下命令下载子模块:
+
+  ```bash
+   git submodule update --init --recursive
+  ```
+
+# 编译
+
+- 操作系统: Windows 
+
+## 编译准备
+
+- 本工程采用xmake管理编译树，因此需要安装好xmake，其官方网址为https://xmake.io。
+- 编译过程中可能需要下载文件，因此需要在整个编译过程中保持网络畅通。
+
+## 脚本说明
+
+- build.bat:构建工程文件并编译。
+- clean.bat:清理构建文件
+
+## 固件烧录
+
+正常编译完成后,最终的固件在 sdk\out目录下的子目录中,后缀名为binpkg。
+
+此时可直接使用合宙官方的Luatools的固件下载烧录:
+
+- USB BOOT烧录。使用USB连接PC，按下BOOT按键后进行一次复位,然后直接下载。
+
+
+

app/RTE_Device.h

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+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+#include "ec618.h"
+
+/*  Peripheral IO Mode Select, Must Configure First !!!
+    Note, when receiver works in DMA_MODE, interrupt is also enabled to transfer tailing bytes.
+*/
+
+#define POLLING_MODE            0x1
+#define DMA_MODE                0x2
+#define IRQ_MODE                0x3
+#define UNILOG_MODE             0x4
+
+#define RTE_UART0_TX_IO_MODE    UNILOG_MODE
+#define RTE_UART0_RX_IO_MODE    IRQ_MODE
+#define USART0_RX_TRIG_LVL      (30)
+
+#define RTE_UART1_TX_IO_MODE    DMA_MODE
+#define RTE_UART1_RX_IO_MODE    DMA_MODE
+
+#define RTE_UART2_TX_IO_MODE    POLLING_MODE
+#define RTE_UART2_RX_IO_MODE    DMA_MODE
+
+#define RTE_SPI0_IO_MODE        POLLING_MODE
+
+#define RTE_SPI1_IO_MODE        POLLING_MODE
+
+#define RTE_I2C0_IO_MODE        POLLING_MODE
+#define RTE_I2C1_IO_MODE        POLLING_MODE
+
+
+// I2C0 (Inter-integrated Circuit Interface) [Driver_I2C0]
+// Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+#define RTE_I2C0                        1
+
+// { PAD_PIN28},  // 0 : gpio13 / 2 : I2C0 SCL
+// { PAD_PIN27},  // 0 : gpio12 / 2 : I2C0 SDA
+#define RTE_I2C0_SCL_BIT                28			// AUDIO use 28
+#define RTE_I2C0_SCL_FUNC               PAD_MUX_ALT2
+
+#define RTE_I2C0_SDA_BIT                27			// AUDIO use 27
+#define RTE_I2C0_SDA_FUNC               PAD_MUX_ALT2
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_I2C0_DMA_TX_EN              0
+#define RTE_I2C0_DMA_TX_REQID           DMA_REQUEST_I2C0_TX
+//   Rx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_I2C0_DMA_RX_EN              0
+#define RTE_I2C0_DMA_RX_REQID           DMA_REQUEST_I2C0_RX
+
+// I2C1 (Inter-integrated Circuit Interface) [Driver_I2C1]
+// Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define RTE_I2C1                        1
+
+// { PAD_PIN20},  // 0 : gpio5  / 2 : I2C1 SCL
+// { PAD_PIN19},  // 0 : gpio4  / 2 : I2C1 SDA
+#define RTE_I2C1_SCL_BIT                20
+#define RTE_I2C1_SCL_FUNC               PAD_MUX_ALT2
+
+#define RTE_I2C1_SDA_BIT                19
+#define RTE_I2C1_SDA_FUNC               PAD_MUX_ALT2
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_I2C1_DMA_TX_EN              1
+#define RTE_I2C1_DMA_TX_REQID           DMA_REQUEST_I2C1_TX
+//   Rx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_I2C1_DMA_RX_EN              1
+#define RTE_I2C1_DMA_RX_REQID           DMA_REQUEST_I2C1_RX
+
+
+// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0]
+// Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define RTE_UART0_CTS_PIN_EN            0
+#define RTE_UART0_RTS_PIN_EN            0
+
+// { PAD_PIN27},  // 0 : gpio12 / 3 : UART0 RTSn
+// { PAD_PIN28},  // 0 : gpio13 / 3 : UART0 CTSn
+// { PAD_PIN29},  // 0 : gpio14 / 3 : UART0 RXD
+// { PAD_PIN30},  // 0 : gpio15 / 3 : UART0 TXD
+#define RTE_UART0_RTS_BIT               27
+#define RTE_UART0_RTS_FUNC              PAD_MUX_ALT3
+
+#define RTE_UART0_CTS_BIT               28
+#define RTE_UART0_CTS_FUNC              PAD_MUX_ALT3
+
+#define RTE_UART0_RX_BIT                29
+#define RTE_UART0_RX_FUNC               PAD_MUX_ALT3
+
+#define RTE_UART0_TX_BIT                30
+#define RTE_UART0_TX_FUNC               PAD_MUX_ALT3
+
+// DMA
+//  Tx
+//    Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART0_DMA_TX_REQID          DMA_REQUEST_USART0_TX
+//  Rx
+//    Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART0_DMA_RX_REQID          DMA_REQUEST_USART0_RX
+
+// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+// Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define RTE_UART1_CTS_PIN_EN            0
+#define RTE_UART1_RTS_PIN_EN            0
+
+// { PAD_PIN31},  // 0 : gpio16  / 1 : UART1 RTS
+// { PAD_PIN32},  // 0 : gpio17  / 1 : UART1 CTS
+// { PAD_PIN33},  // 0 : gpio18  / 1 : UART1 RXD
+// { PAD_PIN34},  // 0 : gpio19  / 1 : UART1 TXD
+#define RTE_UART1_RTS_BIT               31
+#define RTE_UART1_RTS_FUNC              PAD_MUX_ALT1
+
+#define RTE_UART1_CTS_BIT               32
+#define RTE_UART1_CTS_FUNC              PAD_MUX_ALT1
+
+#define RTE_UART1_RX_BIT                33
+#define RTE_UART1_RX_FUNC               PAD_MUX_ALT1
+
+#define RTE_UART1_TX_BIT                34
+#define RTE_UART1_TX_FUNC               PAD_MUX_ALT1
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART1_DMA_TX_REQID          DMA_REQUEST_USART1_TX
+//   Rx
+//     Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART1_DMA_RX_REQID          DMA_REQUEST_USART1_RX
+
+// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2]
+// Configuration settings for Driver_USART2 in component ::Drivers:USART
+#define RTE_UART2_CTS_PIN_EN            0
+#define RTE_UART2_RTS_PIN_EN            0
+
+// { PAD_PIN25},  // 0 : gpio10 / 3 : UART2 RXD
+// { PAD_PIN26},  // 0 : gpio11 / 3 : UART2 TXD
+#define RTE_UART2_RX_BIT                25
+#define RTE_UART2_RX_FUNC               PAD_MUX_ALT3
+
+#define RTE_UART2_TX_BIT                26
+#define RTE_UART2_TX_FUNC               PAD_MUX_ALT3
+
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART2_DMA_TX_REQID          DMA_REQUEST_USART2_TX
+//   Rx
+//     Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_UART2_DMA_RX_REQID          DMA_REQUEST_USART2_RX
+
+// SPI0 (Serial Peripheral Interface) [Driver_SPI0]
+// Configuration settings for Driver_SPI0 in component ::Drivers:SPI
+#define RTE_SPI0                        1
+
+// { PAD_PIN23},  // 0 : gpio8  / 1 : SPI0 SSn
+// { PAD_PIN24},  // 0 : gpio9  / 1 : SPI0 MOSI
+// { PAD_PIN25},  // 0 : gpio10 / 1 : SPI0 MISO
+// { PAD_PIN26},  // 0 : gpio11 / 1 : SPI0 SCLK
+#define RTE_SPI0_SSN_BIT                23
+#define RTE_SPI0_SSN_FUNC               PAD_MUX_ALT1
+
+#define RTE_SPI0_MOSI_BIT               24
+#define RTE_SPI0_MOSI_FUNC              PAD_MUX_ALT1
+
+#define RTE_SPI0_MISO_BIT               25
+#define RTE_SPI0_MISO_FUNC              PAD_MUX_ALT1
+
+#define RTE_SPI0_SCLK_BIT               26
+#define RTE_SPI0_SCLK_FUNC              PAD_MUX_ALT1
+
+#define RTE_SPI0_SSN_GPIO_INSTANCE      0
+#define RTE_SPI0_SSN_GPIO_INDEX         8
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_SPI0_DMA_TX_REQID           DMA_REQUEST_SPI0_TX
+
+//   Rx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_SPI0_DMA_RX_REQID           DMA_REQUEST_SPI0_RX
+
+// SPI1 (Serial Peripheral Interface) [Driver_SPI1]
+// Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define RTE_SPI1                        0
+
+// { PAD_PIN27},  // 0 : gpio12  / 1 : SPI1 SSn
+// { PAD_PIN28},  // 0 : gpio13  / 1 : SPI1 MOSI
+// { PAD_PIN29},  // 0 : gpio14  / 1 : SPI1 MISO
+// { PAD_PIN30},  // 0 : gpio15  / 1 : SPI1 SCLK
+// { PAD_PIN31},  // 0 : gpio16  / 4 : SPI1 SSn1
+#define RTE_SPI1_SSN_BIT                27
+#define RTE_SPI1_SSN_FUNC               PAD_MUX_ALT1
+
+#define RTE_SPI1_MOSI_BIT               28
+#define RTE_SPI1_MOSI_FUNC              PAD_MUX_ALT1
+
+#define RTE_SPI1_MISO_BIT               29
+#define RTE_SPI1_MISO_FUNC              PAD_MUX_ALT1
+
+#define RTE_SPI1_SCLK_BIT               30
+#define RTE_SPI1_SCLK_FUNC              PAD_MUX_ALT1
+
+#define RTE_SPI1_SSN_GPIO_INSTANCE      0
+#define RTE_SPI1_SSN_GPIO_INDEX         12
+
+#define RTE_SPI1_SSN1_BIT               31
+#define RTE_SPI1_SSN1_FUNC              PAD_MUX_ALT4
+
+// DMA
+//   Tx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_SPI1_DMA_TX_REQID           DMA_REQUEST_SPI1_TX
+
+//   Rx
+//     Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+#define RTE_SPI1_DMA_RX_REQID           DMA_REQUEST_SPI1_RX
+
+
+// PWM0 Controller [Driver_PWM0]
+// Configuration settings for Driver_PWM0 in component ::Drivers:PWM
+#define RTE_PWM                         1
+
+#define EFUSE_INIT_MODE POLLING_MODE
+#define L2CTLS_INIT_MODE POLLING_MODE
+
+#define FLASH_BARE_RW_MODE 1
+
+
+
+
+
+#define RTE_UART0                       1
+#define RTE_UART1                       1
+#define RTE_UART2                       1
+/* to enable external thermal */
+#define EXTERNAL_NTC_EXIST              0
+
+
+#if (RTE_UART1 == 1)
+#define UART1_DTR_PAD_INDEX             26     // GPIO11
+#define UART1_DTR_GPIO_INSTANCE         0
+#define UART1_DTR_GPIO_PIN              11
+
+#define UART1_RI_PAD_INDEX              44     // AONIO 4 = GPIO24
+#define UART1_RI_GPIO_INSTANCE          1
+#define UART1_RI_GPIO_PIN               8
+#define UART1_RI_PWM_INSTANCE           1
+#define UART1_RI_PWM_CLK_ID             FCLK_TIMER1
+#define UART1_RI_PWM_CLK_SEL            FCLK_TIMER1_SEL_26M
+
+#define UART1_DCD_PAD_INDEX             45     // AONIO 5 = GPIO25
+#define UART1_DCD_GPIO_INSTANCE         1
+#define UART1_DCD_GPIO_PIN              9
+#endif
+
+#if (RTE_UART2 == 1)
+#define UART2_DTR_PAD_INDEX             25     // GPIO10
+#define UART2_DTR_GPIO_INSTANCE         0
+#define UART2_DTR_GPIO_PIN              10
+
+#define UART2_RI_PAD_INDEX              43     // AONIO 3 = GPIO23
+#define UART2_RI_GPIO_INSTANCE          1
+#define UART2_RI_GPIO_PIN               7
+#define UART2_RI_PWM_INSTANCE           0
+#define UART2_RI_PWM_CLK_ID             FCLK_TIMER0
+#define UART2_RI_PWM_CLK_SEL            FCLK_TIMER0_SEL_26M
+
+#define UART2_DCD_PAD_INDEX             47     // AONIO 7 = GPIO27
+#define UART2_DCD_GPIO_INSTANCE         1
+#define UART2_DCD_GPIO_PIN              11
+#endif
+
+
+#define NETLIGHT_PAD_INDEX              46     // AONIO 6 = GPIO26
+#define NETLIGHT_PAD_ALT_FUNC           PAD_MUX_ALT5
+#define NETLIGHT_PWM_INSTANCE           3
+
+//USIM1 OPTION1
+#define USIM1_URST_OP1_PAD_INDEX             19     // GPIO4
+#define USIM1_URST_OP1_GPIO_INSTANCE         0
+#define USIM1_URST_OP1_GPIO_PIN              4
+#define USIM1_UCLK_OP1_PAD_INDEX             20     // GPIO5
+#define USIM1_UCLK_OP1_GPIO_INSTANCE         0
+#define USIM1_UCLK_OP1_GPIO_PIN              5
+#define USIM1_UIO_OP1_PAD_INDEX              21     // GPIO6
+#define USIM1_UIO_OP1_GPIO_INSTANCE          0
+#define USIM1_UIO_OP1_GPIO_PIN               6
+
+//USIM1 OPTION2
+#define USIM1_UIO_OP2_PAD_INDEX              27     // GPIO12
+#define USIM1_UIO_OP2_GPIO_INSTANCE          0
+#define USIM1_UIO_OP2_GPIO_PIN               12
+#define USIM1_URST_OP2_PAD_INDEX             28     // GPIO13
+#define USIM1_URST_OP2_GPIO_INSTANCE         0
+#define USIM1_URST_OP2_GPIO_PIN              13
+#define USIM1_UCLK_OP2_PAD_INDEX             29     // GPIO14
+#define USIM1_UCLK_OP2_GPIO_INSTANCE         0
+#define USIM1_UCLK_OP2_GPIO_PIN              14
+
+//USIM1 clock latched by AONIO, for example, use AONIO-6 test on EVB
+#define AONIO_6_PAD_INDEX        46     // AONIO 6 = GPIO26
+#define AONIO_6_GPIO_INSTANCE    1
+#define AONIO_6_GPIO_PIN         10
+
+#define RTE_CSPI0                       0
+
+#define RTE_CSPI0_MCLK_PAD_ADDR         39
+#define RTE_CSPI0_MCLK_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI0_PCLK_PAD_ADDR         35
+#define RTE_CSPI0_PCLK_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI0_CS_PAD_ADDR           36
+#define RTE_CSPI0_CS_FUNC               PAD_MUX_ALT1
+
+#define RTE_CSPI0_SDO0_PAD_ADDR         37
+#define RTE_CSPI0_SDO0_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI0_SDO1_PAD_ADDR         38
+#define RTE_CSPI0_SDO1_FUNC             PAD_MUX_ALT1
+
+// DMA CSPI0 Request ID
+#define RTE_CSPI0_DMA_RX_REQID          DMA_REQUEST_I2S0_RX
+
+// CSPI1 Configuration
+#define RTE_CSPI1                       1
+
+#define RTE_CSPI1_MCLK_PAD_ADDR         18
+#define RTE_CSPI1_MCLK_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI1_PCLK_PAD_ADDR         19
+#define RTE_CSPI1_PCLK_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI1_CS_PAD_ADDR           20
+#define RTE_CSPI1_CS_FUNC               PAD_MUX_ALT1
+
+#define RTE_CSPI1_SDO0_PAD_ADDR         21
+#define RTE_CSPI1_SDO0_FUNC             PAD_MUX_ALT1
+
+#define RTE_CSPI1_SDO1_PAD_ADDR         22
+#define RTE_CSPI1_SDO1_FUNC             PAD_MUX_ALT1
+
+// DMA CSPI1 Request ID
+#define RTE_CSPI1_DMA_RX_REQID          DMA_REQUEST_I2S1_RX
+
+#endif  /* __RTE_DEVICE_H */

app/main.c

@@ -0,0 +1,69 @@
+#include "luat_network_adapter.h"
+#include "common_api.h"
+#include "luat_debug.h"
+#include "luat_rtos.h"
+#include "luat_mobile.h"
+#include "net_lwip.h"
+#include "luat_mem.h"
+#include "luat_uart.h"
+#include "main.h"
+
+
+
+void main_task_sleep(uint32_t timeout_ms)
+{
+    luat_rtos_task_sleep(timeout_ms);
+}
+
+void * main_malloc(size_t bytes)
+{
+    return luat_heap_malloc(bytes);
+}
+
+void main_free(void *ptr)
+{
+    luat_heap_free(ptr);
+}
+
+int main_debug_print(const char * fmt,...)
+{
+    va_list ap;
+    va_start(ap, fmt);
+    int ret=soc_vsprintf(0, fmt, ap);
+    va_end(ap);
+    return ret;
+}
+
+static luat_rtos_task_handle main_task_handle;
+
+void main_init(void)
+{
+
+    main_debug_print("main init start!");
+
+    {
+        //初始化C++
+        typedef void(*pfunc)();
+        extern pfunc __ctors_start__[];
+        extern pfunc __ctors_end__[];
+        pfunc *p=NULL;
+        for (p = __ctors_start__; p < __ctors_end__; p++)
+        {
+            if(p!=NULL)
+            {
+                (*p)();
+            }
+        }
+    }
+
+    //初始化蜂窝网络
+    net_lwip_init();
+    net_lwip_register_adapter(NW_ADAPTER_INDEX_LWIP_GPRS);
+    network_register_set_default(NW_ADAPTER_INDEX_LWIP_GPRS);
+
+    //创建主任务
+    luat_rtos_task_create(&main_task_handle,8192,10,"main",main_task,NULL,16);
+
+}
+
+INIT_TASK_EXPORT(main_init, "1");

app/main.cpp

@@ -0,0 +1,40 @@
+#include "main.h"
+
+void main_task(void *param)
+{
+    main_debug_print("main start!");
+
+    while(true)
+    {
+        main_task_sleep(1000);
+        main_debug_print("main loop!");
+    }
+}
+
+/*
+  重载相关函数
+*/
+void *operator new(size_t size)
+{
+    return main_malloc(size);
+}
+
+void *operator new[](size_t size)
+{
+    return main_malloc(size);
+}
+
+void operator delete(void *ptr)
+{
+    main_free(ptr);
+}
+
+void operator delete[](void *ptr)
+{
+    return main_free(ptr);
+}
+
+void __cxa_pure_virtual(void)
+{
+    main_debug_print("Illegal to call a pure virtual function.\n");
+}

app/main.h

@@ -0,0 +1,32 @@
+#ifndef __MAIN_H__
+#define __MAIN_H__
+
+#include "stdint.h"
+#include "stdlib.h"
+#include "inttypes.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif // __cplusplus
+
+
+void main_task(void *param);
+
+void main_task_sleep(uint32_t timeout_ms);
+
+void * main_malloc(size_t bytes);
+
+void main_free(void *ptr);
+
+int main_debug_print(const char * fmt,...);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __MAIN_H__
+
+
+
+

app/xmake.lua

@@ -0,0 +1,27 @@
+local TARGET_NAME = "Air780E"
+local LIB_DIR = "$(buildir)/".. TARGET_NAME .. "/"
+local LIB_NAME = "lib" .. TARGET_NAME .. ".a "
+
+includes(SDK_TOP.."/luatos_lwip_socket")
+includes(SDK_TOP.."/thirdparty/libhttp")
+includes(SDK_TOP .. "/thirdparty/libemqtt")
+
+target(TARGET_NAME)
+    set_kind("static")
+    set_targetdir(LIB_DIR)
+    
+    --加入代码和头文件
+    add_includedirs("./",{public = true})
+    add_files("./*.c",{public = true})
+    add_files("./*.cpp",{public = true})
+
+    add_deps("luatos_lwip_socket") --socket依赖
+    add_deps("libhttp") --加入HTTP客户端支持，自动加载了socket依赖
+    add_deps("libemqtt") --加入MQTT支持
+
+
+    --可以继续增加add_includedirs和add_files
+    --自动链接
+    LIB_USER = LIB_USER .. SDK_TOP ..  "/".. LIB_DIR .. LIB_NAME .. " "
+    --甚至可以加入自己的库
+target_end()

build.bat

@@ -0,0 +1,42 @@
+@echo off
+
+@rem 目录
+set APP_ROOT_PATH=%~dp0
+
+@rem 设置sdk所需环境变量设置(可根据实际情况设置环境变量)
+set PROJECT_NAME=Air780E
+set PROJECT_DIR=%APP_ROOT_PATH%\app
+set PROJECT_DIR=%PROJECT_DIR:\=/%
+if "X" == "X%LSPD_MODE%" set LSPD_MODE=disable
+if "X" == "X%EC618_RNDIS%" set EC618_RNDIS=disable
+
+@rem 检查SDK
+if exist "%APP_ROOT_PATH%\sdk\xmake.lua" goto :CheckSdkOk
+echo SDK不存在,请使用git下载并使用git submodule update --init下载子模块。
+pause
+goto :eof
+:CheckSdkOk
+set ROOT_PATH=%APP_ROOT_PATH%\sdk
+set ROOT_PATH=%ROOT_PATH:\=/%
+
+@rem 检查xmake
+xmake --version 2> nul  > nul
+if "X%ERRORLEVEL%" == "X0" goto :CheckXMakeOk
+echo xmake 未安装，请到https://xmake.io下载安装
+pause
+goto :eof
+:CheckXMakeOk
+
+@rem 给SDK打补丁(替换一些文件)
+COPY /Y  "%APP_ROOT_PATH%\sdk_patch\ec618_0h00_flash.c"    "%APP_ROOT_PATH%\sdk\PLAT\core\ld\ec618_0h00_flash.c"
+
+@rem 产生CMakeLists.txt(用于方便使用编辑器打开)构建工程
+PUSHD "%APP_ROOT_PATH%\sdk" 2> nul > nul
+xmake project -k cmake 2> nul > nul
+xmake -v
+if NOT "X%ERRORLEVEL%" == "X0" PAUSE
+POPD 2> nul > nul
+
+@rem 使用ping延时一段时间
+ping localhost 2> nul > nul
+

clean.bat

@@ -0,0 +1,8 @@
+@echo off
+
+@rem 目录
+set APP_ROOT_PATH=%~dp0
+
+if exist "%APP_ROOT_PATH%\sdk\clean.bat" call "%APP_ROOT_PATH%\sdk\clean.bat"
+if exist "%APP_ROOT_PATH%\sdk\out" del /s /q "%APP_ROOT_PATH%\sdk\out"
+if exist "%APP_ROOT_PATH%\sdk\build" del /s /q "%APP_ROOT_PATH%\sdk\build"

sdk

@@ -0,0 +1 @@
+Subproject commit 08cc7dd46bce84c31e69526a840f4c44bd829a0e

sdk_patch/ec618_0h00_flash.c

@@ -0,0 +1,374 @@
+
+#include "mem_map.h"
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Specify the memory areas */
+MEMORY
+{
+  ASMB_AREA(rwx)              : ORIGIN = 0x00000000, LENGTH = 0x010000      /* 64KB */
+  MSMB_AREA(rwx)              : ORIGIN = 0x00400000, LENGTH = 0x140000      /* 1.25MB */
+#ifdef __LUATOS__
+#if defined(FLASH_AREA_SIZE)
+  FLASH_AREA(rx)              : ORIGIN = 0x00824000, LENGTH = FLASH_AREA_SIZE
+#else
+  FLASH_AREA(rx)              : ORIGIN = 0x00824000, LENGTH = 2212K         /* 2212K */
+#endif
+#else
+  FLASH_AREA(rx)              : ORIGIN = 0x00824000, LENGTH = 2944K         /* 2944K */
+#endif
+}
+
+/* Define output sections */
+SECTIONS
+{
+  . = AP_FLASH_LOAD_ADDR;
+  .vector :
+  {
+    KEEP(*(.isr_vector))
+  } >FLASH_AREA
+  .cache : ALIGN(128)
+  {
+    Image$$UNLOAD_NOCACHE$$Base = .;
+    *libdriver*.a:cache.o(.text*) 
+  } >FLASH_AREA
+  
+  .load_bootcode 0x0 :
+  {
+    . = ALIGN(4);
+    Load$$LOAD_BOOTCODE$$Base = LOADADDR(.load_bootcode);
+    Image$$LOAD_BOOTCODE$$Base = .;
+    KEEP(*(.mcuVector))
+    *(.ramBootCode)
+    *libdriver*.a:qspi.o(.text*)
+    *libdriver*.a:flash.o(.text*)
+    . = ALIGN(4);
+  } >ASMB_AREA AT>FLASH_AREA
+
+    Image$$LOAD_BOOTCODE$$Length = SIZEOF(.load_bootcode);
+
+  .load_ap_piram_asmb : ALIGN(4)
+  {
+   . = ALIGN(4);
+   Load$$LOAD_AP_PIRAM_ASMB$$Base = LOADADDR(.load_ap_piram_asmb);
+   Image$$LOAD_AP_PIRAM_ASMB$$Base = .;
+   *(.psPARamcode)
+   *(.platPARamcode)
+   *libc*.a:*memset.o(.text*)
+   *memcpy-armv7m.o(.text*)
+   . = ALIGN(4);
+  } >ASMB_AREA AT>FLASH_AREA
+
+  Image$$LOAD_AP_PIRAM_ASMB$$Length = SIZEOF(.load_ap_piram_asmb);
+
+  .load_ap_firam_asmb : ALIGN(4)
+  {
+   . = ALIGN(4);
+   Load$$LOAD_AP_FIRAM_ASMB$$Base = LOADADDR(.load_ap_firam_asmb);
+   Image$$LOAD_AP_FIRAM_ASMB$$Base = .;
+   *(.psFARamcode)
+   *(.platFARamcode)
+   . = ALIGN(4);
+  } >ASMB_AREA AT>FLASH_AREA
+
+  Image$$LOAD_AP_FIRAM_ASMB$$Length = SIZEOF(.load_ap_firam_asmb);
+
+  .load_apos : ALIGN(4)
+  {
+    . = ALIGN(4);
+    Load$$LOAD_APOS$$Base = LOADADDR(.load_apos);
+    Image$$LOAD_APOS$$Base = .;
+    *libfreertos.a:event_groups.o(.text*)
+    *libfreertos.a:heap_6.o(.text*)
+    *libfreertos.a:tlsf.o(.text*)
+    *libfreertos.a:list.o(.text*)
+    *libfreertos.a:queue.o(.text*)
+    *libfreertos.a:tasks.o(.text*)
+    . = ALIGN(4);
+  } >ASMB_AREA AT>FLASH_AREA
+
+  Image$$LOAD_APOS$$Length = SIZEOF(.load_apos);
+
+  .load_ap_rwdata_asmb : ALIGN(4)
+  {
+   . = ALIGN(4);
+   Load$$LOAD_AP_FDATA_ASMB$$RW$$Base = LOADADDR(.load_ap_rwdata_asmb);
+   Image$$LOAD_AP_FDATA_ASMB$$RW$$Base = .;
+   *(.platFARWData)
+   . = ALIGN(4);
+  } >ASMB_AREA AT>FLASH_AREA
+  Image$$LOAD_AP_FDATA_ASMB$$Length = SIZEOF(.load_ap_rwdata_asmb);
+  
+  .load_ps_rwdata_asmb : ALIGN(4)
+  {
+    Load$$LOAD_PS_FDATA_ASMB$$RW$$Base = LOADADDR(.load_ps_rwdata_asmb);
+    Image$$LOAD_PS_FDATA_ASMB$$RW$$Base = .;
+    *(.psFARWData)
+    . = ALIGN(4);
+  } >ASMB_AREA AT>FLASH_AREA
+  Image$$LOAD_PS_FDATA_ASMB$$RW$$Length = SIZEOF(.load_ps_rwdata_asmb);
+  
+  .load_ap_zidata_asmb (NOLOAD):
+  {
+   . = ALIGN(4);
+   Image$$LOAD_AP_FDATA_ASMB$$ZI$$Base = .;
+   *(.platFAZIData)
+   . = ALIGN(4);
+   Image$$LOAD_AP_FDATA_ASMB$$ZI$$Limit = .;
+   
+   Image$$LOAD_PS_FDATA_ASMB$$ZI$$Base = .;
+   *(.psFAZIData)
+   . = ALIGN(4);
+   Image$$LOAD_PS_FDATA_ASMB$$ZI$$Limit = .;
+   *(.platPANoInit)
+   *(.psFANoInitData)
+   *(.exceptCheck)
+  } >ASMB_AREA
+
+  .unload_cpaon CP_AONMEMBACKUP_START_ADDR (NOLOAD):
+  {
+
+  } >ASMB_AREA
+  
+  .load_rrcmem 0xB000 (NOLOAD):
+  {
+    *(.rrcMem)
+  } >ASMB_AREA
+
+  .load_flashmem 0xC000 (NOLOAD):
+  {
+    *(.apFlashMem)
+  } >ASMB_AREA
+
+  .load_ap_piram_msmb MSMB_START_ADDR :
+  {
+    . = ALIGN(4);
+    Load$$LOAD_AP_PIRAM_MSMB$$Base = LOADADDR(.load_ap_piram_msmb);
+    Image$$LOAD_AP_PIRAM_MSMB$$Base = .;
+    *(.psPMRamcode)
+    *(.platPMRamcode)
+    *(.platPMRamcodeFCLK)
+    *(.recordNodeRO)
+    . = ALIGN(4);
+  } >MSMB_AREA AT>FLASH_AREA
+
+  Image$$LOAD_AP_PIRAM_MSMB$$Length = SIZEOF(.load_ap_piram_msmb);
+
+  .load_ap_firam_msmb : ALIGN(4)
+  {
+    . = ALIGN(4);
+    Load$$LOAD_AP_FIRAM_MSMB$$Base = LOADADDR(.load_ap_firam_msmb);
+    Image$$LOAD_AP_FIRAM_MSMB$$Base = .;
+    *(.ramCode2)
+    *(.upRamCode)
+    *(.psFMRamcode)
+    *(.platFMRamcode)
+    *libfreertos.a:port_asm.o(.text*)
+    *libfreertos.a:port.o(.text*)
+    *libfreertos.a:timers.o(.text*)
+    *libfreertos.a:cmsis_os2.o(.text*)
+    . = ALIGN(4);
+  } >MSMB_AREA AT>FLASH_AREA
+
+  Image$$LOAD_AP_FIRAM_MSMB$$Length = SIZEOF(.load_ap_firam_msmb);
+
+  .load_dram_bsp : ALIGN(4)
+  {
+    . = ALIGN(4);
+    Load$$LOAD_DRAM_BSP$$Base = LOADADDR(.load_dram_bsp);
+    Image$$LOAD_DRAM_BSP$$Base = .;
+    *libdriver*:bsp_spi.o(.data*)
+    *libdriver*:flash.o(.data*)
+    *libdriver*:flash_rt.o(.data*)
+    *libdriver*:gpr.o(.data*)
+    *libdriver*:apmu.o(.data*)
+    *libdriver*:apmuTiming.o(.data*)
+    *libdriver*:bsp.o(.data*)
+    *libdriver*:plat_config.o(.data*)
+    *libstartup*:system_ec618.o(.data*)
+    *libdriver*:unilog.o(.data*)
+    *libdriver*:pad.o(.data*)
+    *libdriver*:ic.o(.data*)
+    *libdriver*:ec_main.o(.data*)
+    *libdriver*:slpman.o(.data*)
+    *libdriver*:bsp_usart.o(.data*)
+    *libdriver*:bsp_lpusart.o(.data*)
+    *libdriver*:timer.o(.data*)
+    *libdriver*:dma.o(.data*)
+    *libdriver*:adc.o(.data*)
+    *libdriver*:wdt.o(.data*)
+    *libmiddleware_ec*:usb_device.o(.data*)
+    *libmiddleware_ec*:uart_device.o(.data*)
+    *libdriver*:clock.o(.data*)
+    *libdriver*:hal_adc.o(.data*)
+    *libdriver*:hal_adcproxy.o(.data*)
+    *libdriver*:hal_alarm.o(.data*)
+    *libdriver*:exception_process.o(.data*)
+    *libdriver*:exception_dump.o(.data*)
+    . = ALIGN(4);
+  } >MSMB_AREA AT>FLASH_AREA
+
+  Image$$LOAD_DRAM_BSP$$Length = SIZEOF(.load_dram_bsp);
+
+  .load_dram_bsp_zi (NOLOAD):
+  {
+    . = ALIGN(4);
+    Image$$LOAD_DRAM_BSP$$ZI$$Base = .;
+    *libdriver*:bsp_spi.o(.bss*)
+    *libdriver*:flash.o(.bss*)
+    *libdriver*:flash_rt.o(.bss*)
+    *libdriver*:gpr.o(.bss*)
+    *libdriver*:apmu.o(.bss*)
+    *libdriver*:apmuTiming.o(.bss*)
+    *libdriver*:bsp.o(.bss*)
+    *libdriver*:plat_config.o(.bss*)
+    *libstartup*:system_ec618.o(.bss*)
+    *libdriver*:unilog.o(.bss*)
+    *libdriver*:pad.o(.bss*)
+    *libdriver*:ic.o(.bss*)
+    *libdriver*:ec_main.o(.bss*)
+    *libdriver*:slpman.o(.bss*)
+    *libdriver*:bsp_usart.o(.bss*)
+    *libdriver*:bsp_lpusart.o(.bss*)
+    *libdriver*:timer.o(.bss*)
+    *libdriver*:dma.o(.bss*)
+    *libdriver*:adc.o(.bss*)
+    *libdriver*:wdt.o(.bss*)
+    *libmiddleware_ec*:usb_device.o(.bss*)
+    *libmiddleware_ec*:uart_device.o(.bss*)
+    *libdriver*:clock.o(.bss*)
+    *libdriver*:hal_adc.o(.bss*)
+    *libdriver*:hal_trim.o(.bss*)
+    *libdriver*:hal_adcproxy.o(.bss*)
+    *libdriver*:hal_alarm.o(.bss*)
+    *libdriver*:exception_process.o(.bss*)
+    *libdriver*:exception_dump.o(.bss*)
+    *(.recordNodeZI)
+    . = ALIGN(4);
+  Image$$LOAD_DRAM_BSP$$ZI$$Limit = .;
+  } >MSMB_AREA
+
+  .unload_slpmem (NOLOAD):
+  {
+    *(.sleepmem)
+  } >MSMB_AREA
+
+  .load_dram_shared : ALIGN(4)
+  {
+    . = ALIGN(4);
+    Load$$LOAD_DRAM_SHARED$$Base = LOADADDR(.load_dram_shared);
+    Image$$LOAD_DRAM_SHARED$$Base = .;
+    *(.data*)
+    . = ALIGN(4);
+  } >MSMB_AREA AT>FLASH_AREA
+
+  Image$$LOAD_DRAM_SHARED$$Length = SIZEOF(.load_dram_shared);
+
+  .load_dram_shared_zi (NOLOAD):
+  {
+    . = ALIGN(4);
+    Image$$LOAD_DRAM_SHARED$$ZI$$Base = .;
+    *(.platBlSctZIData)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    *(.stack)               /* stack should be 4 byte align */
+    Image$$LOAD_DRAM_SHARED$$ZI$$Limit = .;
+    *(.USB_NOINIT_DATA_BUF)
+  } >MSMB_AREA
+
+
+  PROVIDE(end_ap_data = . );
+  PROVIDE(start_up_buffer = up_buf_start);
+  .load_up_buffer start_up_buffer(NOLOAD):
+  {
+    *(.catShareBuf)
+    Image$$LOAD_UP_BUFFER$$Limit = .;
+  } >MSMB_AREA
+
+  PROVIDE(end_up_buffer = . );
+  heap_size = start_up_buffer - end_ap_data;
+  ASSERT(heap_size>=min_heap_size_threshold,"ap use too much ram, heap less than min_heap_size_threshold!")
+  ASSERT(end_up_buffer<=MSMB_APMEM_END_ADDR,"ap use too much ram, exceed to MSMB_APMEM_END_ADDR")
+
+  .text :
+  {
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.text*)
+    . = ALIGN(4); 
+    __exidx_start = .;
+    /* *(.ARM.exidx* .gnu.linkonce.armexidx.*) */
+    __exidx_end = .;
+    . = ALIGN(4);
+    *(.ARM.extab*) 
+    . = ALIGN(4);
+    *(.glue_7)
+    *(.glue_7t)
+    *(.vfpll_veneer)
+    *(.v4_bx)
+    . = ALIGN(4);
+   PROVIDE(__ctors_start__ = .);
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   PROVIDE(__ctors_end__ = .);
+    *(.init*)
+    *(.fini*)
+    *(.iplt)
+    *(.igot.plt)
+    *(.rel.iplt)
+  } >FLASH_AREA
+
+  .preinit_fun_array :
+  {
+      . = ALIGN(4);
+      __preinit_fun_array_start = .;
+      KEEP (*(SORT(.preinit_fun_array.*)))
+      KEEP (*(.preinit_fun_array*))
+      __preinit_fun_array_end = .;
+      . = ALIGN(4);
+  } > FLASH_AREA   
+  .drv_init_fun_array :
+  {
+      . = ALIGN(4);
+      __drv_init_fun_array_start = .;
+      KEEP (*(SORT(.drv_init_fun_array.*)))
+      KEEP (*(.drv_init_fun_array*))
+      __drv_init_fun_array_end = .;
+      . = ALIGN(4);
+  } > FLASH_AREA
+  
+  .task_fun_array :
+  {
+      . = ALIGN(4);
+      __task_fun_array_start = .;
+      KEEP (*(SORT(.task_fun_array.*)))
+      KEEP (*(.task_fun_array*))
+      __task_fun_array_end = .;
+      . = ALIGN(4);
+  } > FLASH_AREA
+
+  PROVIDE(totalFlashLimit = .);
+
+  .load_xp_sharedinfo XP_SHAREINFO_BASE_ADDR (NOLOAD):
+  {
+  *(.shareInfo)
+  } >MSMB_AREA
+  
+  .load_dbg_area XP_DBGRESERVED_BASE_ADDR (NOLOAD):
+  {
+  *(.resetFlag)
+  } >MSMB_AREA
+  
+  .unload_xp_ipcmem IPC_SHAREDMEM_START_ADDR (NOLOAD):
+  {
+
+  } >MSMB_AREA
+
+}
+
+GROUP(
+    libgcc.a
+    libc.a
+    libm.a
+ )