HEYAHONG/SPI_Flasher_Via_STM32
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SPI_Flasher_Via_STM32/FW/Debug/STM32F103C8.list

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STM32F103C8.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00008064 0800010c 0800010c 0001010c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000004c 08008170 08008170 00018170 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080081bc 080081bc 00020188 2**0
CONTENTS
4 .ARM 00000000 080081bc 080081bc 00020188 2**0
CONTENTS
5 .preinit_array 00000000 080081bc 080081bc 00020188 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080081bc 080081bc 000181bc 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080081c0 080081c0 000181c0 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000188 20000000 080081c4 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00001acc 20000188 0800834c 00020188 2**2
ALLOC
10 ._user_heap_stack 00000604 20001c54 0800834c 00021c54 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00020188 2**0
CONTENTS, READONLY
12 .debug_info 00020498 00000000 00000000 000201b1 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 00003f78 00000000 00000000 00040649 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 00001750 00000000 00000000 000445c8 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 00001588 00000000 00000000 00045d18 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 00018ee4 00000000 00000000 000472a0 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 00014c3e 00000000 00000000 00060184 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 0007afb9 00000000 00000000 00074dc2 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 000efd7b 2**0
CONTENTS, READONLY
20 .debug_frame 0000622c 00000000 00000000 000efdf8 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 20000188 .word 0x20000188
8000128: 00000000 .word 0x00000000
800012c: 08008158 .word 0x08008158
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 2000018c .word 0x2000018c
8000148: 08008158 .word 0x08008158
0800014c <__aeabi_drsub>:
800014c: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000
8000150: e002 b.n 8000158 <__adddf3>
8000152: bf00 nop
08000154 <__aeabi_dsub>:
8000154: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000
08000158 <__adddf3>:
8000158: b530 push {r4, r5, lr}
800015a: ea4f 0441 mov.w r4, r1, lsl #1
800015e: ea4f 0543 mov.w r5, r3, lsl #1
8000162: ea94 0f05 teq r4, r5
8000166: bf08 it eq
8000168: ea90 0f02 teqeq r0, r2
800016c: bf1f itttt ne
800016e: ea54 0c00 orrsne.w ip, r4, r0
8000172: ea55 0c02 orrsne.w ip, r5, r2
8000176: ea7f 5c64 mvnsne.w ip, r4, asr #21
800017a: ea7f 5c65 mvnsne.w ip, r5, asr #21
800017e: f000 80e2 beq.w 8000346 <__adddf3+0x1ee>
8000182: ea4f 5454 mov.w r4, r4, lsr #21
8000186: ebd4 5555 rsbs r5, r4, r5, lsr #21
800018a: bfb8 it lt
800018c: 426d neglt r5, r5
800018e: dd0c ble.n 80001aa <__adddf3+0x52>
8000190: 442c add r4, r5
8000192: ea80 0202 eor.w r2, r0, r2
8000196: ea81 0303 eor.w r3, r1, r3
800019a: ea82 0000 eor.w r0, r2, r0
800019e: ea83 0101 eor.w r1, r3, r1
80001a2: ea80 0202 eor.w r2, r0, r2
80001a6: ea81 0303 eor.w r3, r1, r3
80001aa: 2d36 cmp r5, #54 ; 0x36
80001ac: bf88 it hi
80001ae: bd30 pophi {r4, r5, pc}
80001b0: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
80001b4: ea4f 3101 mov.w r1, r1, lsl #12
80001b8: f44f 1c80 mov.w ip, #1048576 ; 0x100000
80001bc: ea4c 3111 orr.w r1, ip, r1, lsr #12
80001c0: d002 beq.n 80001c8 <__adddf3+0x70>
80001c2: 4240 negs r0, r0
80001c4: eb61 0141 sbc.w r1, r1, r1, lsl #1
80001c8: f013 4f00 tst.w r3, #2147483648 ; 0x80000000
80001cc: ea4f 3303 mov.w r3, r3, lsl #12
80001d0: ea4c 3313 orr.w r3, ip, r3, lsr #12
80001d4: d002 beq.n 80001dc <__adddf3+0x84>
80001d6: 4252 negs r2, r2
80001d8: eb63 0343 sbc.w r3, r3, r3, lsl #1
80001dc: ea94 0f05 teq r4, r5
80001e0: f000 80a7 beq.w 8000332 <__adddf3+0x1da>
80001e4: f1a4 0401 sub.w r4, r4, #1
80001e8: f1d5 0e20 rsbs lr, r5, #32
80001ec: db0d blt.n 800020a <__adddf3+0xb2>
80001ee: fa02 fc0e lsl.w ip, r2, lr
80001f2: fa22 f205 lsr.w r2, r2, r5
80001f6: 1880 adds r0, r0, r2
80001f8: f141 0100 adc.w r1, r1, #0
80001fc: fa03 f20e lsl.w r2, r3, lr
8000200: 1880 adds r0, r0, r2
8000202: fa43 f305 asr.w r3, r3, r5
8000206: 4159 adcs r1, r3
8000208: e00e b.n 8000228 <__adddf3+0xd0>
800020a: f1a5 0520 sub.w r5, r5, #32
800020e: f10e 0e20 add.w lr, lr, #32
8000212: 2a01 cmp r2, #1
8000214: fa03 fc0e lsl.w ip, r3, lr
8000218: bf28 it cs
800021a: f04c 0c02 orrcs.w ip, ip, #2
800021e: fa43 f305 asr.w r3, r3, r5
8000222: 18c0 adds r0, r0, r3
8000224: eb51 71e3 adcs.w r1, r1, r3, asr #31
8000228: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
800022c: d507 bpl.n 800023e <__adddf3+0xe6>
800022e: f04f 0e00 mov.w lr, #0
8000232: f1dc 0c00 rsbs ip, ip, #0
8000236: eb7e 0000 sbcs.w r0, lr, r0
800023a: eb6e 0101 sbc.w r1, lr, r1
800023e: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000
8000242: d31b bcc.n 800027c <__adddf3+0x124>
8000244: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000
8000248: d30c bcc.n 8000264 <__adddf3+0x10c>
800024a: 0849 lsrs r1, r1, #1
800024c: ea5f 0030 movs.w r0, r0, rrx
8000250: ea4f 0c3c mov.w ip, ip, rrx
8000254: f104 0401 add.w r4, r4, #1
8000258: ea4f 5244 mov.w r2, r4, lsl #21
800025c: f512 0f80 cmn.w r2, #4194304 ; 0x400000
8000260: f080 809a bcs.w 8000398 <__adddf3+0x240>
8000264: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000
8000268: bf08 it eq
800026a: ea5f 0c50 movseq.w ip, r0, lsr #1
800026e: f150 0000 adcs.w r0, r0, #0
8000272: eb41 5104 adc.w r1, r1, r4, lsl #20
8000276: ea41 0105 orr.w r1, r1, r5
800027a: bd30 pop {r4, r5, pc}
800027c: ea5f 0c4c movs.w ip, ip, lsl #1
8000280: 4140 adcs r0, r0
8000282: eb41 0101 adc.w r1, r1, r1
8000286: f411 1f80 tst.w r1, #1048576 ; 0x100000
800028a: f1a4 0401 sub.w r4, r4, #1
800028e: d1e9 bne.n 8000264 <__adddf3+0x10c>
8000290: f091 0f00 teq r1, #0
8000294: bf04 itt eq
8000296: 4601 moveq r1, r0
8000298: 2000 moveq r0, #0
800029a: fab1 f381 clz r3, r1
800029e: bf08 it eq
80002a0: 3320 addeq r3, #32
80002a2: f1a3 030b sub.w r3, r3, #11
80002a6: f1b3 0220 subs.w r2, r3, #32
80002aa: da0c bge.n 80002c6 <__adddf3+0x16e>
80002ac: 320c adds r2, #12
80002ae: dd08 ble.n 80002c2 <__adddf3+0x16a>
80002b0: f102 0c14 add.w ip, r2, #20
80002b4: f1c2 020c rsb r2, r2, #12
80002b8: fa01 f00c lsl.w r0, r1, ip
80002bc: fa21 f102 lsr.w r1, r1, r2
80002c0: e00c b.n 80002dc <__adddf3+0x184>
80002c2: f102 0214 add.w r2, r2, #20
80002c6: bfd8 it le
80002c8: f1c2 0c20 rsble ip, r2, #32
80002cc: fa01 f102 lsl.w r1, r1, r2
80002d0: fa20 fc0c lsr.w ip, r0, ip
80002d4: bfdc itt le
80002d6: ea41 010c orrle.w r1, r1, ip
80002da: 4090 lslle r0, r2
80002dc: 1ae4 subs r4, r4, r3
80002de: bfa2 ittt ge
80002e0: eb01 5104 addge.w r1, r1, r4, lsl #20
80002e4: 4329 orrge r1, r5
80002e6: bd30 popge {r4, r5, pc}
80002e8: ea6f 0404 mvn.w r4, r4
80002ec: 3c1f subs r4, #31
80002ee: da1c bge.n 800032a <__adddf3+0x1d2>
80002f0: 340c adds r4, #12
80002f2: dc0e bgt.n 8000312 <__adddf3+0x1ba>
80002f4: f104 0414 add.w r4, r4, #20
80002f8: f1c4 0220 rsb r2, r4, #32
80002fc: fa20 f004 lsr.w r0, r0, r4
8000300: fa01 f302 lsl.w r3, r1, r2
8000304: ea40 0003 orr.w r0, r0, r3
8000308: fa21 f304 lsr.w r3, r1, r4
800030c: ea45 0103 orr.w r1, r5, r3
8000310: bd30 pop {r4, r5, pc}
8000312: f1c4 040c rsb r4, r4, #12
8000316: f1c4 0220 rsb r2, r4, #32
800031a: fa20 f002 lsr.w r0, r0, r2
800031e: fa01 f304 lsl.w r3, r1, r4
8000322: ea40 0003 orr.w r0, r0, r3
8000326: 4629 mov r1, r5
8000328: bd30 pop {r4, r5, pc}
800032a: fa21 f004 lsr.w r0, r1, r4
800032e: 4629 mov r1, r5
8000330: bd30 pop {r4, r5, pc}
8000332: f094 0f00 teq r4, #0
8000336: f483 1380 eor.w r3, r3, #1048576 ; 0x100000
800033a: bf06 itte eq
800033c: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000
8000340: 3401 addeq r4, #1
8000342: 3d01 subne r5, #1
8000344: e74e b.n 80001e4 <__adddf3+0x8c>
8000346: ea7f 5c64 mvns.w ip, r4, asr #21
800034a: bf18 it ne
800034c: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000350: d029 beq.n 80003a6 <__adddf3+0x24e>
8000352: ea94 0f05 teq r4, r5
8000356: bf08 it eq
8000358: ea90 0f02 teqeq r0, r2
800035c: d005 beq.n 800036a <__adddf3+0x212>
800035e: ea54 0c00 orrs.w ip, r4, r0
8000362: bf04 itt eq
8000364: 4619 moveq r1, r3
8000366: 4610 moveq r0, r2
8000368: bd30 pop {r4, r5, pc}
800036a: ea91 0f03 teq r1, r3
800036e: bf1e ittt ne
8000370: 2100 movne r1, #0
8000372: 2000 movne r0, #0
8000374: bd30 popne {r4, r5, pc}
8000376: ea5f 5c54 movs.w ip, r4, lsr #21
800037a: d105 bne.n 8000388 <__adddf3+0x230>
800037c: 0040 lsls r0, r0, #1
800037e: 4149 adcs r1, r1
8000380: bf28 it cs
8000382: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000
8000386: bd30 pop {r4, r5, pc}
8000388: f514 0480 adds.w r4, r4, #4194304 ; 0x400000
800038c: bf3c itt cc
800038e: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000
8000392: bd30 popcc {r4, r5, pc}
8000394: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
8000398: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000
800039c: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
80003a0: f04f 0000 mov.w r0, #0
80003a4: bd30 pop {r4, r5, pc}
80003a6: ea7f 5c64 mvns.w ip, r4, asr #21
80003aa: bf1a itte ne
80003ac: 4619 movne r1, r3
80003ae: 4610 movne r0, r2
80003b0: ea7f 5c65 mvnseq.w ip, r5, asr #21
80003b4: bf1c itt ne
80003b6: 460b movne r3, r1
80003b8: 4602 movne r2, r0
80003ba: ea50 3401 orrs.w r4, r0, r1, lsl #12
80003be: bf06 itte eq
80003c0: ea52 3503 orrseq.w r5, r2, r3, lsl #12
80003c4: ea91 0f03 teqeq r1, r3
80003c8: f441 2100 orrne.w r1, r1, #524288 ; 0x80000
80003cc: bd30 pop {r4, r5, pc}
80003ce: bf00 nop
080003d0 <__aeabi_ui2d>:
80003d0: f090 0f00 teq r0, #0
80003d4: bf04 itt eq
80003d6: 2100 moveq r1, #0
80003d8: 4770 bxeq lr
80003da: b530 push {r4, r5, lr}
80003dc: f44f 6480 mov.w r4, #1024 ; 0x400
80003e0: f104 0432 add.w r4, r4, #50 ; 0x32
80003e4: f04f 0500 mov.w r5, #0
80003e8: f04f 0100 mov.w r1, #0
80003ec: e750 b.n 8000290 <__adddf3+0x138>
80003ee: bf00 nop
080003f0 <__aeabi_i2d>:
80003f0: f090 0f00 teq r0, #0
80003f4: bf04 itt eq
80003f6: 2100 moveq r1, #0
80003f8: 4770 bxeq lr
80003fa: b530 push {r4, r5, lr}
80003fc: f44f 6480 mov.w r4, #1024 ; 0x400
8000400: f104 0432 add.w r4, r4, #50 ; 0x32
8000404: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000
8000408: bf48 it mi
800040a: 4240 negmi r0, r0
800040c: f04f 0100 mov.w r1, #0
8000410: e73e b.n 8000290 <__adddf3+0x138>
8000412: bf00 nop
08000414 <__aeabi_f2d>:
8000414: 0042 lsls r2, r0, #1
8000416: ea4f 01e2 mov.w r1, r2, asr #3
800041a: ea4f 0131 mov.w r1, r1, rrx
800041e: ea4f 7002 mov.w r0, r2, lsl #28
8000422: bf1f itttt ne
8000424: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000
8000428: f093 4f7f teqne r3, #4278190080 ; 0xff000000
800042c: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000
8000430: 4770 bxne lr
8000432: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000
8000436: bf08 it eq
8000438: 4770 bxeq lr
800043a: f093 4f7f teq r3, #4278190080 ; 0xff000000
800043e: bf04 itt eq
8000440: f441 2100 orreq.w r1, r1, #524288 ; 0x80000
8000444: 4770 bxeq lr
8000446: b530 push {r4, r5, lr}
8000448: f44f 7460 mov.w r4, #896 ; 0x380
800044c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
8000450: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
8000454: e71c b.n 8000290 <__adddf3+0x138>
8000456: bf00 nop
08000458 <__aeabi_ul2d>:
8000458: ea50 0201 orrs.w r2, r0, r1
800045c: bf08 it eq
800045e: 4770 bxeq lr
8000460: b530 push {r4, r5, lr}
8000462: f04f 0500 mov.w r5, #0
8000466: e00a b.n 800047e <__aeabi_l2d+0x16>
08000468 <__aeabi_l2d>:
8000468: ea50 0201 orrs.w r2, r0, r1
800046c: bf08 it eq
800046e: 4770 bxeq lr
8000470: b530 push {r4, r5, lr}
8000472: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000
8000476: d502 bpl.n 800047e <__aeabi_l2d+0x16>
8000478: 4240 negs r0, r0
800047a: eb61 0141 sbc.w r1, r1, r1, lsl #1
800047e: f44f 6480 mov.w r4, #1024 ; 0x400
8000482: f104 0432 add.w r4, r4, #50 ; 0x32
8000486: ea5f 5c91 movs.w ip, r1, lsr #22
800048a: f43f aed8 beq.w 800023e <__adddf3+0xe6>
800048e: f04f 0203 mov.w r2, #3
8000492: ea5f 0cdc movs.w ip, ip, lsr #3
8000496: bf18 it ne
8000498: 3203 addne r2, #3
800049a: ea5f 0cdc movs.w ip, ip, lsr #3
800049e: bf18 it ne
80004a0: 3203 addne r2, #3
80004a2: eb02 02dc add.w r2, r2, ip, lsr #3
80004a6: f1c2 0320 rsb r3, r2, #32
80004aa: fa00 fc03 lsl.w ip, r0, r3
80004ae: fa20 f002 lsr.w r0, r0, r2
80004b2: fa01 fe03 lsl.w lr, r1, r3
80004b6: ea40 000e orr.w r0, r0, lr
80004ba: fa21 f102 lsr.w r1, r1, r2
80004be: 4414 add r4, r2
80004c0: e6bd b.n 800023e <__adddf3+0xe6>
80004c2: bf00 nop
080004c4 <__aeabi_dmul>:
80004c4: b570 push {r4, r5, r6, lr}
80004c6: f04f 0cff mov.w ip, #255 ; 0xff
80004ca: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
80004ce: ea1c 5411 ands.w r4, ip, r1, lsr #20
80004d2: bf1d ittte ne
80004d4: ea1c 5513 andsne.w r5, ip, r3, lsr #20
80004d8: ea94 0f0c teqne r4, ip
80004dc: ea95 0f0c teqne r5, ip
80004e0: f000 f8de bleq 80006a0 <__aeabi_dmul+0x1dc>
80004e4: 442c add r4, r5
80004e6: ea81 0603 eor.w r6, r1, r3
80004ea: ea21 514c bic.w r1, r1, ip, lsl #21
80004ee: ea23 534c bic.w r3, r3, ip, lsl #21
80004f2: ea50 3501 orrs.w r5, r0, r1, lsl #12
80004f6: bf18 it ne
80004f8: ea52 3503 orrsne.w r5, r2, r3, lsl #12
80004fc: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
8000500: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
8000504: d038 beq.n 8000578 <__aeabi_dmul+0xb4>
8000506: fba0 ce02 umull ip, lr, r0, r2
800050a: f04f 0500 mov.w r5, #0
800050e: fbe1 e502 umlal lr, r5, r1, r2
8000512: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000
8000516: fbe0 e503 umlal lr, r5, r0, r3
800051a: f04f 0600 mov.w r6, #0
800051e: fbe1 5603 umlal r5, r6, r1, r3
8000522: f09c 0f00 teq ip, #0
8000526: bf18 it ne
8000528: f04e 0e01 orrne.w lr, lr, #1
800052c: f1a4 04ff sub.w r4, r4, #255 ; 0xff
8000530: f5b6 7f00 cmp.w r6, #512 ; 0x200
8000534: f564 7440 sbc.w r4, r4, #768 ; 0x300
8000538: d204 bcs.n 8000544 <__aeabi_dmul+0x80>
800053a: ea5f 0e4e movs.w lr, lr, lsl #1
800053e: 416d adcs r5, r5
8000540: eb46 0606 adc.w r6, r6, r6
8000544: ea42 21c6 orr.w r1, r2, r6, lsl #11
8000548: ea41 5155 orr.w r1, r1, r5, lsr #21
800054c: ea4f 20c5 mov.w r0, r5, lsl #11
8000550: ea40 505e orr.w r0, r0, lr, lsr #21
8000554: ea4f 2ece mov.w lr, lr, lsl #11
8000558: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
800055c: bf88 it hi
800055e: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
8000562: d81e bhi.n 80005a2 <__aeabi_dmul+0xde>
8000564: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000
8000568: bf08 it eq
800056a: ea5f 0e50 movseq.w lr, r0, lsr #1
800056e: f150 0000 adcs.w r0, r0, #0
8000572: eb41 5104 adc.w r1, r1, r4, lsl #20
8000576: bd70 pop {r4, r5, r6, pc}
8000578: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000
800057c: ea46 0101 orr.w r1, r6, r1
8000580: ea40 0002 orr.w r0, r0, r2
8000584: ea81 0103 eor.w r1, r1, r3
8000588: ebb4 045c subs.w r4, r4, ip, lsr #1
800058c: bfc2 ittt gt
800058e: ebd4 050c rsbsgt r5, r4, ip
8000592: ea41 5104 orrgt.w r1, r1, r4, lsl #20
8000596: bd70 popgt {r4, r5, r6, pc}
8000598: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
800059c: f04f 0e00 mov.w lr, #0
80005a0: 3c01 subs r4, #1
80005a2: f300 80ab bgt.w 80006fc <__aeabi_dmul+0x238>
80005a6: f114 0f36 cmn.w r4, #54 ; 0x36
80005aa: bfde ittt le
80005ac: 2000 movle r0, #0
80005ae: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000
80005b2: bd70 pople {r4, r5, r6, pc}
80005b4: f1c4 0400 rsb r4, r4, #0
80005b8: 3c20 subs r4, #32
80005ba: da35 bge.n 8000628 <__aeabi_dmul+0x164>
80005bc: 340c adds r4, #12
80005be: dc1b bgt.n 80005f8 <__aeabi_dmul+0x134>
80005c0: f104 0414 add.w r4, r4, #20
80005c4: f1c4 0520 rsb r5, r4, #32
80005c8: fa00 f305 lsl.w r3, r0, r5
80005cc: fa20 f004 lsr.w r0, r0, r4
80005d0: fa01 f205 lsl.w r2, r1, r5
80005d4: ea40 0002 orr.w r0, r0, r2
80005d8: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000
80005dc: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
80005e0: eb10 70d3 adds.w r0, r0, r3, lsr #31
80005e4: fa21 f604 lsr.w r6, r1, r4
80005e8: eb42 0106 adc.w r1, r2, r6
80005ec: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80005f0: bf08 it eq
80005f2: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80005f6: bd70 pop {r4, r5, r6, pc}
80005f8: f1c4 040c rsb r4, r4, #12
80005fc: f1c4 0520 rsb r5, r4, #32
8000600: fa00 f304 lsl.w r3, r0, r4
8000604: fa20 f005 lsr.w r0, r0, r5
8000608: fa01 f204 lsl.w r2, r1, r4
800060c: ea40 0002 orr.w r0, r0, r2
8000610: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
8000614: eb10 70d3 adds.w r0, r0, r3, lsr #31
8000618: f141 0100 adc.w r1, r1, #0
800061c: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000620: bf08 it eq
8000622: ea20 70d3 biceq.w r0, r0, r3, lsr #31
8000626: bd70 pop {r4, r5, r6, pc}
8000628: f1c4 0520 rsb r5, r4, #32
800062c: fa00 f205 lsl.w r2, r0, r5
8000630: ea4e 0e02 orr.w lr, lr, r2
8000634: fa20 f304 lsr.w r3, r0, r4
8000638: fa01 f205 lsl.w r2, r1, r5
800063c: ea43 0302 orr.w r3, r3, r2
8000640: fa21 f004 lsr.w r0, r1, r4
8000644: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
8000648: fa21 f204 lsr.w r2, r1, r4
800064c: ea20 0002 bic.w r0, r0, r2
8000650: eb00 70d3 add.w r0, r0, r3, lsr #31
8000654: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000658: bf08 it eq
800065a: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800065e: bd70 pop {r4, r5, r6, pc}
8000660: f094 0f00 teq r4, #0
8000664: d10f bne.n 8000686 <__aeabi_dmul+0x1c2>
8000666: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000
800066a: 0040 lsls r0, r0, #1
800066c: eb41 0101 adc.w r1, r1, r1
8000670: f411 1f80 tst.w r1, #1048576 ; 0x100000
8000674: bf08 it eq
8000676: 3c01 subeq r4, #1
8000678: d0f7 beq.n 800066a <__aeabi_dmul+0x1a6>
800067a: ea41 0106 orr.w r1, r1, r6
800067e: f095 0f00 teq r5, #0
8000682: bf18 it ne
8000684: 4770 bxne lr
8000686: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000
800068a: 0052 lsls r2, r2, #1
800068c: eb43 0303 adc.w r3, r3, r3
8000690: f413 1f80 tst.w r3, #1048576 ; 0x100000
8000694: bf08 it eq
8000696: 3d01 subeq r5, #1
8000698: d0f7 beq.n 800068a <__aeabi_dmul+0x1c6>
800069a: ea43 0306 orr.w r3, r3, r6
800069e: 4770 bx lr
80006a0: ea94 0f0c teq r4, ip
80006a4: ea0c 5513 and.w r5, ip, r3, lsr #20
80006a8: bf18 it ne
80006aa: ea95 0f0c teqne r5, ip
80006ae: d00c beq.n 80006ca <__aeabi_dmul+0x206>
80006b0: ea50 0641 orrs.w r6, r0, r1, lsl #1
80006b4: bf18 it ne
80006b6: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80006ba: d1d1 bne.n 8000660 <__aeabi_dmul+0x19c>
80006bc: ea81 0103 eor.w r1, r1, r3
80006c0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
80006c4: f04f 0000 mov.w r0, #0
80006c8: bd70 pop {r4, r5, r6, pc}
80006ca: ea50 0641 orrs.w r6, r0, r1, lsl #1
80006ce: bf06 itte eq
80006d0: 4610 moveq r0, r2
80006d2: 4619 moveq r1, r3
80006d4: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80006d8: d019 beq.n 800070e <__aeabi_dmul+0x24a>
80006da: ea94 0f0c teq r4, ip
80006de: d102 bne.n 80006e6 <__aeabi_dmul+0x222>
80006e0: ea50 3601 orrs.w r6, r0, r1, lsl #12
80006e4: d113 bne.n 800070e <__aeabi_dmul+0x24a>
80006e6: ea95 0f0c teq r5, ip
80006ea: d105 bne.n 80006f8 <__aeabi_dmul+0x234>
80006ec: ea52 3603 orrs.w r6, r2, r3, lsl #12
80006f0: bf1c itt ne
80006f2: 4610 movne r0, r2
80006f4: 4619 movne r1, r3
80006f6: d10a bne.n 800070e <__aeabi_dmul+0x24a>
80006f8: ea81 0103 eor.w r1, r1, r3
80006fc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
8000700: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
8000704: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
8000708: f04f 0000 mov.w r0, #0
800070c: bd70 pop {r4, r5, r6, pc}
800070e: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
8000712: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000
8000716: bd70 pop {r4, r5, r6, pc}
08000718 <__aeabi_ddiv>:
8000718: b570 push {r4, r5, r6, lr}
800071a: f04f 0cff mov.w ip, #255 ; 0xff
800071e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
8000722: ea1c 5411 ands.w r4, ip, r1, lsr #20
8000726: bf1d ittte ne
8000728: ea1c 5513 andsne.w r5, ip, r3, lsr #20
800072c: ea94 0f0c teqne r4, ip
8000730: ea95 0f0c teqne r5, ip
8000734: f000 f8a7 bleq 8000886 <__aeabi_ddiv+0x16e>
8000738: eba4 0405 sub.w r4, r4, r5
800073c: ea81 0e03 eor.w lr, r1, r3
8000740: ea52 3503 orrs.w r5, r2, r3, lsl #12
8000744: ea4f 3101 mov.w r1, r1, lsl #12
8000748: f000 8088 beq.w 800085c <__aeabi_ddiv+0x144>
800074c: ea4f 3303 mov.w r3, r3, lsl #12
8000750: f04f 5580 mov.w r5, #268435456 ; 0x10000000
8000754: ea45 1313 orr.w r3, r5, r3, lsr #4
8000758: ea43 6312 orr.w r3, r3, r2, lsr #24
800075c: ea4f 2202 mov.w r2, r2, lsl #8
8000760: ea45 1511 orr.w r5, r5, r1, lsr #4
8000764: ea45 6510 orr.w r5, r5, r0, lsr #24
8000768: ea4f 2600 mov.w r6, r0, lsl #8
800076c: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000
8000770: 429d cmp r5, r3
8000772: bf08 it eq
8000774: 4296 cmpeq r6, r2
8000776: f144 04fd adc.w r4, r4, #253 ; 0xfd
800077a: f504 7440 add.w r4, r4, #768 ; 0x300
800077e: d202 bcs.n 8000786 <__aeabi_ddiv+0x6e>
8000780: 085b lsrs r3, r3, #1
8000782: ea4f 0232 mov.w r2, r2, rrx
8000786: 1ab6 subs r6, r6, r2
8000788: eb65 0503 sbc.w r5, r5, r3
800078c: 085b lsrs r3, r3, #1
800078e: ea4f 0232 mov.w r2, r2, rrx
8000792: f44f 1080 mov.w r0, #1048576 ; 0x100000
8000796: f44f 2c00 mov.w ip, #524288 ; 0x80000
800079a: ebb6 0e02 subs.w lr, r6, r2
800079e: eb75 0e03 sbcs.w lr, r5, r3
80007a2: bf22 ittt cs
80007a4: 1ab6 subcs r6, r6, r2
80007a6: 4675 movcs r5, lr
80007a8: ea40 000c orrcs.w r0, r0, ip
80007ac: 085b lsrs r3, r3, #1
80007ae: ea4f 0232 mov.w r2, r2, rrx
80007b2: ebb6 0e02 subs.w lr, r6, r2
80007b6: eb75 0e03 sbcs.w lr, r5, r3
80007ba: bf22 ittt cs
80007bc: 1ab6 subcs r6, r6, r2
80007be: 4675 movcs r5, lr
80007c0: ea40 005c orrcs.w r0, r0, ip, lsr #1
80007c4: 085b lsrs r3, r3, #1
80007c6: ea4f 0232 mov.w r2, r2, rrx
80007ca: ebb6 0e02 subs.w lr, r6, r2
80007ce: eb75 0e03 sbcs.w lr, r5, r3
80007d2: bf22 ittt cs
80007d4: 1ab6 subcs r6, r6, r2
80007d6: 4675 movcs r5, lr
80007d8: ea40 009c orrcs.w r0, r0, ip, lsr #2
80007dc: 085b lsrs r3, r3, #1
80007de: ea4f 0232 mov.w r2, r2, rrx
80007e2: ebb6 0e02 subs.w lr, r6, r2
80007e6: eb75 0e03 sbcs.w lr, r5, r3
80007ea: bf22 ittt cs
80007ec: 1ab6 subcs r6, r6, r2
80007ee: 4675 movcs r5, lr
80007f0: ea40 00dc orrcs.w r0, r0, ip, lsr #3
80007f4: ea55 0e06 orrs.w lr, r5, r6
80007f8: d018 beq.n 800082c <__aeabi_ddiv+0x114>
80007fa: ea4f 1505 mov.w r5, r5, lsl #4
80007fe: ea45 7516 orr.w r5, r5, r6, lsr #28
8000802: ea4f 1606 mov.w r6, r6, lsl #4
8000806: ea4f 03c3 mov.w r3, r3, lsl #3
800080a: ea43 7352 orr.w r3, r3, r2, lsr #29
800080e: ea4f 02c2 mov.w r2, r2, lsl #3
8000812: ea5f 1c1c movs.w ip, ip, lsr #4
8000816: d1c0 bne.n 800079a <__aeabi_ddiv+0x82>
8000818: f411 1f80 tst.w r1, #1048576 ; 0x100000
800081c: d10b bne.n 8000836 <__aeabi_ddiv+0x11e>
800081e: ea41 0100 orr.w r1, r1, r0
8000822: f04f 0000 mov.w r0, #0
8000826: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000
800082a: e7b6 b.n 800079a <__aeabi_ddiv+0x82>
800082c: f411 1f80 tst.w r1, #1048576 ; 0x100000
8000830: bf04 itt eq
8000832: 4301 orreq r1, r0
8000834: 2000 moveq r0, #0
8000836: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
800083a: bf88 it hi
800083c: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
8000840: f63f aeaf bhi.w 80005a2 <__aeabi_dmul+0xde>
8000844: ebb5 0c03 subs.w ip, r5, r3
8000848: bf04 itt eq
800084a: ebb6 0c02 subseq.w ip, r6, r2
800084e: ea5f 0c50 movseq.w ip, r0, lsr #1
8000852: f150 0000 adcs.w r0, r0, #0
8000856: eb41 5104 adc.w r1, r1, r4, lsl #20
800085a: bd70 pop {r4, r5, r6, pc}
800085c: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000
8000860: ea4e 3111 orr.w r1, lr, r1, lsr #12
8000864: eb14 045c adds.w r4, r4, ip, lsr #1
8000868: bfc2 ittt gt
800086a: ebd4 050c rsbsgt r5, r4, ip
800086e: ea41 5104 orrgt.w r1, r1, r4, lsl #20
8000872: bd70 popgt {r4, r5, r6, pc}
8000874: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
8000878: f04f 0e00 mov.w lr, #0
800087c: 3c01 subs r4, #1
800087e: e690 b.n 80005a2 <__aeabi_dmul+0xde>
8000880: ea45 0e06 orr.w lr, r5, r6
8000884: e68d b.n 80005a2 <__aeabi_dmul+0xde>
8000886: ea0c 5513 and.w r5, ip, r3, lsr #20
800088a: ea94 0f0c teq r4, ip
800088e: bf08 it eq
8000890: ea95 0f0c teqeq r5, ip
8000894: f43f af3b beq.w 800070e <__aeabi_dmul+0x24a>
8000898: ea94 0f0c teq r4, ip
800089c: d10a bne.n 80008b4 <__aeabi_ddiv+0x19c>
800089e: ea50 3401 orrs.w r4, r0, r1, lsl #12
80008a2: f47f af34 bne.w 800070e <__aeabi_dmul+0x24a>
80008a6: ea95 0f0c teq r5, ip
80008aa: f47f af25 bne.w 80006f8 <__aeabi_dmul+0x234>
80008ae: 4610 mov r0, r2
80008b0: 4619 mov r1, r3
80008b2: e72c b.n 800070e <__aeabi_dmul+0x24a>
80008b4: ea95 0f0c teq r5, ip
80008b8: d106 bne.n 80008c8 <__aeabi_ddiv+0x1b0>
80008ba: ea52 3503 orrs.w r5, r2, r3, lsl #12
80008be: f43f aefd beq.w 80006bc <__aeabi_dmul+0x1f8>
80008c2: 4610 mov r0, r2
80008c4: 4619 mov r1, r3
80008c6: e722 b.n 800070e <__aeabi_dmul+0x24a>
80008c8: ea50 0641 orrs.w r6, r0, r1, lsl #1
80008cc: bf18 it ne
80008ce: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80008d2: f47f aec5 bne.w 8000660 <__aeabi_dmul+0x19c>
80008d6: ea50 0441 orrs.w r4, r0, r1, lsl #1
80008da: f47f af0d bne.w 80006f8 <__aeabi_dmul+0x234>
80008de: ea52 0543 orrs.w r5, r2, r3, lsl #1
80008e2: f47f aeeb bne.w 80006bc <__aeabi_dmul+0x1f8>
80008e6: e712 b.n 800070e <__aeabi_dmul+0x24a>
080008e8 <__aeabi_d2uiz>:
80008e8: 004a lsls r2, r1, #1
80008ea: d211 bcs.n 8000910 <__aeabi_d2uiz+0x28>
80008ec: f512 1200 adds.w r2, r2, #2097152 ; 0x200000
80008f0: d211 bcs.n 8000916 <__aeabi_d2uiz+0x2e>
80008f2: d50d bpl.n 8000910 <__aeabi_d2uiz+0x28>
80008f4: f46f 7378 mvn.w r3, #992 ; 0x3e0
80008f8: ebb3 5262 subs.w r2, r3, r2, asr #21
80008fc: d40e bmi.n 800091c <__aeabi_d2uiz+0x34>
80008fe: ea4f 23c1 mov.w r3, r1, lsl #11
8000902: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
8000906: ea43 5350 orr.w r3, r3, r0, lsr #21
800090a: fa23 f002 lsr.w r0, r3, r2
800090e: 4770 bx lr
8000910: f04f 0000 mov.w r0, #0
8000914: 4770 bx lr
8000916: ea50 3001 orrs.w r0, r0, r1, lsl #12
800091a: d102 bne.n 8000922 <__aeabi_d2uiz+0x3a>
800091c: f04f 30ff mov.w r0, #4294967295
8000920: 4770 bx lr
8000922: f04f 0000 mov.w r0, #0
8000926: 4770 bx lr
08000928 <init_user_call>:
};
WorkMode_t WorkMode=Mode_UART;
void init_user_call()//在硬件初始化完成后调用
{
8000928: b480 push {r7}
800092a: af00 add r7, sp, #0
__HAL_UART_ENABLE_IT(&huart2,UART_IT_IDLE);//打开总线空闲中断
800092c: 4b05 ldr r3, [pc, #20] ; (8000944 <init_user_call+0x1c>)
800092e: 681b ldr r3, [r3, #0]
8000930: 68da ldr r2, [r3, #12]
8000932: 4b04 ldr r3, [pc, #16] ; (8000944 <init_user_call+0x1c>)
8000934: 681b ldr r3, [r3, #0]
8000936: f042 0210 orr.w r2, r2, #16
800093a: 60da str r2, [r3, #12]
}
800093c: bf00 nop
800093e: 46bd mov sp, r7
8000940: bc80 pop {r7}
8000942: 4770 bx lr
8000944: 20000cd0 .word 0x20000cd0
08000948 <loop_user_call>:
void loop_user_call()//在Main函数里循环调用此函数
{
8000948: b580 push {r7, lr}
800094a: af00 add r7, sp, #0
if(linecode.IsUpdate)
800094c: 4b48 ldr r3, [pc, #288] ; (8000a70 <loop_user_call+0x128>)
800094e: 7a1b ldrb r3, [r3, #8]
8000950: 2b00 cmp r3, #0
8000952: f000 808b beq.w 8000a6c <loop_user_call+0x124>
{
HAL_Delay(20);//延时20ms设置通信参数
8000956: 2014 movs r0, #20
8000958: f000 fe0a bl 8001570 <HAL_Delay>
if(linecode.Rate<1500000)//速率小于1.5Mbps，为串口模式(极其有限的串口支持)
800095c: 4b44 ldr r3, [pc, #272] ; (8000a70 <loop_user_call+0x128>)
800095e: 681b ldr r3, [r3, #0]
8000960: 4a44 ldr r2, [pc, #272] ; (8000a74 <loop_user_call+0x12c>)
8000962: 4293 cmp r3, r2
8000964: d870 bhi.n 8000a48 <loop_user_call+0x100>
{//重新初始化串口
WorkMode=Mode_UART;
8000966: 4b44 ldr r3, [pc, #272] ; (8000a78 <loop_user_call+0x130>)
8000968: 2200 movs r2, #0
800096a: 701a strb r2, [r3, #0]
huart2.Instance = USART2;
800096c: 4b43 ldr r3, [pc, #268] ; (8000a7c <loop_user_call+0x134>)
800096e: 4a44 ldr r2, [pc, #272] ; (8000a80 <loop_user_call+0x138>)
8000970: 601a str r2, [r3, #0]
huart2.Init.BaudRate = linecode.Rate;//linecode的速率
8000972: 4b3f ldr r3, [pc, #252] ; (8000a70 <loop_user_call+0x128>)
8000974: 681b ldr r3, [r3, #0]
8000976: 4a41 ldr r2, [pc, #260] ; (8000a7c <loop_user_call+0x134>)
8000978: 6053 str r3, [r2, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;//只支持8/9数据位（包括校验位）
800097a: 4b40 ldr r3, [pc, #256] ; (8000a7c <loop_user_call+0x134>)
800097c: 2200 movs r2, #0
800097e: 609a str r2, [r3, #8]
if(linecode.DataBits==8 && linecode.Parity!=0)
8000980: 4b3b ldr r3, [pc, #236] ; (8000a70 <loop_user_call+0x128>)
8000982: 88db ldrh r3, [r3, #6]
8000984: 2b08 cmp r3, #8
8000986: d107 bne.n 8000998 <loop_user_call+0x50>
8000988: 4b39 ldr r3, [pc, #228] ; (8000a70 <loop_user_call+0x128>)
800098a: 795b ldrb r3, [r3, #5]
800098c: 2b00 cmp r3, #0
800098e: d003 beq.n 8000998 <loop_user_call+0x50>
{
huart2.Init.WordLength=UART_WORDLENGTH_9B;
8000990: 4b3a ldr r3, [pc, #232] ; (8000a7c <loop_user_call+0x134>)
8000992: f44f 5280 mov.w r2, #4096 ; 0x1000
8000996: 609a str r2, [r3, #8]
}
huart2.Init.StopBits = UART_STOPBITS_1;
8000998: 4b38 ldr r3, [pc, #224] ; (8000a7c <loop_user_call+0x134>)
800099a: 2200 movs r2, #0
800099c: 60da str r2, [r3, #12]
if(linecode.StopBits==2)
800099e: 4b34 ldr r3, [pc, #208] ; (8000a70 <loop_user_call+0x128>)
80009a0: 791b ldrb r3, [r3, #4]
80009a2: 2b02 cmp r3, #2
80009a4: d103 bne.n 80009ae <loop_user_call+0x66>
{
huart2.Init.StopBits=UART_STOPBITS_2;
80009a6: 4b35 ldr r3, [pc, #212] ; (8000a7c <loop_user_call+0x134>)
80009a8: f44f 5200 mov.w r2, #8192 ; 0x2000
80009ac: 60da str r2, [r3, #12]
}
huart2.Init.Parity = UART_PARITY_NONE;
80009ae: 4b33 ldr r3, [pc, #204] ; (8000a7c <loop_user_call+0x134>)
80009b0: 2200 movs r2, #0
80009b2: 611a str r2, [r3, #16]
if(linecode.Parity==1)
80009b4: 4b2e ldr r3, [pc, #184] ; (8000a70 <loop_user_call+0x128>)
80009b6: 795b ldrb r3, [r3, #5]
80009b8: 2b01 cmp r3, #1
80009ba: d103 bne.n 80009c4 <loop_user_call+0x7c>
huart2.Init.Parity = UART_PARITY_ODD;
80009bc: 4b2f ldr r3, [pc, #188] ; (8000a7c <loop_user_call+0x134>)
80009be: f44f 62c0 mov.w r2, #1536 ; 0x600
80009c2: 611a str r2, [r3, #16]
if(linecode.Parity==2)
80009c4: 4b2a ldr r3, [pc, #168] ; (8000a70 <loop_user_call+0x128>)
80009c6: 795b ldrb r3, [r3, #5]
80009c8: 2b02 cmp r3, #2
80009ca: d103 bne.n 80009d4 <loop_user_call+0x8c>
huart2.Init.Parity = UART_PARITY_EVEN;
80009cc: 4b2b ldr r3, [pc, #172] ; (8000a7c <loop_user_call+0x134>)
80009ce: f44f 6280 mov.w r2, #1024 ; 0x400
80009d2: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
80009d4: 4b29 ldr r3, [pc, #164] ; (8000a7c <loop_user_call+0x134>)
80009d6: 220c movs r2, #12
80009d8: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;//不支持流控
80009da: 4b28 ldr r3, [pc, #160] ; (8000a7c <loop_user_call+0x134>)
80009dc: 2200 movs r2, #0
80009de: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
80009e0: 4b26 ldr r3, [pc, #152] ; (8000a7c <loop_user_call+0x134>)
80009e2: 2200 movs r2, #0
80009e4: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
80009e6: 4825 ldr r0, [pc, #148] ; (8000a7c <loop_user_call+0x134>)
80009e8: f003 fc62 bl 80042b0 <HAL_UART_Init>
80009ec: 4603 mov r3, r0
80009ee: 2b00 cmp r3, #0
80009f0: d028 beq.n 8000a44 <loop_user_call+0xfc>
{//打开失败则使用默认设置
huart2.Instance = USART2;
80009f2: 4b22 ldr r3, [pc, #136] ; (8000a7c <loop_user_call+0x134>)
80009f4: 4a22 ldr r2, [pc, #136] ; (8000a80 <loop_user_call+0x138>)
80009f6: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
80009f8: 4b20 ldr r3, [pc, #128] ; (8000a7c <loop_user_call+0x134>)
80009fa: f44f 32e1 mov.w r2, #115200 ; 0x1c200
80009fe: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
8000a00: 4b1e ldr r3, [pc, #120] ; (8000a7c <loop_user_call+0x134>)
8000a02: 2200 movs r2, #0
8000a04: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8000a06: 4b1d ldr r3, [pc, #116] ; (8000a7c <loop_user_call+0x134>)
8000a08: 2200 movs r2, #0
8000a0a: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8000a0c: 4b1b ldr r3, [pc, #108] ; (8000a7c <loop_user_call+0x134>)
8000a0e: 2200 movs r2, #0
8000a10: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
8000a12: 4b1a ldr r3, [pc, #104] ; (8000a7c <loop_user_call+0x134>)
8000a14: 220c movs r2, #12
8000a16: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000a18: 4b18 ldr r3, [pc, #96] ; (8000a7c <loop_user_call+0x134>)
8000a1a: 2200 movs r2, #0
8000a1c: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8000a1e: 4b17 ldr r3, [pc, #92] ; (8000a7c <loop_user_call+0x134>)
8000a20: 2200 movs r2, #0
8000a22: 61da str r2, [r3, #28]
HAL_UART_Init(&huart2);
8000a24: 4815 ldr r0, [pc, #84] ; (8000a7c <loop_user_call+0x134>)
8000a26: f003 fc43 bl 80042b0 <HAL_UART_Init>
linecode.DataBits=8;
8000a2a: 4b11 ldr r3, [pc, #68] ; (8000a70 <loop_user_call+0x128>)
8000a2c: 2208 movs r2, #8
8000a2e: 80da strh r2, [r3, #6]
linecode.Parity=0;
8000a30: 4b0f ldr r3, [pc, #60] ; (8000a70 <loop_user_call+0x128>)
8000a32: 2200 movs r2, #0
8000a34: 715a strb r2, [r3, #5]
linecode.Rate=115200;
8000a36: 4b0e ldr r3, [pc, #56] ; (8000a70 <loop_user_call+0x128>)
8000a38: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000a3c: 601a str r2, [r3, #0]
linecode.StopBits=0;
8000a3e: 4b0c ldr r3, [pc, #48] ; (8000a70 <loop_user_call+0x128>)
8000a40: 2200 movs r2, #0
8000a42: 711a strb r2, [r3, #4]
}
uart_start_receive();
8000a44: f000 f8da bl 8000bfc <uart_start_receive>
}
if(linecode.Rate>=2000000)//切换为spi模式
8000a48: 4b09 ldr r3, [pc, #36] ; (8000a70 <loop_user_call+0x128>)
8000a4a: 681b ldr r3, [r3, #0]
8000a4c: 4a0d ldr r2, [pc, #52] ; (8000a84 <loop_user_call+0x13c>)
8000a4e: 4293 cmp r3, r2
8000a50: d909 bls.n 8000a66 <loop_user_call+0x11e>
{
WorkMode=Mode_SPI_RAW;
8000a52: 4b09 ldr r3, [pc, #36] ; (8000a78 <loop_user_call+0x130>)
8000a54: 2201 movs r2, #1
8000a56: 701a strb r2, [r3, #0]
if(linecode.StopBits!=0)
8000a58: 4b05 ldr r3, [pc, #20] ; (8000a70 <loop_user_call+0x128>)
8000a5a: 791b ldrb r3, [r3, #4]
8000a5c: 2b00 cmp r3, #0
8000a5e: d002 beq.n 8000a66 <loop_user_call+0x11e>
{
WorkMode=Mode_SPI_CMD;
8000a60: 4b05 ldr r3, [pc, #20] ; (8000a78 <loop_user_call+0x130>)
8000a62: 2202 movs r2, #2
8000a64: 701a strb r2, [r3, #0]
}
}
linecode.IsUpdate=0;
8000a66: 4b02 ldr r3, [pc, #8] ; (8000a70 <loop_user_call+0x128>)
8000a68: 2200 movs r2, #0
8000a6a: 721a strb r2, [r3, #8]
}
}
8000a6c: bf00 nop
8000a6e: bd80 pop {r7, pc}
8000a70: 20000000 .word 0x20000000
8000a74: 0016e35f .word 0x0016e35f
8000a78: 200001a4 .word 0x200001a4
8000a7c: 20000cd0 .word 0x20000cd0
8000a80: 40004400 .word 0x40004400
8000a84: 001e847f .word 0x001e847f
08000a88 <cdc_receive_call>:
void cdc_receive_call(uint8_t* Buf, uint32_t Len)//由USB CDC/ACM接收数据时调用
{
8000a88: b580 push {r7, lr}
8000a8a: b082 sub sp, #8
8000a8c: af00 add r7, sp, #0
8000a8e: 6078 str r0, [r7, #4]
8000a90: 6039 str r1, [r7, #0]
switch(WorkMode)
8000a92: 4b0e ldr r3, [pc, #56] ; (8000acc <cdc_receive_call+0x44>)
8000a94: 781b ldrb r3, [r3, #0]
8000a96: 2b01 cmp r3, #1
8000a98: d006 beq.n 8000aa8 <cdc_receive_call+0x20>
8000a9a: 2b02 cmp r3, #2
8000a9c: d010 beq.n 8000ac0 <cdc_receive_call+0x38>
{
default:
uart_transmit(Buf,Len);
8000a9e: 6839 ldr r1, [r7, #0]
8000aa0: 6878 ldr r0, [r7, #4]
8000aa2: f000 f873 bl 8000b8c <uart_transmit>
break;
8000aa6: e00c b.n 8000ac2 <cdc_receive_call+0x3a>
case Mode_SPI_RAW:
CDC_Transmit_FS(spi_transmitReceive(Buf,Len),Len);
8000aa8: 6839 ldr r1, [r7, #0]
8000aaa: 6878 ldr r0, [r7, #4]
8000aac: f000 f836 bl 8000b1c <spi_transmitReceive>
8000ab0: 4602 mov r2, r0
8000ab2: 683b ldr r3, [r7, #0]
8000ab4: b29b uxth r3, r3
8000ab6: 4619 mov r1, r3
8000ab8: 4610 mov r0, r2
8000aba: f006 ff43 bl 8007944 <CDC_Transmit_FS>
break;
8000abe: e000 b.n 8000ac2 <cdc_receive_call+0x3a>
case Mode_SPI_CMD:
break;
8000ac0: bf00 nop
}
}
8000ac2: bf00 nop
8000ac4: 3708 adds r7, #8
8000ac6: 46bd mov sp, r7
8000ac8: bd80 pop {r7, pc}
8000aca: bf00 nop
8000acc: 200001a4 .word 0x200001a4
08000ad0 <uart_receive_call>:
void uart_receive_call(void * buf,size_t len)//接收数据完成后调用此函数
{
8000ad0: b580 push {r7, lr}
8000ad2: b082 sub sp, #8
8000ad4: af00 add r7, sp, #0
8000ad6: 6078 str r0, [r7, #4]
8000ad8: 6039 str r1, [r7, #0]
if(WorkMode!=Mode_UART)
8000ada: 4b07 ldr r3, [pc, #28] ; (8000af8 <uart_receive_call+0x28>)
8000adc: 781b ldrb r3, [r3, #0]
8000ade: 2b00 cmp r3, #0
8000ae0: d106 bne.n 8000af0 <uart_receive_call+0x20>
return;//检查模式
CDC_Transmit_FS(buf,len);//发送给上位机
8000ae2: 683b ldr r3, [r7, #0]
8000ae4: b29b uxth r3, r3
8000ae6: 4619 mov r1, r3
8000ae8: 6878 ldr r0, [r7, #4]
8000aea: f006 ff2b bl 8007944 <CDC_Transmit_FS>
8000aee: e000 b.n 8000af2 <uart_receive_call+0x22>
return;//检查模式
8000af0: bf00 nop
}
8000af2: 3708 adds r7, #8
8000af4: 46bd mov sp, r7
8000af6: bd80 pop {r7, pc}
8000af8: 200001a4 .word 0x200001a4
08000afc <delay>:
#include "userapp.h"
static uint8_t spi_rx_buff[1000];
void delay(size_t delay)//中断中不能调用HAL_Delay时使用
{
8000afc: b480 push {r7}
8000afe: b083 sub sp, #12
8000b00: af00 add r7, sp, #0
8000b02: 6078 str r0, [r7, #4]
while(delay--);
8000b04: bf00 nop
8000b06: 687b ldr r3, [r7, #4]
8000b08: 1e5a subs r2, r3, #1
8000b0a: 607a str r2, [r7, #4]
8000b0c: 2b00 cmp r3, #0
8000b0e: d1fa bne.n 8000b06 <delay+0xa>
}
8000b10: bf00 nop
8000b12: 370c adds r7, #12
8000b14: 46bd mov sp, r7
8000b16: bc80 pop {r7}
8000b18: 4770 bx lr
...
08000b1c <spi_transmitReceive>:
void * spi_transmitReceive(void * txbuff,size_t len)
{
8000b1c: b580 push {r7, lr}
8000b1e: b084 sub sp, #16
8000b20: af02 add r7, sp, #8
8000b22: 6078 str r0, [r7, #4]
8000b24: 6039 str r1, [r7, #0]
SPI_CS_HIGH();
8000b26: 2201 movs r2, #1
8000b28: 2110 movs r1, #16
8000b2a: 4815 ldr r0, [pc, #84] ; (8000b80 <spi_transmitReceive+0x64>)
8000b2c: f001 fa1a bl 8001f64 <HAL_GPIO_WritePin>
delay(48*5);//
8000b30: 20f0 movs r0, #240 ; 0xf0
8000b32: f7ff ffe3 bl 8000afc <delay>
SPI_CS_LOW();
8000b36: 2200 movs r2, #0
8000b38: 2110 movs r1, #16
8000b3a: 4811 ldr r0, [pc, #68] ; (8000b80 <spi_transmitReceive+0x64>)
8000b3c: f001 fa12 bl 8001f64 <HAL_GPIO_WritePin>
delay(48*5);
8000b40: 20f0 movs r0, #240 ; 0xf0
8000b42: f7ff ffdb bl 8000afc <delay>
memset(spi_rx_buff,0,sizeof(spi_rx_buff));
8000b46: f44f 727a mov.w r2, #1000 ; 0x3e8
8000b4a: 2100 movs r1, #0
8000b4c: 480d ldr r0, [pc, #52] ; (8000b84 <spi_transmitReceive+0x68>)
8000b4e: f007 fafa bl 8008146 <memset>
HAL_SPI_TransmitReceive(&hspi1,txbuff,spi_rx_buff,len,1000+len);
8000b52: 683b ldr r3, [r7, #0]
8000b54: b29a uxth r2, r3
8000b56: 683b ldr r3, [r7, #0]
8000b58: f503 737a add.w r3, r3, #1000 ; 0x3e8
8000b5c: 9300 str r3, [sp, #0]
8000b5e: 4613 mov r3, r2
8000b60: 4a08 ldr r2, [pc, #32] ; (8000b84 <spi_transmitReceive+0x68>)
8000b62: 6879 ldr r1, [r7, #4]
8000b64: 4808 ldr r0, [pc, #32] ; (8000b88 <spi_transmitReceive+0x6c>)
8000b66: f002 ff82 bl 8003a6e <HAL_SPI_TransmitReceive>
SPI_CS_HIGH();
8000b6a: 2201 movs r2, #1
8000b6c: 2110 movs r1, #16
8000b6e: 4804 ldr r0, [pc, #16] ; (8000b80 <spi_transmitReceive+0x64>)
8000b70: f001 f9f8 bl 8001f64 <HAL_GPIO_WritePin>
return spi_rx_buff;
8000b74: 4b03 ldr r3, [pc, #12] ; (8000b84 <spi_transmitReceive+0x68>)
}
8000b76: 4618 mov r0, r3
8000b78: 3708 adds r7, #8
8000b7a: 46bd mov sp, r7
8000b7c: bd80 pop {r7, pc}
8000b7e: bf00 nop
8000b80: 40010800 .word 0x40010800
8000b84: 200001a8 .word 0x200001a8
8000b88: 20000c78 .word 0x20000c78
08000b8c <uart_transmit>:
#include "userapp.h"
uint8_t uart_rx_buff[1000];//接收缓冲
//uint8_t uart_tx_buff[1000];//发送缓冲
uint8_t uart_transmit(void * buf,size_t len)//发送数据到串口
{
8000b8c: b5f0 push {r4, r5, r6, r7, lr}
8000b8e: b083 sub sp, #12
8000b90: af00 add r7, sp, #0
8000b92: 6078 str r0, [r7, #4]
8000b94: 6039 str r1, [r7, #0]
HAL_UART_Transmit(&huart2,buf,len,(uint32_t)(len*(1000.0/linecode.Rate))+1000);
8000b96: 683b ldr r3, [r7, #0]
8000b98: b29c uxth r4, r3
8000b9a: 6838 ldr r0, [r7, #0]
8000b9c: f7ff fc18 bl 80003d0 <__aeabi_ui2d>
8000ba0: 4605 mov r5, r0
8000ba2: 460e mov r6, r1
8000ba4: 4b12 ldr r3, [pc, #72] ; (8000bf0 <uart_transmit+0x64>)
8000ba6: 681b ldr r3, [r3, #0]
8000ba8: 4618 mov r0, r3
8000baa: f7ff fc11 bl 80003d0 <__aeabi_ui2d>
8000bae: 4602 mov r2, r0
8000bb0: 460b mov r3, r1
8000bb2: f04f 0000 mov.w r0, #0
8000bb6: 490f ldr r1, [pc, #60] ; (8000bf4 <uart_transmit+0x68>)
8000bb8: f7ff fdae bl 8000718 <__aeabi_ddiv>
8000bbc: 4602 mov r2, r0
8000bbe: 460b mov r3, r1
8000bc0: 4628 mov r0, r5
8000bc2: 4631 mov r1, r6
8000bc4: f7ff fc7e bl 80004c4 <__aeabi_dmul>
8000bc8: 4602 mov r2, r0
8000bca: 460b mov r3, r1
8000bcc: 4610 mov r0, r2
8000bce: 4619 mov r1, r3
8000bd0: f7ff fe8a bl 80008e8 <__aeabi_d2uiz>
8000bd4: 4603 mov r3, r0
8000bd6: f503 737a add.w r3, r3, #1000 ; 0x3e8
8000bda: 4622 mov r2, r4
8000bdc: 6879 ldr r1, [r7, #4]
8000bde: 4806 ldr r0, [pc, #24] ; (8000bf8 <uart_transmit+0x6c>)
8000be0: f003 fbb3 bl 800434a <HAL_UART_Transmit>
return HAL_OK;
8000be4: 2300 movs r3, #0
}
8000be6: 4618 mov r0, r3
8000be8: 370c adds r7, #12
8000bea: 46bd mov sp, r7
8000bec: bdf0 pop {r4, r5, r6, r7, pc}
8000bee: bf00 nop
8000bf0: 20000000 .word 0x20000000
8000bf4: 408f4000 .word 0x408f4000
8000bf8: 20000cd0 .word 0x20000cd0
08000bfc <uart_start_receive>:
void uart_start_receive()
{
8000bfc: b580 push {r7, lr}
8000bfe: af00 add r7, sp, #0
if(huart2.gState !=HAL_UART_STATE_READY && huart2.gState != HAL_UART_STATE_BUSY_TX)
8000c00: 4b11 ldr r3, [pc, #68] ; (8000c48 <uart_start_receive+0x4c>)
8000c02: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8000c06: b2db uxtb r3, r3
8000c08: 2b20 cmp r3, #32
8000c0a: d008 beq.n 8000c1e <uart_start_receive+0x22>
8000c0c: 4b0e ldr r3, [pc, #56] ; (8000c48 <uart_start_receive+0x4c>)
8000c0e: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8000c12: b2db uxtb r3, r3
8000c14: 2b21 cmp r3, #33 ; 0x21
8000c16: d002 beq.n 8000c1e <uart_start_receive+0x22>
HAL_UART_DMAStop(&huart2);
8000c18: 480b ldr r0, [pc, #44] ; (8000c48 <uart_start_receive+0x4c>)
8000c1a: f003 fcaf bl 800457c <HAL_UART_DMAStop>
if(huart2.gState == HAL_UART_STATE_BUSY_TX)
8000c1e: 4b0a ldr r3, [pc, #40] ; (8000c48 <uart_start_receive+0x4c>)
8000c20: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8000c24: b2db uxtb r3, r3
8000c26: 2b21 cmp r3, #33 ; 0x21
8000c28: d106 bne.n 8000c38 <uart_start_receive+0x3c>
while(huart2.gState!=HAL_UART_STATE_READY);//等待发送完成
8000c2a: bf00 nop
8000c2c: 4b06 ldr r3, [pc, #24] ; (8000c48 <uart_start_receive+0x4c>)
8000c2e: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8000c32: b2db uxtb r3, r3
8000c34: 2b20 cmp r3, #32
8000c36: d1f9 bne.n 8000c2c <uart_start_receive+0x30>
HAL_UART_Receive_DMA(&huart2,uart_rx_buff,sizeof(uart_rx_buff));
8000c38: f44f 727a mov.w r2, #1000 ; 0x3e8
8000c3c: 4903 ldr r1, [pc, #12] ; (8000c4c <uart_start_receive+0x50>)
8000c3e: 4802 ldr r0, [pc, #8] ; (8000c48 <uart_start_receive+0x4c>)
8000c40: f003 fc1c bl 800447c <HAL_UART_Receive_DMA>
}
8000c44: bf00 nop
8000c46: bd80 pop {r7, pc}
8000c48: 20000cd0 .word 0x20000cd0
8000c4c: 200007b4 .word 0x200007b4
08000c50 <uart_finish_receive>:
void uart_finish_receive()
{
8000c50: b580 push {r7, lr}
8000c52: b082 sub sp, #8
8000c54: af00 add r7, sp, #0
if(huart2.gState !=HAL_UART_STATE_READY && huart2.gState != HAL_UART_STATE_BUSY_TX)
8000c56: 4b1a ldr r3, [pc, #104] ; (8000cc0 <uart_finish_receive+0x70>)
8000c58: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8000c5c: b2db uxtb r3, r3
8000c5e: 2b20 cmp r3, #32
8000c60: d008 beq.n 8000c74 <uart_finish_receive+0x24>
8000c62: 4b17 ldr r3, [pc, #92] ; (8000cc0 <uart_finish_receive+0x70>)
8000c64: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8000c68: b2db uxtb r3, r3
8000c6a: 2b21 cmp r3, #33 ; 0x21
8000c6c: d002 beq.n 8000c74 <uart_finish_receive+0x24>
HAL_UART_DMAStop(&huart2);
8000c6e: 4814 ldr r0, [pc, #80] ; (8000cc0 <uart_finish_receive+0x70>)
8000c70: f003 fc84 bl 800457c <HAL_UART_DMAStop>
if(huart2.gState == HAL_UART_STATE_BUSY_TX)
8000c74: 4b12 ldr r3, [pc, #72] ; (8000cc0 <uart_finish_receive+0x70>)
8000c76: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8000c7a: b2db uxtb r3, r3
8000c7c: 2b21 cmp r3, #33 ; 0x21
8000c7e: d106 bne.n 8000c8e <uart_finish_receive+0x3e>
while(huart2.gState!=HAL_UART_STATE_READY);//等待发送完成
8000c80: bf00 nop
8000c82: 4b0f ldr r3, [pc, #60] ; (8000cc0 <uart_finish_receive+0x70>)
8000c84: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8000c88: b2db uxtb r3, r3
8000c8a: 2b20 cmp r3, #32
8000c8c: d1f9 bne.n 8000c82 <uart_finish_receive+0x32>
size_t count=sizeof(uart_rx_buff)-huart2.hdmarx->Instance->CNDTR;
8000c8e: 4b0c ldr r3, [pc, #48] ; (8000cc0 <uart_finish_receive+0x70>)
8000c90: 6b5b ldr r3, [r3, #52] ; 0x34
8000c92: 681b ldr r3, [r3, #0]
8000c94: 685b ldr r3, [r3, #4]
8000c96: f5c3 737a rsb r3, r3, #1000 ; 0x3e8
8000c9a: 607b str r3, [r7, #4]
uart_receive_call(uart_rx_buff,count);
8000c9c: 6879 ldr r1, [r7, #4]
8000c9e: 4809 ldr r0, [pc, #36] ; (8000cc4 <uart_finish_receive+0x74>)
8000ca0: f7ff ff16 bl 8000ad0 <uart_receive_call>
HAL_UART_DMAStop(&huart2);
8000ca4: 4806 ldr r0, [pc, #24] ; (8000cc0 <uart_finish_receive+0x70>)
8000ca6: f003 fc69 bl 800457c <HAL_UART_DMAStop>
HAL_UART_Receive_DMA(&huart2,uart_rx_buff,sizeof(uart_rx_buff));
8000caa: f44f 727a mov.w r2, #1000 ; 0x3e8
8000cae: 4905 ldr r1, [pc, #20] ; (8000cc4 <uart_finish_receive+0x74>)
8000cb0: 4803 ldr r0, [pc, #12] ; (8000cc0 <uart_finish_receive+0x70>)
8000cb2: f003 fbe3 bl 800447c <HAL_UART_Receive_DMA>
}
8000cb6: bf00 nop
8000cb8: 3708 adds r7, #8
8000cba: 46bd mov sp, r7
8000cbc: bd80 pop {r7, pc}
8000cbe: bf00 nop
8000cc0: 20000cd0 .word 0x20000cd0
8000cc4: 200007b4 .word 0x200007b4
08000cc8 <HAL_UART_RxCpltCallback>:
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)//DMA接收全满
{
8000cc8: b580 push {r7, lr}
8000cca: b082 sub sp, #8
8000ccc: af00 add r7, sp, #0
8000cce: 6078 str r0, [r7, #4]
UNUSED(huart);
uart_finish_receive();
8000cd0: f7ff ffbe bl 8000c50 <uart_finish_receive>
}
8000cd4: bf00 nop
8000cd6: 3708 adds r7, #8
8000cd8: 46bd mov sp, r7
8000cda: bd80 pop {r7, pc}
08000cdc <HAL_UART_RxHalfCpltCallback>:
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)//DMA接收半满
{
8000cdc: b580 push {r7, lr}
8000cde: b082 sub sp, #8
8000ce0: af00 add r7, sp, #0
8000ce2: 6078 str r0, [r7, #4]
UNUSED(huart);
uart_finish_receive();
8000ce4: f7ff ffb4 bl 8000c50 <uart_finish_receive>
}
8000ce8: bf00 nop
8000cea: 3708 adds r7, #8
8000cec: 46bd mov sp, r7
8000cee: bd80 pop {r7, pc}
08000cf0 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000cf0: b580 push {r7, lr}
8000cf2: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000cf4: f000 fc0a bl 800150c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000cf8: f000 f811 bl 8000d1e <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000cfc: f000 f92c bl 8000f58 <MX_GPIO_Init>
MX_DMA_Init();
8000d00: f000 f904 bl 8000f0c <MX_DMA_Init>
MX_I2C1_Init();
8000d04: f000 f862 bl 8000dcc <MX_I2C1_Init>
MX_SPI1_Init();
8000d08: f000 f8a0 bl 8000e4c <MX_SPI1_Init>
MX_USART2_UART_Init();
8000d0c: f000 f8d4 bl 8000eb8 <MX_USART2_UART_Init>
MX_USB_DEVICE_Init();
8000d10: f006 fd38 bl 8007784 <MX_USB_DEVICE_Init>
/* USER CODE BEGIN 2 */
init_user_call();
8000d14: f7ff fe08 bl 8000928 <init_user_call>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
loop_user_call();
8000d18: f7ff fe16 bl 8000948 <loop_user_call>
8000d1c: e7fc b.n 8000d18 <main+0x28>
08000d1e <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000d1e: b580 push {r7, lr}
8000d20: b094 sub sp, #80 ; 0x50
8000d22: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000d24: f107 0328 add.w r3, r7, #40 ; 0x28
8000d28: 2228 movs r2, #40 ; 0x28
8000d2a: 2100 movs r1, #0
8000d2c: 4618 mov r0, r3
8000d2e: f007 fa0a bl 8008146 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000d32: f107 0314 add.w r3, r7, #20
8000d36: 2200 movs r2, #0
8000d38: 601a str r2, [r3, #0]
8000d3a: 605a str r2, [r3, #4]
8000d3c: 609a str r2, [r3, #8]
8000d3e: 60da str r2, [r3, #12]
8000d40: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000d42: 1d3b adds r3, r7, #4
8000d44: 2200 movs r2, #0
8000d46: 601a str r2, [r3, #0]
8000d48: 605a str r2, [r3, #4]
8000d4a: 609a str r2, [r3, #8]
8000d4c: 60da str r2, [r3, #12]
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000d4e: 2302 movs r3, #2
8000d50: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000d52: 2301 movs r3, #1
8000d54: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000d56: 2310 movs r3, #16
8000d58: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000d5a: 2302 movs r3, #2
8000d5c: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
8000d5e: 2300 movs r3, #0
8000d60: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
8000d62: f44f 1320 mov.w r3, #2621440 ; 0x280000
8000d66: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000d68: f107 0328 add.w r3, r7, #40 ; 0x28
8000d6c: 4618 mov r0, r3
8000d6e: f002 f91b bl 8002fa8 <HAL_RCC_OscConfig>
8000d72: 4603 mov r3, r0
8000d74: 2b00 cmp r3, #0
8000d76: d001 beq.n 8000d7c <SystemClock_Config+0x5e>
{
Error_Handler();
8000d78: f000 f93e bl 8000ff8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000d7c: 230f movs r3, #15
8000d7e: 617b str r3, [r7, #20]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000d80: 2302 movs r3, #2
8000d82: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000d84: 2300 movs r3, #0
8000d86: 61fb str r3, [r7, #28]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
8000d88: f44f 6380 mov.w r3, #1024 ; 0x400
8000d8c: 623b str r3, [r7, #32]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000d8e: 2300 movs r3, #0
8000d90: 627b str r3, [r7, #36] ; 0x24
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
8000d92: f107 0314 add.w r3, r7, #20
8000d96: 2101 movs r1, #1
8000d98: 4618 mov r0, r3
8000d9a: f002 fb85 bl 80034a8 <HAL_RCC_ClockConfig>
8000d9e: 4603 mov r3, r0
8000da0: 2b00 cmp r3, #0
8000da2: d001 beq.n 8000da8 <SystemClock_Config+0x8a>
{
Error_Handler();
8000da4: f000 f928 bl 8000ff8 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
8000da8: 2310 movs r3, #16
8000daa: 607b str r3, [r7, #4]
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
8000dac: f44f 0380 mov.w r3, #4194304 ; 0x400000
8000db0: 613b str r3, [r7, #16]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000db2: 1d3b adds r3, r7, #4
8000db4: 4618 mov r0, r3
8000db6: f002 fd43 bl 8003840 <HAL_RCCEx_PeriphCLKConfig>
8000dba: 4603 mov r3, r0
8000dbc: 2b00 cmp r3, #0
8000dbe: d001 beq.n 8000dc4 <SystemClock_Config+0xa6>
{
Error_Handler();
8000dc0: f000 f91a bl 8000ff8 <Error_Handler>
}
}
8000dc4: bf00 nop
8000dc6: 3750 adds r7, #80 ; 0x50
8000dc8: 46bd mov sp, r7
8000dca: bd80 pop {r7, pc}
08000dcc <MX_I2C1_Init>:
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
8000dcc: b580 push {r7, lr}
8000dce: b082 sub sp, #8
8000dd0: af00 add r7, sp, #0
/* USER CODE BEGIN I2C1_Init 0 */
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
__HAL_RCC_I2C1_CLK_ENABLE();
8000dd2: 4b1a ldr r3, [pc, #104] ; (8000e3c <MX_I2C1_Init+0x70>)
8000dd4: 69db ldr r3, [r3, #28]
8000dd6: 4a19 ldr r2, [pc, #100] ; (8000e3c <MX_I2C1_Init+0x70>)
8000dd8: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
8000ddc: 61d3 str r3, [r2, #28]
8000dde: 4b17 ldr r3, [pc, #92] ; (8000e3c <MX_I2C1_Init+0x70>)
8000de0: 69db ldr r3, [r3, #28]
8000de2: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000de6: 607b str r3, [r7, #4]
8000de8: 687b ldr r3, [r7, #4]
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
8000dea: 4b15 ldr r3, [pc, #84] ; (8000e40 <MX_I2C1_Init+0x74>)
8000dec: 4a15 ldr r2, [pc, #84] ; (8000e44 <MX_I2C1_Init+0x78>)
8000dee: 601a str r2, [r3, #0]
hi2c1.Init.ClockSpeed = 100000;
8000df0: 4b13 ldr r3, [pc, #76] ; (8000e40 <MX_I2C1_Init+0x74>)
8000df2: 4a15 ldr r2, [pc, #84] ; (8000e48 <MX_I2C1_Init+0x7c>)
8000df4: 605a str r2, [r3, #4]
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
8000df6: 4b12 ldr r3, [pc, #72] ; (8000e40 <MX_I2C1_Init+0x74>)
8000df8: 2200 movs r2, #0
8000dfa: 609a str r2, [r3, #8]
hi2c1.Init.OwnAddress1 = 0;
8000dfc: 4b10 ldr r3, [pc, #64] ; (8000e40 <MX_I2C1_Init+0x74>)
8000dfe: 2200 movs r2, #0
8000e00: 60da str r2, [r3, #12]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8000e02: 4b0f ldr r3, [pc, #60] ; (8000e40 <MX_I2C1_Init+0x74>)
8000e04: f44f 4280 mov.w r2, #16384 ; 0x4000
8000e08: 611a str r2, [r3, #16]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8000e0a: 4b0d ldr r3, [pc, #52] ; (8000e40 <MX_I2C1_Init+0x74>)
8000e0c: 2200 movs r2, #0
8000e0e: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2 = 0;
8000e10: 4b0b ldr r3, [pc, #44] ; (8000e40 <MX_I2C1_Init+0x74>)
8000e12: 2200 movs r2, #0
8000e14: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8000e16: 4b0a ldr r3, [pc, #40] ; (8000e40 <MX_I2C1_Init+0x74>)
8000e18: 2200 movs r2, #0
8000e1a: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8000e1c: 4b08 ldr r3, [pc, #32] ; (8000e40 <MX_I2C1_Init+0x74>)
8000e1e: 2200 movs r2, #0
8000e20: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
8000e22: 4807 ldr r0, [pc, #28] ; (8000e40 <MX_I2C1_Init+0x74>)
8000e24: f001 f8b6 bl 8001f94 <HAL_I2C_Init>
8000e28: 4603 mov r3, r0
8000e2a: 2b00 cmp r3, #0
8000e2c: d001 beq.n 8000e32 <MX_I2C1_Init+0x66>
{
Error_Handler();
8000e2e: f000 f8e3 bl 8000ff8 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
8000e32: bf00 nop
8000e34: 3708 adds r7, #8
8000e36: 46bd mov sp, r7
8000e38: bd80 pop {r7, pc}
8000e3a: bf00 nop
8000e3c: 40021000 .word 0x40021000
8000e40: 20000be0 .word 0x20000be0
8000e44: 40005400 .word 0x40005400
8000e48: 000186a0 .word 0x000186a0
08000e4c <MX_SPI1_Init>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
8000e4c: b580 push {r7, lr}
8000e4e: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
8000e50: 4b17 ldr r3, [pc, #92] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e52: 4a18 ldr r2, [pc, #96] ; (8000eb4 <MX_SPI1_Init+0x68>)
8000e54: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
8000e56: 4b16 ldr r3, [pc, #88] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e58: f44f 7282 mov.w r2, #260 ; 0x104
8000e5c: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
8000e5e: 4b14 ldr r3, [pc, #80] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e60: 2200 movs r2, #0
8000e62: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
8000e64: 4b12 ldr r3, [pc, #72] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e66: 2200 movs r2, #0
8000e68: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
8000e6a: 4b11 ldr r3, [pc, #68] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e6c: 2200 movs r2, #0
8000e6e: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
8000e70: 4b0f ldr r3, [pc, #60] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e72: 2200 movs r2, #0
8000e74: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
8000e76: 4b0e ldr r3, [pc, #56] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e78: f44f 7200 mov.w r2, #512 ; 0x200
8000e7c: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
8000e7e: 4b0c ldr r3, [pc, #48] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e80: 2220 movs r2, #32
8000e82: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000e84: 4b0a ldr r3, [pc, #40] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e86: 2200 movs r2, #0
8000e88: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8000e8a: 4b09 ldr r3, [pc, #36] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e8c: 2200 movs r2, #0
8000e8e: 625a str r2, [r3, #36] ; 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000e90: 4b07 ldr r3, [pc, #28] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e92: 2200 movs r2, #0
8000e94: 629a str r2, [r3, #40] ; 0x28
hspi1.Init.CRCPolynomial = 10;
8000e96: 4b06 ldr r3, [pc, #24] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e98: 220a movs r2, #10
8000e9a: 62da str r2, [r3, #44] ; 0x2c
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8000e9c: 4804 ldr r0, [pc, #16] ; (8000eb0 <MX_SPI1_Init+0x64>)
8000e9e: f002 fd85 bl 80039ac <HAL_SPI_Init>
8000ea2: 4603 mov r3, r0
8000ea4: 2b00 cmp r3, #0
8000ea6: d001 beq.n 8000eac <MX_SPI1_Init+0x60>
{
Error_Handler();
8000ea8: f000 f8a6 bl 8000ff8 <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
8000eac: bf00 nop
8000eae: bd80 pop {r7, pc}
8000eb0: 20000c78 .word 0x20000c78
8000eb4: 40013000 .word 0x40013000
08000eb8 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
8000eb8: b580 push {r7, lr}
8000eba: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
8000ebc: 4b11 ldr r3, [pc, #68] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000ebe: 4a12 ldr r2, [pc, #72] ; (8000f08 <MX_USART2_UART_Init+0x50>)
8000ec0: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
8000ec2: 4b10 ldr r3, [pc, #64] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000ec4: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000ec8: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
8000eca: 4b0e ldr r3, [pc, #56] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000ecc: 2200 movs r2, #0
8000ece: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8000ed0: 4b0c ldr r3, [pc, #48] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000ed2: 2200 movs r2, #0
8000ed4: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8000ed6: 4b0b ldr r3, [pc, #44] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000ed8: 2200 movs r2, #0
8000eda: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
8000edc: 4b09 ldr r3, [pc, #36] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000ede: 220c movs r2, #12
8000ee0: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
8000ee2: 4b08 ldr r3, [pc, #32] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000ee4: f44f 7240 mov.w r2, #768 ; 0x300
8000ee8: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8000eea: 4b06 ldr r3, [pc, #24] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000eec: 2200 movs r2, #0
8000eee: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
8000ef0: 4804 ldr r0, [pc, #16] ; (8000f04 <MX_USART2_UART_Init+0x4c>)
8000ef2: f003 f9dd bl 80042b0 <HAL_UART_Init>
8000ef6: 4603 mov r3, r0
8000ef8: 2b00 cmp r3, #0
8000efa: d001 beq.n 8000f00 <MX_USART2_UART_Init+0x48>
{
Error_Handler();
8000efc: f000 f87c bl 8000ff8 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
8000f00: bf00 nop
8000f02: bd80 pop {r7, pc}
8000f04: 20000cd0 .word 0x20000cd0
8000f08: 40004400 .word 0x40004400
08000f0c <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
8000f0c: b580 push {r7, lr}
8000f0e: b082 sub sp, #8
8000f10: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
8000f12: 4b10 ldr r3, [pc, #64] ; (8000f54 <MX_DMA_Init+0x48>)
8000f14: 695b ldr r3, [r3, #20]
8000f16: 4a0f ldr r2, [pc, #60] ; (8000f54 <MX_DMA_Init+0x48>)
8000f18: f043 0301 orr.w r3, r3, #1
8000f1c: 6153 str r3, [r2, #20]
8000f1e: 4b0d ldr r3, [pc, #52] ; (8000f54 <MX_DMA_Init+0x48>)
8000f20: 695b ldr r3, [r3, #20]
8000f22: f003 0301 and.w r3, r3, #1
8000f26: 607b str r3, [r7, #4]
8000f28: 687b ldr r3, [r7, #4]
/* DMA interrupt init */
/* DMA1_Channel6_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 0, 0);
8000f2a: 2200 movs r2, #0
8000f2c: 2100 movs r1, #0
8000f2e: 2010 movs r0, #16
8000f30: f000 fbf5 bl 800171e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn);
8000f34: 2010 movs r0, #16
8000f36: f000 fc0e bl 8001756 <HAL_NVIC_EnableIRQ>
/* DMA1_Channel7_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
8000f3a: 2200 movs r2, #0
8000f3c: 2100 movs r1, #0
8000f3e: 2011 movs r0, #17
8000f40: f000 fbed bl 800171e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
8000f44: 2011 movs r0, #17
8000f46: f000 fc06 bl 8001756 <HAL_NVIC_EnableIRQ>
}
8000f4a: bf00 nop
8000f4c: 3708 adds r7, #8
8000f4e: 46bd mov sp, r7
8000f50: bd80 pop {r7, pc}
8000f52: bf00 nop
8000f54: 40021000 .word 0x40021000
08000f58 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000f58: b580 push {r7, lr}
8000f5a: b086 sub sp, #24
8000f5c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000f5e: f107 0308 add.w r3, r7, #8
8000f62: 2200 movs r2, #0
8000f64: 601a str r2, [r3, #0]
8000f66: 605a str r2, [r3, #4]
8000f68: 609a str r2, [r3, #8]
8000f6a: 60da str r2, [r3, #12]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000f6c: 4b17 ldr r3, [pc, #92] ; (8000fcc <MX_GPIO_Init+0x74>)
8000f6e: 699b ldr r3, [r3, #24]
8000f70: 4a16 ldr r2, [pc, #88] ; (8000fcc <MX_GPIO_Init+0x74>)
8000f72: f043 0304 orr.w r3, r3, #4
8000f76: 6193 str r3, [r2, #24]
8000f78: 4b14 ldr r3, [pc, #80] ; (8000fcc <MX_GPIO_Init+0x74>)
8000f7a: 699b ldr r3, [r3, #24]
8000f7c: f003 0304 and.w r3, r3, #4
8000f80: 607b str r3, [r7, #4]
8000f82: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000f84: 4b11 ldr r3, [pc, #68] ; (8000fcc <MX_GPIO_Init+0x74>)
8000f86: 699b ldr r3, [r3, #24]
8000f88: 4a10 ldr r2, [pc, #64] ; (8000fcc <MX_GPIO_Init+0x74>)
8000f8a: f043 0308 orr.w r3, r3, #8
8000f8e: 6193 str r3, [r2, #24]
8000f90: 4b0e ldr r3, [pc, #56] ; (8000fcc <MX_GPIO_Init+0x74>)
8000f92: 699b ldr r3, [r3, #24]
8000f94: f003 0308 and.w r3, r3, #8
8000f98: 603b str r3, [r7, #0]
8000f9a: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET);
8000f9c: 2201 movs r2, #1
8000f9e: 2110 movs r1, #16
8000fa0: 480b ldr r0, [pc, #44] ; (8000fd0 <MX_GPIO_Init+0x78>)
8000fa2: f000 ffdf bl 8001f64 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PA4 */
GPIO_InitStruct.Pin = GPIO_PIN_4;
8000fa6: 2310 movs r3, #16
8000fa8: 60bb str r3, [r7, #8]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000faa: 2301 movs r3, #1
8000fac: 60fb str r3, [r7, #12]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000fae: 2300 movs r3, #0
8000fb0: 613b str r3, [r7, #16]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000fb2: 2303 movs r3, #3
8000fb4: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000fb6: f107 0308 add.w r3, r7, #8
8000fba: 4619 mov r1, r3
8000fbc: 4804 ldr r0, [pc, #16] ; (8000fd0 <MX_GPIO_Init+0x78>)
8000fbe: f000 fe77 bl 8001cb0 <HAL_GPIO_Init>
}
8000fc2: bf00 nop
8000fc4: 3718 adds r7, #24
8000fc6: 46bd mov sp, r7
8000fc8: bd80 pop {r7, pc}
8000fca: bf00 nop
8000fcc: 40021000 .word 0x40021000
8000fd0: 40010800 .word 0x40010800
08000fd4 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8000fd4: b580 push {r7, lr}
8000fd6: b082 sub sp, #8
8000fd8: af00 add r7, sp, #0
8000fda: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM4) {
8000fdc: 687b ldr r3, [r7, #4]
8000fde: 681b ldr r3, [r3, #0]
8000fe0: 4a04 ldr r2, [pc, #16] ; (8000ff4 <HAL_TIM_PeriodElapsedCallback+0x20>)
8000fe2: 4293 cmp r3, r2
8000fe4: d101 bne.n 8000fea <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
8000fe6: f000 faa7 bl 8001538 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8000fea: bf00 nop
8000fec: 3708 adds r7, #8
8000fee: 46bd mov sp, r7
8000ff0: bd80 pop {r7, pc}
8000ff2: bf00 nop
8000ff4: 40000800 .word 0x40000800
08000ff8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000ff8: b480 push {r7}
8000ffa: af00 add r7, sp, #0
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
8000ffc: bf00 nop
8000ffe: 46bd mov sp, r7
8001000: bc80 pop {r7}
8001002: 4770 bx lr
08001004 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001004: b480 push {r7}
8001006: b085 sub sp, #20
8001008: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
800100a: 4b15 ldr r3, [pc, #84] ; (8001060 <HAL_MspInit+0x5c>)
800100c: 699b ldr r3, [r3, #24]
800100e: 4a14 ldr r2, [pc, #80] ; (8001060 <HAL_MspInit+0x5c>)
8001010: f043 0301 orr.w r3, r3, #1
8001014: 6193 str r3, [r2, #24]
8001016: 4b12 ldr r3, [pc, #72] ; (8001060 <HAL_MspInit+0x5c>)
8001018: 699b ldr r3, [r3, #24]
800101a: f003 0301 and.w r3, r3, #1
800101e: 60bb str r3, [r7, #8]
8001020: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8001022: 4b0f ldr r3, [pc, #60] ; (8001060 <HAL_MspInit+0x5c>)
8001024: 69db ldr r3, [r3, #28]
8001026: 4a0e ldr r2, [pc, #56] ; (8001060 <HAL_MspInit+0x5c>)
8001028: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800102c: 61d3 str r3, [r2, #28]
800102e: 4b0c ldr r3, [pc, #48] ; (8001060 <HAL_MspInit+0x5c>)
8001030: 69db ldr r3, [r3, #28]
8001032: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001036: 607b str r3, [r7, #4]
8001038: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
800103a: 4b0a ldr r3, [pc, #40] ; (8001064 <HAL_MspInit+0x60>)
800103c: 685b ldr r3, [r3, #4]
800103e: 60fb str r3, [r7, #12]
8001040: 68fb ldr r3, [r7, #12]
8001042: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
8001046: 60fb str r3, [r7, #12]
8001048: 68fb ldr r3, [r7, #12]
800104a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800104e: 60fb str r3, [r7, #12]
8001050: 4a04 ldr r2, [pc, #16] ; (8001064 <HAL_MspInit+0x60>)
8001052: 68fb ldr r3, [r7, #12]
8001054: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001056: bf00 nop
8001058: 3714 adds r7, #20
800105a: 46bd mov sp, r7
800105c: bc80 pop {r7}
800105e: 4770 bx lr
8001060: 40021000 .word 0x40021000
8001064: 40010000 .word 0x40010000
08001068 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8001068: b580 push {r7, lr}
800106a: b088 sub sp, #32
800106c: af00 add r7, sp, #0
800106e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001070: f107 0310 add.w r3, r7, #16
8001074: 2200 movs r2, #0
8001076: 601a str r2, [r3, #0]
8001078: 605a str r2, [r3, #4]
800107a: 609a str r2, [r3, #8]
800107c: 60da str r2, [r3, #12]
if(hi2c->Instance==I2C1)
800107e: 687b ldr r3, [r7, #4]
8001080: 681b ldr r3, [r3, #0]
8001082: 4a15 ldr r2, [pc, #84] ; (80010d8 <HAL_I2C_MspInit+0x70>)
8001084: 4293 cmp r3, r2
8001086: d123 bne.n 80010d0 <HAL_I2C_MspInit+0x68>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8001088: 4b14 ldr r3, [pc, #80] ; (80010dc <HAL_I2C_MspInit+0x74>)
800108a: 699b ldr r3, [r3, #24]
800108c: 4a13 ldr r2, [pc, #76] ; (80010dc <HAL_I2C_MspInit+0x74>)
800108e: f043 0308 orr.w r3, r3, #8
8001092: 6193 str r3, [r2, #24]
8001094: 4b11 ldr r3, [pc, #68] ; (80010dc <HAL_I2C_MspInit+0x74>)
8001096: 699b ldr r3, [r3, #24]
8001098: f003 0308 and.w r3, r3, #8
800109c: 60fb str r3, [r7, #12]
800109e: 68fb ldr r3, [r7, #12]
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
80010a0: 23c0 movs r3, #192 ; 0xc0
80010a2: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80010a4: 2312 movs r3, #18
80010a6: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80010a8: 2303 movs r3, #3
80010aa: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80010ac: f107 0310 add.w r3, r7, #16
80010b0: 4619 mov r1, r3
80010b2: 480b ldr r0, [pc, #44] ; (80010e0 <HAL_I2C_MspInit+0x78>)
80010b4: f000 fdfc bl 8001cb0 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
80010b8: 4b08 ldr r3, [pc, #32] ; (80010dc <HAL_I2C_MspInit+0x74>)
80010ba: 69db ldr r3, [r3, #28]
80010bc: 4a07 ldr r2, [pc, #28] ; (80010dc <HAL_I2C_MspInit+0x74>)
80010be: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
80010c2: 61d3 str r3, [r2, #28]
80010c4: 4b05 ldr r3, [pc, #20] ; (80010dc <HAL_I2C_MspInit+0x74>)
80010c6: 69db ldr r3, [r3, #28]
80010c8: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80010cc: 60bb str r3, [r7, #8]
80010ce: 68bb ldr r3, [r7, #8]
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
80010d0: bf00 nop
80010d2: 3720 adds r7, #32
80010d4: 46bd mov sp, r7
80010d6: bd80 pop {r7, pc}
80010d8: 40005400 .word 0x40005400
80010dc: 40021000 .word 0x40021000
80010e0: 40010c00 .word 0x40010c00
080010e4 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80010e4: b580 push {r7, lr}
80010e6: b088 sub sp, #32
80010e8: af00 add r7, sp, #0
80010ea: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80010ec: f107 0310 add.w r3, r7, #16
80010f0: 2200 movs r2, #0
80010f2: 601a str r2, [r3, #0]
80010f4: 605a str r2, [r3, #4]
80010f6: 609a str r2, [r3, #8]
80010f8: 60da str r2, [r3, #12]
if(hspi->Instance==SPI1)
80010fa: 687b ldr r3, [r7, #4]
80010fc: 681b ldr r3, [r3, #0]
80010fe: 4a1b ldr r2, [pc, #108] ; (800116c <HAL_SPI_MspInit+0x88>)
8001100: 4293 cmp r3, r2
8001102: d12f bne.n 8001164 <HAL_SPI_MspInit+0x80>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
8001104: 4b1a ldr r3, [pc, #104] ; (8001170 <HAL_SPI_MspInit+0x8c>)
8001106: 699b ldr r3, [r3, #24]
8001108: 4a19 ldr r2, [pc, #100] ; (8001170 <HAL_SPI_MspInit+0x8c>)
800110a: f443 5380 orr.w r3, r3, #4096 ; 0x1000
800110e: 6193 str r3, [r2, #24]
8001110: 4b17 ldr r3, [pc, #92] ; (8001170 <HAL_SPI_MspInit+0x8c>)
8001112: 699b ldr r3, [r3, #24]
8001114: f403 5380 and.w r3, r3, #4096 ; 0x1000
8001118: 60fb str r3, [r7, #12]
800111a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800111c: 4b14 ldr r3, [pc, #80] ; (8001170 <HAL_SPI_MspInit+0x8c>)
800111e: 699b ldr r3, [r3, #24]
8001120: 4a13 ldr r2, [pc, #76] ; (8001170 <HAL_SPI_MspInit+0x8c>)
8001122: f043 0304 orr.w r3, r3, #4
8001126: 6193 str r3, [r2, #24]
8001128: 4b11 ldr r3, [pc, #68] ; (8001170 <HAL_SPI_MspInit+0x8c>)
800112a: 699b ldr r3, [r3, #24]
800112c: f003 0304 and.w r3, r3, #4
8001130: 60bb str r3, [r7, #8]
8001132: 68bb ldr r3, [r7, #8]
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;
8001134: 23a0 movs r3, #160 ; 0xa0
8001136: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001138: 2302 movs r3, #2
800113a: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
800113c: 2303 movs r3, #3
800113e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001140: f107 0310 add.w r3, r7, #16
8001144: 4619 mov r1, r3
8001146: 480b ldr r0, [pc, #44] ; (8001174 <HAL_SPI_MspInit+0x90>)
8001148: f000 fdb2 bl 8001cb0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_6;
800114c: 2340 movs r3, #64 ; 0x40
800114e: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001150: 2300 movs r3, #0
8001152: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001154: 2300 movs r3, #0
8001156: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001158: f107 0310 add.w r3, r7, #16
800115c: 4619 mov r1, r3
800115e: 4805 ldr r0, [pc, #20] ; (8001174 <HAL_SPI_MspInit+0x90>)
8001160: f000 fda6 bl 8001cb0 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
8001164: bf00 nop
8001166: 3720 adds r7, #32
8001168: 46bd mov sp, r7
800116a: bd80 pop {r7, pc}
800116c: 40013000 .word 0x40013000
8001170: 40021000 .word 0x40021000
8001174: 40010800 .word 0x40010800
08001178 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001178: b580 push {r7, lr}
800117a: b088 sub sp, #32
800117c: af00 add r7, sp, #0
800117e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001180: f107 0310 add.w r3, r7, #16
8001184: 2200 movs r2, #0
8001186: 601a str r2, [r3, #0]
8001188: 605a str r2, [r3, #4]
800118a: 609a str r2, [r3, #8]
800118c: 60da str r2, [r3, #12]
if(huart->Instance==USART2)
800118e: 687b ldr r3, [r7, #4]
8001190: 681b ldr r3, [r3, #0]
8001192: 4a4c ldr r2, [pc, #304] ; (80012c4 <HAL_UART_MspInit+0x14c>)
8001194: 4293 cmp r3, r2
8001196: f040 8091 bne.w 80012bc <HAL_UART_MspInit+0x144>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
800119a: 4b4b ldr r3, [pc, #300] ; (80012c8 <HAL_UART_MspInit+0x150>)
800119c: 69db ldr r3, [r3, #28]
800119e: 4a4a ldr r2, [pc, #296] ; (80012c8 <HAL_UART_MspInit+0x150>)
80011a0: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80011a4: 61d3 str r3, [r2, #28]
80011a6: 4b48 ldr r3, [pc, #288] ; (80012c8 <HAL_UART_MspInit+0x150>)
80011a8: 69db ldr r3, [r3, #28]
80011aa: f403 3300 and.w r3, r3, #131072 ; 0x20000
80011ae: 60fb str r3, [r7, #12]
80011b0: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80011b2: 4b45 ldr r3, [pc, #276] ; (80012c8 <HAL_UART_MspInit+0x150>)
80011b4: 699b ldr r3, [r3, #24]
80011b6: 4a44 ldr r2, [pc, #272] ; (80012c8 <HAL_UART_MspInit+0x150>)
80011b8: f043 0304 orr.w r3, r3, #4
80011bc: 6193 str r3, [r2, #24]
80011be: 4b42 ldr r3, [pc, #264] ; (80012c8 <HAL_UART_MspInit+0x150>)
80011c0: 699b ldr r3, [r3, #24]
80011c2: f003 0304 and.w r3, r3, #4
80011c6: 60bb str r3, [r7, #8]
80011c8: 68bb ldr r3, [r7, #8]
PA0-WKUP ------> USART2_CTS
PA1 ------> USART2_RTS
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
80011ca: 2301 movs r3, #1
80011cc: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80011ce: 2300 movs r3, #0
80011d0: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011d2: 2300 movs r3, #0
80011d4: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80011d6: f107 0310 add.w r3, r7, #16
80011da: 4619 mov r1, r3
80011dc: 483b ldr r0, [pc, #236] ; (80012cc <HAL_UART_MspInit+0x154>)
80011de: f000 fd67 bl 8001cb0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2;
80011e2: 2306 movs r3, #6
80011e4: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80011e6: 2302 movs r3, #2
80011e8: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80011ea: 2303 movs r3, #3
80011ec: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80011ee: f107 0310 add.w r3, r7, #16
80011f2: 4619 mov r1, r3
80011f4: 4835 ldr r0, [pc, #212] ; (80012cc <HAL_UART_MspInit+0x154>)
80011f6: f000 fd5b bl 8001cb0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_3;
80011fa: 2308 movs r3, #8
80011fc: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80011fe: 2300 movs r3, #0
8001200: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001202: 2301 movs r3, #1
8001204: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001206: f107 0310 add.w r3, r7, #16
800120a: 4619 mov r1, r3
800120c: 482f ldr r0, [pc, #188] ; (80012cc <HAL_UART_MspInit+0x154>)
800120e: f000 fd4f bl 8001cb0 <HAL_GPIO_Init>
/* USART2 DMA Init */
/* USART2_RX Init */
hdma_usart2_rx.Instance = DMA1_Channel6;
8001212: 4b2f ldr r3, [pc, #188] ; (80012d0 <HAL_UART_MspInit+0x158>)
8001214: 4a2f ldr r2, [pc, #188] ; (80012d4 <HAL_UART_MspInit+0x15c>)
8001216: 601a str r2, [r3, #0]
hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
8001218: 4b2d ldr r3, [pc, #180] ; (80012d0 <HAL_UART_MspInit+0x158>)
800121a: 2200 movs r2, #0
800121c: 605a str r2, [r3, #4]
hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
800121e: 4b2c ldr r3, [pc, #176] ; (80012d0 <HAL_UART_MspInit+0x158>)
8001220: 2200 movs r2, #0
8001222: 609a str r2, [r3, #8]
hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
8001224: 4b2a ldr r3, [pc, #168] ; (80012d0 <HAL_UART_MspInit+0x158>)
8001226: 2280 movs r2, #128 ; 0x80
8001228: 60da str r2, [r3, #12]
hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
800122a: 4b29 ldr r3, [pc, #164] ; (80012d0 <HAL_UART_MspInit+0x158>)
800122c: 2200 movs r2, #0
800122e: 611a str r2, [r3, #16]
hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
8001230: 4b27 ldr r3, [pc, #156] ; (80012d0 <HAL_UART_MspInit+0x158>)
8001232: 2200 movs r2, #0
8001234: 615a str r2, [r3, #20]
hdma_usart2_rx.Init.Mode = DMA_NORMAL;
8001236: 4b26 ldr r3, [pc, #152] ; (80012d0 <HAL_UART_MspInit+0x158>)
8001238: 2200 movs r2, #0
800123a: 619a str r2, [r3, #24]
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH;
800123c: 4b24 ldr r3, [pc, #144] ; (80012d0 <HAL_UART_MspInit+0x158>)
800123e: f44f 5240 mov.w r2, #12288 ; 0x3000
8001242: 61da str r2, [r3, #28]
if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
8001244: 4822 ldr r0, [pc, #136] ; (80012d0 <HAL_UART_MspInit+0x158>)
8001246: f000 fa95 bl 8001774 <HAL_DMA_Init>
800124a: 4603 mov r3, r0
800124c: 2b00 cmp r3, #0
800124e: d001 beq.n 8001254 <HAL_UART_MspInit+0xdc>
{
Error_Handler();
8001250: f7ff fed2 bl 8000ff8 <Error_Handler>
}
__HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx);
8001254: 687b ldr r3, [r7, #4]
8001256: 4a1e ldr r2, [pc, #120] ; (80012d0 <HAL_UART_MspInit+0x158>)
8001258: 635a str r2, [r3, #52] ; 0x34
800125a: 4a1d ldr r2, [pc, #116] ; (80012d0 <HAL_UART_MspInit+0x158>)
800125c: 687b ldr r3, [r7, #4]
800125e: 6253 str r3, [r2, #36] ; 0x24
/* USART2_TX Init */
hdma_usart2_tx.Instance = DMA1_Channel7;
8001260: 4b1d ldr r3, [pc, #116] ; (80012d8 <HAL_UART_MspInit+0x160>)
8001262: 4a1e ldr r2, [pc, #120] ; (80012dc <HAL_UART_MspInit+0x164>)
8001264: 601a str r2, [r3, #0]
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
8001266: 4b1c ldr r3, [pc, #112] ; (80012d8 <HAL_UART_MspInit+0x160>)
8001268: 2210 movs r2, #16
800126a: 605a str r2, [r3, #4]
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
800126c: 4b1a ldr r3, [pc, #104] ; (80012d8 <HAL_UART_MspInit+0x160>)
800126e: 2200 movs r2, #0
8001270: 609a str r2, [r3, #8]
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
8001272: 4b19 ldr r3, [pc, #100] ; (80012d8 <HAL_UART_MspInit+0x160>)
8001274: 2280 movs r2, #128 ; 0x80
8001276: 60da str r2, [r3, #12]
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
8001278: 4b17 ldr r3, [pc, #92] ; (80012d8 <HAL_UART_MspInit+0x160>)
800127a: 2200 movs r2, #0
800127c: 611a str r2, [r3, #16]
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
800127e: 4b16 ldr r3, [pc, #88] ; (80012d8 <HAL_UART_MspInit+0x160>)
8001280: 2200 movs r2, #0
8001282: 615a str r2, [r3, #20]
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
8001284: 4b14 ldr r3, [pc, #80] ; (80012d8 <HAL_UART_MspInit+0x160>)
8001286: 2200 movs r2, #0
8001288: 619a str r2, [r3, #24]
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
800128a: 4b13 ldr r3, [pc, #76] ; (80012d8 <HAL_UART_MspInit+0x160>)
800128c: 2200 movs r2, #0
800128e: 61da str r2, [r3, #28]
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
8001290: 4811 ldr r0, [pc, #68] ; (80012d8 <HAL_UART_MspInit+0x160>)
8001292: f000 fa6f bl 8001774 <HAL_DMA_Init>
8001296: 4603 mov r3, r0
8001298: 2b00 cmp r3, #0
800129a: d001 beq.n 80012a0 <HAL_UART_MspInit+0x128>
{
Error_Handler();
800129c: f7ff feac bl 8000ff8 <Error_Handler>
}
__HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
80012a0: 687b ldr r3, [r7, #4]
80012a2: 4a0d ldr r2, [pc, #52] ; (80012d8 <HAL_UART_MspInit+0x160>)
80012a4: 631a str r2, [r3, #48] ; 0x30
80012a6: 4a0c ldr r2, [pc, #48] ; (80012d8 <HAL_UART_MspInit+0x160>)
80012a8: 687b ldr r3, [r7, #4]
80012aa: 6253 str r3, [r2, #36] ; 0x24
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
80012ac: 2200 movs r2, #0
80012ae: 2100 movs r1, #0
80012b0: 2026 movs r0, #38 ; 0x26
80012b2: f000 fa34 bl 800171e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART2_IRQn);
80012b6: 2026 movs r0, #38 ; 0x26
80012b8: f000 fa4d bl 8001756 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
80012bc: bf00 nop
80012be: 3720 adds r7, #32
80012c0: 46bd mov sp, r7
80012c2: bd80 pop {r7, pc}
80012c4: 40004400 .word 0x40004400
80012c8: 40021000 .word 0x40021000
80012cc: 40010800 .word 0x40010800
80012d0: 20000b9c .word 0x20000b9c
80012d4: 4002006c .word 0x4002006c
80012d8: 20000c34 .word 0x20000c34
80012dc: 40020080 .word 0x40020080
080012e0 <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80012e0: b580 push {r7, lr}
80012e2: b08c sub sp, #48 ; 0x30
80012e4: af00 add r7, sp, #0
80012e6: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
80012e8: 2300 movs r3, #0
80012ea: 62fb str r3, [r7, #44] ; 0x2c
uint32_t uwPrescalerValue = 0;
80012ec: 2300 movs r3, #0
80012ee: 62bb str r3, [r7, #40] ; 0x28
uint32_t pFLatency;
/*Configure the TIM4 IRQ priority */
HAL_NVIC_SetPriority(TIM4_IRQn, TickPriority ,0);
80012f0: 2200 movs r2, #0
80012f2: 6879 ldr r1, [r7, #4]
80012f4: 201e movs r0, #30
80012f6: f000 fa12 bl 800171e <HAL_NVIC_SetPriority>
/* Enable the TIM4 global Interrupt */
HAL_NVIC_EnableIRQ(TIM4_IRQn);
80012fa: 201e movs r0, #30
80012fc: f000 fa2b bl 8001756 <HAL_NVIC_EnableIRQ>
/* Enable TIM4 clock */
__HAL_RCC_TIM4_CLK_ENABLE();
8001300: 4b1f ldr r3, [pc, #124] ; (8001380 <HAL_InitTick+0xa0>)
8001302: 69db ldr r3, [r3, #28]
8001304: 4a1e ldr r2, [pc, #120] ; (8001380 <HAL_InitTick+0xa0>)
8001306: f043 0304 orr.w r3, r3, #4
800130a: 61d3 str r3, [r2, #28]
800130c: 4b1c ldr r3, [pc, #112] ; (8001380 <HAL_InitTick+0xa0>)
800130e: 69db ldr r3, [r3, #28]
8001310: f003 0304 and.w r3, r3, #4
8001314: 60fb str r3, [r7, #12]
8001316: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8001318: f107 0210 add.w r2, r7, #16
800131c: f107 0314 add.w r3, r7, #20
8001320: 4611 mov r1, r2
8001322: 4618 mov r0, r3
8001324: f002 fa3e bl 80037a4 <HAL_RCC_GetClockConfig>
/* Compute TIM4 clock */
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
8001328: f002 fa14 bl 8003754 <HAL_RCC_GetPCLK1Freq>
800132c: 4603 mov r3, r0
800132e: 005b lsls r3, r3, #1
8001330: 62fb str r3, [r7, #44] ; 0x2c
/* Compute the prescaler value to have TIM4 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
8001332: 6afb ldr r3, [r7, #44] ; 0x2c
8001334: 4a13 ldr r2, [pc, #76] ; (8001384 <HAL_InitTick+0xa4>)
8001336: fba2 2303 umull r2, r3, r2, r3
800133a: 0c9b lsrs r3, r3, #18
800133c: 3b01 subs r3, #1
800133e: 62bb str r3, [r7, #40] ; 0x28
/* Initialize TIM4 */
htim4.Instance = TIM4;
8001340: 4b11 ldr r3, [pc, #68] ; (8001388 <HAL_InitTick+0xa8>)
8001342: 4a12 ldr r2, [pc, #72] ; (800138c <HAL_InitTick+0xac>)
8001344: 601a str r2, [r3, #0]
+ Period = [(TIM4CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim4.Init.Period = (1000000 / 1000) - 1;
8001346: 4b10 ldr r3, [pc, #64] ; (8001388 <HAL_InitTick+0xa8>)
8001348: f240 32e7 movw r2, #999 ; 0x3e7
800134c: 60da str r2, [r3, #12]
htim4.Init.Prescaler = uwPrescalerValue;
800134e: 4a0e ldr r2, [pc, #56] ; (8001388 <HAL_InitTick+0xa8>)
8001350: 6abb ldr r3, [r7, #40] ; 0x28
8001352: 6053 str r3, [r2, #4]
htim4.Init.ClockDivision = 0;
8001354: 4b0c ldr r3, [pc, #48] ; (8001388 <HAL_InitTick+0xa8>)
8001356: 2200 movs r2, #0
8001358: 611a str r2, [r3, #16]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
800135a: 4b0b ldr r3, [pc, #44] ; (8001388 <HAL_InitTick+0xa8>)
800135c: 2200 movs r2, #0
800135e: 609a str r2, [r3, #8]
if(HAL_TIM_Base_Init(&htim4) == HAL_OK)
8001360: 4809 ldr r0, [pc, #36] ; (8001388 <HAL_InitTick+0xa8>)
8001362: f002 fdae bl 8003ec2 <HAL_TIM_Base_Init>
8001366: 4603 mov r3, r0
8001368: 2b00 cmp r3, #0
800136a: d104 bne.n 8001376 <HAL_InitTick+0x96>
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim4);
800136c: 4806 ldr r0, [pc, #24] ; (8001388 <HAL_InitTick+0xa8>)
800136e: f002 fddc bl 8003f2a <HAL_TIM_Base_Start_IT>
8001372: 4603 mov r3, r0
8001374: e000 b.n 8001378 <HAL_InitTick+0x98>
}
/* Return function status */
return HAL_ERROR;
8001376: 2301 movs r3, #1
}
8001378: 4618 mov r0, r3
800137a: 3730 adds r7, #48 ; 0x30
800137c: 46bd mov sp, r7
800137e: bd80 pop {r7, pc}
8001380: 40021000 .word 0x40021000
8001384: 431bde83 .word 0x431bde83
8001388: 20000d10 .word 0x20000d10
800138c: 40000800 .word 0x40000800
08001390 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001390: b480 push {r7}
8001392: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
8001394: bf00 nop
8001396: 46bd mov sp, r7
8001398: bc80 pop {r7}
800139a: 4770 bx lr
0800139c <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800139c: b480 push {r7}
800139e: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80013a0: e7fe b.n 80013a0 <HardFault_Handler+0x4>
080013a2 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80013a2: b480 push {r7}
80013a4: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80013a6: e7fe b.n 80013a6 <MemManage_Handler+0x4>
080013a8 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80013a8: b480 push {r7}
80013aa: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80013ac: e7fe b.n 80013ac <BusFault_Handler+0x4>
080013ae <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80013ae: b480 push {r7}
80013b0: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80013b2: e7fe b.n 80013b2 <UsageFault_Handler+0x4>
080013b4 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80013b4: b480 push {r7}
80013b6: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80013b8: bf00 nop
80013ba: 46bd mov sp, r7
80013bc: bc80 pop {r7}
80013be: 4770 bx lr
080013c0 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80013c0: b480 push {r7}
80013c2: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80013c4: bf00 nop
80013c6: 46bd mov sp, r7
80013c8: bc80 pop {r7}
80013ca: 4770 bx lr
080013cc <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80013cc: b480 push {r7}
80013ce: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80013d0: bf00 nop
80013d2: 46bd mov sp, r7
80013d4: bc80 pop {r7}
80013d6: 4770 bx lr
080013d8 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80013d8: b480 push {r7}
80013da: af00 add r7, sp, #0
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80013dc: bf00 nop
80013de: 46bd mov sp, r7
80013e0: bc80 pop {r7}
80013e2: 4770 bx lr
080013e4 <DMA1_Channel6_IRQHandler>:
/**
* @brief This function handles DMA1 channel6 global interrupt.
*/
void DMA1_Channel6_IRQHandler(void)
{
80013e4: b580 push {r7, lr}
80013e6: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel6_IRQn 0 */
/* USER CODE END DMA1_Channel6_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_rx);
80013e8: 4802 ldr r0, [pc, #8] ; (80013f4 <DMA1_Channel6_IRQHandler+0x10>)
80013ea: f000 fb2d bl 8001a48 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel6_IRQn 1 */
/* USER CODE END DMA1_Channel6_IRQn 1 */
}
80013ee: bf00 nop
80013f0: bd80 pop {r7, pc}
80013f2: bf00 nop
80013f4: 20000b9c .word 0x20000b9c
080013f8 <DMA1_Channel7_IRQHandler>:
/**
* @brief This function handles DMA1 channel7 global interrupt.
*/
void DMA1_Channel7_IRQHandler(void)
{
80013f8: b580 push {r7, lr}
80013fa: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel7_IRQn 0 */
/* USER CODE END DMA1_Channel7_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_tx);
80013fc: 4802 ldr r0, [pc, #8] ; (8001408 <DMA1_Channel7_IRQHandler+0x10>)
80013fe: f000 fb23 bl 8001a48 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel7_IRQn 1 */
/* USER CODE END DMA1_Channel7_IRQn 1 */
}
8001402: bf00 nop
8001404: bd80 pop {r7, pc}
8001406: bf00 nop
8001408: 20000c34 .word 0x20000c34
0800140c <USB_LP_CAN1_RX0_IRQHandler>:
/**
* @brief This function handles USB low priority or CAN RX0 interrupts.
*/
void USB_LP_CAN1_RX0_IRQHandler(void)
{
800140c: b580 push {r7, lr}
800140e: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_FS);
8001410: 4802 ldr r0, [pc, #8] ; (800141c <USB_LP_CAN1_RX0_IRQHandler+0x10>)
8001412: f000 ffee bl 80023f2 <HAL_PCD_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */
}
8001416: bf00 nop
8001418: bd80 pop {r7, pc}
800141a: bf00 nop
800141c: 200019e8 .word 0x200019e8
08001420 <TIM4_IRQHandler>:
/**
* @brief This function handles TIM4 global interrupt.
*/
void TIM4_IRQHandler(void)
{
8001420: b580 push {r7, lr}
8001422: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_IRQn 0 */
/* USER CODE END TIM4_IRQn 0 */
HAL_TIM_IRQHandler(&htim4);
8001424: 4802 ldr r0, [pc, #8] ; (8001430 <TIM4_IRQHandler+0x10>)
8001426: f002 fda3 bl 8003f70 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM4_IRQn 1 */
/* USER CODE END TIM4_IRQn 1 */
}
800142a: bf00 nop
800142c: bd80 pop {r7, pc}
800142e: bf00 nop
8001430: 20000d10 .word 0x20000d10
08001434 <USART2_IRQHandler>:
/**
* @brief This function handles USART2 global interrupt.
*/
void USART2_IRQHandler(void)
{
8001434: b580 push {r7, lr}
8001436: af00 add r7, sp, #0
/* USER CODE BEGIN USART2_IRQn 0 */
if(__HAL_UART_GET_FLAG(&huart2,UART_FLAG_IDLE))
8001438: 4b06 ldr r3, [pc, #24] ; (8001454 <USART2_IRQHandler+0x20>)
800143a: 681b ldr r3, [r3, #0]
800143c: 681b ldr r3, [r3, #0]
800143e: f003 0310 and.w r3, r3, #16
8001442: 2b10 cmp r3, #16
8001444: d101 bne.n 800144a <USART2_IRQHandler+0x16>
uart_finish_receive();//空闲中断
8001446: f7ff fc03 bl 8000c50 <uart_finish_receive>
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
800144a: 4802 ldr r0, [pc, #8] ; (8001454 <USART2_IRQHandler+0x20>)
800144c: f003 f8f2 bl 8004634 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
8001450: bf00 nop
8001452: bd80 pop {r7, pc}
8001454: 20000cd0 .word 0x20000cd0
08001458 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8001458: b480 push {r7}
800145a: af00 add r7, sp, #0
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= 0x00000001U;
800145c: 4b15 ldr r3, [pc, #84] ; (80014b4 <SystemInit+0x5c>)
800145e: 681b ldr r3, [r3, #0]
8001460: 4a14 ldr r2, [pc, #80] ; (80014b4 <SystemInit+0x5c>)
8001462: f043 0301 orr.w r3, r3, #1
8001466: 6013 str r3, [r2, #0]
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
RCC->CFGR &= 0xF8FF0000U;
8001468: 4b12 ldr r3, [pc, #72] ; (80014b4 <SystemInit+0x5c>)
800146a: 685a ldr r2, [r3, #4]
800146c: 4911 ldr r1, [pc, #68] ; (80014b4 <SystemInit+0x5c>)
800146e: 4b12 ldr r3, [pc, #72] ; (80014b8 <SystemInit+0x60>)
8001470: 4013 ands r3, r2
8001472: 604b str r3, [r1, #4]
#else
RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= 0xFEF6FFFFU;
8001474: 4b0f ldr r3, [pc, #60] ; (80014b4 <SystemInit+0x5c>)
8001476: 681b ldr r3, [r3, #0]
8001478: 4a0e ldr r2, [pc, #56] ; (80014b4 <SystemInit+0x5c>)
800147a: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000
800147e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001482: 6013 str r3, [r2, #0]
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
8001484: 4b0b ldr r3, [pc, #44] ; (80014b4 <SystemInit+0x5c>)
8001486: 681b ldr r3, [r3, #0]
8001488: 4a0a ldr r2, [pc, #40] ; (80014b4 <SystemInit+0x5c>)
800148a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800148e: 6013 str r3, [r2, #0]
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= 0xFF80FFFFU;
8001490: 4b08 ldr r3, [pc, #32] ; (80014b4 <SystemInit+0x5c>)
8001492: 685b ldr r3, [r3, #4]
8001494: 4a07 ldr r2, [pc, #28] ; (80014b4 <SystemInit+0x5c>)
8001496: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000
800149a: 6053 str r3, [r2, #4]
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000U;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000U;
800149c: 4b05 ldr r3, [pc, #20] ; (80014b4 <SystemInit+0x5c>)
800149e: f44f 021f mov.w r2, #10420224 ; 0x9f0000
80014a2: 609a str r2, [r3, #8]
#endif
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
80014a4: 4b05 ldr r3, [pc, #20] ; (80014bc <SystemInit+0x64>)
80014a6: f04f 6200 mov.w r2, #134217728 ; 0x8000000
80014aa: 609a str r2, [r3, #8]
#endif
}
80014ac: bf00 nop
80014ae: 46bd mov sp, r7
80014b0: bc80 pop {r7}
80014b2: 4770 bx lr
80014b4: 40021000 .word 0x40021000
80014b8: f8ff0000 .word 0xf8ff0000
80014bc: e000ed00 .word 0xe000ed00
080014c0 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
80014c0: 2100 movs r1, #0
b LoopCopyDataInit
80014c2: e003 b.n 80014cc <LoopCopyDataInit>
080014c4 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
80014c4: 4b0b ldr r3, [pc, #44] ; (80014f4 <LoopFillZerobss+0x14>)
ldr r3, [r3, r1]
80014c6: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
80014c8: 5043 str r3, [r0, r1]
adds r1, r1, #4
80014ca: 3104 adds r1, #4
080014cc <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
80014cc: 480a ldr r0, [pc, #40] ; (80014f8 <LoopFillZerobss+0x18>)
ldr r3, =_edata
80014ce: 4b0b ldr r3, [pc, #44] ; (80014fc <LoopFillZerobss+0x1c>)
adds r2, r0, r1
80014d0: 1842 adds r2, r0, r1
cmp r2, r3
80014d2: 429a cmp r2, r3
bcc CopyDataInit
80014d4: d3f6 bcc.n 80014c4 <CopyDataInit>
ldr r2, =_sbss
80014d6: 4a0a ldr r2, [pc, #40] ; (8001500 <LoopFillZerobss+0x20>)
b LoopFillZerobss
80014d8: e002 b.n 80014e0 <LoopFillZerobss>
080014da <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
80014da: 2300 movs r3, #0
str r3, [r2], #4
80014dc: f842 3b04 str.w r3, [r2], #4
080014e0 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
80014e0: 4b08 ldr r3, [pc, #32] ; (8001504 <LoopFillZerobss+0x24>)
cmp r2, r3
80014e2: 429a cmp r2, r3
bcc FillZerobss
80014e4: d3f9 bcc.n 80014da <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
80014e6: f7ff ffb7 bl 8001458 <SystemInit>
/* Call static constructors */
bl __libc_init_array
80014ea: f006 fdfd bl 80080e8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80014ee: f7ff fbff bl 8000cf0 <main>
bx lr
80014f2: 4770 bx lr
ldr r3, =_sidata
80014f4: 080081c4 .word 0x080081c4
ldr r0, =_sdata
80014f8: 20000000 .word 0x20000000
ldr r3, =_edata
80014fc: 20000188 .word 0x20000188
ldr r2, =_sbss
8001500: 20000188 .word 0x20000188
ldr r3, = _ebss
8001504: 20001c54 .word 0x20001c54
08001508 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001508: e7fe b.n 8001508 <ADC1_2_IRQHandler>
...
0800150c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800150c: b580 push {r7, lr}
800150e: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001510: 4b08 ldr r3, [pc, #32] ; (8001534 <HAL_Init+0x28>)
8001512: 681b ldr r3, [r3, #0]
8001514: 4a07 ldr r2, [pc, #28] ; (8001534 <HAL_Init+0x28>)
8001516: f043 0310 orr.w r3, r3, #16
800151a: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800151c: 2003 movs r0, #3
800151e: f000 f8f3 bl 8001708 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001522: 2000 movs r0, #0
8001524: f7ff fedc bl 80012e0 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001528: f7ff fd6c bl 8001004 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800152c: 2300 movs r3, #0
}
800152e: 4618 mov r0, r3
8001530: bd80 pop {r7, pc}
8001532: bf00 nop
8001534: 40022000 .word 0x40022000
08001538 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001538: b480 push {r7}
800153a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800153c: 4b05 ldr r3, [pc, #20] ; (8001554 <HAL_IncTick+0x1c>)
800153e: 781b ldrb r3, [r3, #0]
8001540: 461a mov r2, r3
8001542: 4b05 ldr r3, [pc, #20] ; (8001558 <HAL_IncTick+0x20>)
8001544: 681b ldr r3, [r3, #0]
8001546: 4413 add r3, r2
8001548: 4a03 ldr r2, [pc, #12] ; (8001558 <HAL_IncTick+0x20>)
800154a: 6013 str r3, [r2, #0]
}
800154c: bf00 nop
800154e: 46bd mov sp, r7
8001550: bc80 pop {r7}
8001552: 4770 bx lr
8001554: 20000014 .word 0x20000014
8001558: 20000d50 .word 0x20000d50
0800155c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800155c: b480 push {r7}
800155e: af00 add r7, sp, #0
return uwTick;
8001560: 4b02 ldr r3, [pc, #8] ; (800156c <HAL_GetTick+0x10>)
8001562: 681b ldr r3, [r3, #0]
}
8001564: 4618 mov r0, r3
8001566: 46bd mov sp, r7
8001568: bc80 pop {r7}
800156a: 4770 bx lr
800156c: 20000d50 .word 0x20000d50
08001570 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001570: b580 push {r7, lr}
8001572: b084 sub sp, #16
8001574: af00 add r7, sp, #0
8001576: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001578: f7ff fff0 bl 800155c <HAL_GetTick>
800157c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
800157e: 687b ldr r3, [r7, #4]
8001580: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8001582: 68fb ldr r3, [r7, #12]
8001584: f1b3 3fff cmp.w r3, #4294967295
8001588: d005 beq.n 8001596 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
800158a: 4b09 ldr r3, [pc, #36] ; (80015b0 <HAL_Delay+0x40>)
800158c: 781b ldrb r3, [r3, #0]
800158e: 461a mov r2, r3
8001590: 68fb ldr r3, [r7, #12]
8001592: 4413 add r3, r2
8001594: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8001596: bf00 nop
8001598: f7ff ffe0 bl 800155c <HAL_GetTick>
800159c: 4602 mov r2, r0
800159e: 68bb ldr r3, [r7, #8]
80015a0: 1ad3 subs r3, r2, r3
80015a2: 68fa ldr r2, [r7, #12]
80015a4: 429a cmp r2, r3
80015a6: d8f7 bhi.n 8001598 <HAL_Delay+0x28>
{
}
}
80015a8: bf00 nop
80015aa: 3710 adds r7, #16
80015ac: 46bd mov sp, r7
80015ae: bd80 pop {r7, pc}
80015b0: 20000014 .word 0x20000014
080015b4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80015b4: b480 push {r7}
80015b6: b085 sub sp, #20
80015b8: af00 add r7, sp, #0
80015ba: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80015bc: 687b ldr r3, [r7, #4]
80015be: f003 0307 and.w r3, r3, #7
80015c2: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80015c4: 4b0c ldr r3, [pc, #48] ; (80015f8 <__NVIC_SetPriorityGrouping+0x44>)
80015c6: 68db ldr r3, [r3, #12]
80015c8: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80015ca: 68ba ldr r2, [r7, #8]
80015cc: f64f 03ff movw r3, #63743 ; 0xf8ff
80015d0: 4013 ands r3, r2
80015d2: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80015d4: 68fb ldr r3, [r7, #12]
80015d6: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80015d8: 68bb ldr r3, [r7, #8]
80015da: 4313 orrs r3, r2
reg_value = (reg_value |
80015dc: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
80015e0: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80015e4: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80015e6: 4a04 ldr r2, [pc, #16] ; (80015f8 <__NVIC_SetPriorityGrouping+0x44>)
80015e8: 68bb ldr r3, [r7, #8]
80015ea: 60d3 str r3, [r2, #12]
}
80015ec: bf00 nop
80015ee: 3714 adds r7, #20
80015f0: 46bd mov sp, r7
80015f2: bc80 pop {r7}
80015f4: 4770 bx lr
80015f6: bf00 nop
80015f8: e000ed00 .word 0xe000ed00
080015fc <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80015fc: b480 push {r7}
80015fe: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001600: 4b04 ldr r3, [pc, #16] ; (8001614 <__NVIC_GetPriorityGrouping+0x18>)
8001602: 68db ldr r3, [r3, #12]
8001604: 0a1b lsrs r3, r3, #8
8001606: f003 0307 and.w r3, r3, #7
}
800160a: 4618 mov r0, r3
800160c: 46bd mov sp, r7
800160e: bc80 pop {r7}
8001610: 4770 bx lr
8001612: bf00 nop
8001614: e000ed00 .word 0xe000ed00
08001618 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001618: b480 push {r7}
800161a: b083 sub sp, #12
800161c: af00 add r7, sp, #0
800161e: 4603 mov r3, r0
8001620: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001622: f997 3007 ldrsb.w r3, [r7, #7]
8001626: 2b00 cmp r3, #0
8001628: db0b blt.n 8001642 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800162a: 79fb ldrb r3, [r7, #7]
800162c: f003 021f and.w r2, r3, #31
8001630: 4906 ldr r1, [pc, #24] ; (800164c <__NVIC_EnableIRQ+0x34>)
8001632: f997 3007 ldrsb.w r3, [r7, #7]
8001636: 095b lsrs r3, r3, #5
8001638: 2001 movs r0, #1
800163a: fa00 f202 lsl.w r2, r0, r2
800163e: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001642: bf00 nop
8001644: 370c adds r7, #12
8001646: 46bd mov sp, r7
8001648: bc80 pop {r7}
800164a: 4770 bx lr
800164c: e000e100 .word 0xe000e100
08001650 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001650: b480 push {r7}
8001652: b083 sub sp, #12
8001654: af00 add r7, sp, #0
8001656: 4603 mov r3, r0
8001658: 6039 str r1, [r7, #0]
800165a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800165c: f997 3007 ldrsb.w r3, [r7, #7]
8001660: 2b00 cmp r3, #0
8001662: db0a blt.n 800167a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001664: 683b ldr r3, [r7, #0]
8001666: b2da uxtb r2, r3
8001668: 490c ldr r1, [pc, #48] ; (800169c <__NVIC_SetPriority+0x4c>)
800166a: f997 3007 ldrsb.w r3, [r7, #7]
800166e: 0112 lsls r2, r2, #4
8001670: b2d2 uxtb r2, r2
8001672: 440b add r3, r1
8001674: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001678: e00a b.n 8001690 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800167a: 683b ldr r3, [r7, #0]
800167c: b2da uxtb r2, r3
800167e: 4908 ldr r1, [pc, #32] ; (80016a0 <__NVIC_SetPriority+0x50>)
8001680: 79fb ldrb r3, [r7, #7]
8001682: f003 030f and.w r3, r3, #15
8001686: 3b04 subs r3, #4
8001688: 0112 lsls r2, r2, #4
800168a: b2d2 uxtb r2, r2
800168c: 440b add r3, r1
800168e: 761a strb r2, [r3, #24]
}
8001690: bf00 nop
8001692: 370c adds r7, #12
8001694: 46bd mov sp, r7
8001696: bc80 pop {r7}
8001698: 4770 bx lr
800169a: bf00 nop
800169c: e000e100 .word 0xe000e100
80016a0: e000ed00 .word 0xe000ed00
080016a4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80016a4: b480 push {r7}
80016a6: b089 sub sp, #36 ; 0x24
80016a8: af00 add r7, sp, #0
80016aa: 60f8 str r0, [r7, #12]
80016ac: 60b9 str r1, [r7, #8]
80016ae: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80016b0: 68fb ldr r3, [r7, #12]
80016b2: f003 0307 and.w r3, r3, #7
80016b6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80016b8: 69fb ldr r3, [r7, #28]
80016ba: f1c3 0307 rsb r3, r3, #7
80016be: 2b04 cmp r3, #4
80016c0: bf28 it cs
80016c2: 2304 movcs r3, #4
80016c4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80016c6: 69fb ldr r3, [r7, #28]
80016c8: 3304 adds r3, #4
80016ca: 2b06 cmp r3, #6
80016cc: d902 bls.n 80016d4 <NVIC_EncodePriority+0x30>
80016ce: 69fb ldr r3, [r7, #28]
80016d0: 3b03 subs r3, #3
80016d2: e000 b.n 80016d6 <NVIC_EncodePriority+0x32>
80016d4: 2300 movs r3, #0
80016d6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80016d8: f04f 32ff mov.w r2, #4294967295
80016dc: 69bb ldr r3, [r7, #24]
80016de: fa02 f303 lsl.w r3, r2, r3
80016e2: 43da mvns r2, r3
80016e4: 68bb ldr r3, [r7, #8]
80016e6: 401a ands r2, r3
80016e8: 697b ldr r3, [r7, #20]
80016ea: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80016ec: f04f 31ff mov.w r1, #4294967295
80016f0: 697b ldr r3, [r7, #20]
80016f2: fa01 f303 lsl.w r3, r1, r3
80016f6: 43d9 mvns r1, r3
80016f8: 687b ldr r3, [r7, #4]
80016fa: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80016fc: 4313 orrs r3, r2
);
}
80016fe: 4618 mov r0, r3
8001700: 3724 adds r7, #36 ; 0x24
8001702: 46bd mov sp, r7
8001704: bc80 pop {r7}
8001706: 4770 bx lr
08001708 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001708: b580 push {r7, lr}
800170a: b082 sub sp, #8
800170c: af00 add r7, sp, #0
800170e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001710: 6878 ldr r0, [r7, #4]
8001712: f7ff ff4f bl 80015b4 <__NVIC_SetPriorityGrouping>
}
8001716: bf00 nop
8001718: 3708 adds r7, #8
800171a: 46bd mov sp, r7
800171c: bd80 pop {r7, pc}
0800171e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800171e: b580 push {r7, lr}
8001720: b086 sub sp, #24
8001722: af00 add r7, sp, #0
8001724: 4603 mov r3, r0
8001726: 60b9 str r1, [r7, #8]
8001728: 607a str r2, [r7, #4]
800172a: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
800172c: 2300 movs r3, #0
800172e: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001730: f7ff ff64 bl 80015fc <__NVIC_GetPriorityGrouping>
8001734: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001736: 687a ldr r2, [r7, #4]
8001738: 68b9 ldr r1, [r7, #8]
800173a: 6978 ldr r0, [r7, #20]
800173c: f7ff ffb2 bl 80016a4 <NVIC_EncodePriority>
8001740: 4602 mov r2, r0
8001742: f997 300f ldrsb.w r3, [r7, #15]
8001746: 4611 mov r1, r2
8001748: 4618 mov r0, r3
800174a: f7ff ff81 bl 8001650 <__NVIC_SetPriority>
}
800174e: bf00 nop
8001750: 3718 adds r7, #24
8001752: 46bd mov sp, r7
8001754: bd80 pop {r7, pc}
08001756 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001756: b580 push {r7, lr}
8001758: b082 sub sp, #8
800175a: af00 add r7, sp, #0
800175c: 4603 mov r3, r0
800175e: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001760: f997 3007 ldrsb.w r3, [r7, #7]
8001764: 4618 mov r0, r3
8001766: f7ff ff57 bl 8001618 <__NVIC_EnableIRQ>
}
800176a: bf00 nop
800176c: 3708 adds r7, #8
800176e: 46bd mov sp, r7
8001770: bd80 pop {r7, pc}
...
08001774 <HAL_DMA_Init>:
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8001774: b480 push {r7}
8001776: b085 sub sp, #20
8001778: af00 add r7, sp, #0
800177a: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
800177c: 2300 movs r3, #0
800177e: 60fb str r3, [r7, #12]
/* Check the DMA handle allocation */
if(hdma == NULL)
8001780: 687b ldr r3, [r7, #4]
8001782: 2b00 cmp r3, #0
8001784: d101 bne.n 800178a <HAL_DMA_Init+0x16>
{
return HAL_ERROR;
8001786: 2301 movs r3, #1
8001788: e043 b.n 8001812 <HAL_DMA_Init+0x9e>
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
hdma->DmaBaseAddress = DMA2;
}
#else
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
800178a: 687b ldr r3, [r7, #4]
800178c: 681b ldr r3, [r3, #0]
800178e: 461a mov r2, r3
8001790: 4b22 ldr r3, [pc, #136] ; (800181c <HAL_DMA_Init+0xa8>)
8001792: 4413 add r3, r2
8001794: 4a22 ldr r2, [pc, #136] ; (8001820 <HAL_DMA_Init+0xac>)
8001796: fba2 2303 umull r2, r3, r2, r3
800179a: 091b lsrs r3, r3, #4
800179c: 009a lsls r2, r3, #2
800179e: 687b ldr r3, [r7, #4]
80017a0: 641a str r2, [r3, #64] ; 0x40
hdma->DmaBaseAddress = DMA1;
80017a2: 687b ldr r3, [r7, #4]
80017a4: 4a1f ldr r2, [pc, #124] ; (8001824 <HAL_DMA_Init+0xb0>)
80017a6: 63da str r2, [r3, #60] ; 0x3c
#endif /* DMA2 */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
80017a8: 687b ldr r3, [r7, #4]
80017aa: 2202 movs r2, #2
80017ac: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Get the CR register value */
tmp = hdma->Instance->CCR;
80017b0: 687b ldr r3, [r7, #4]
80017b2: 681b ldr r3, [r3, #0]
80017b4: 681b ldr r3, [r3, #0]
80017b6: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
80017b8: 68fb ldr r3, [r7, #12]
80017ba: f423 537f bic.w r3, r3, #16320 ; 0x3fc0
80017be: f023 0330 bic.w r3, r3, #48 ; 0x30
80017c2: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
80017c4: 687b ldr r3, [r7, #4]
80017c6: 685a ldr r2, [r3, #4]
hdma->Init.PeriphInc | hdma->Init.MemInc |
80017c8: 687b ldr r3, [r7, #4]
80017ca: 689b ldr r3, [r3, #8]
tmp |= hdma->Init.Direction |
80017cc: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
80017ce: 687b ldr r3, [r7, #4]
80017d0: 68db ldr r3, [r3, #12]
80017d2: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80017d4: 687b ldr r3, [r7, #4]
80017d6: 691b ldr r3, [r3, #16]
hdma->Init.PeriphInc | hdma->Init.MemInc |
80017d8: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80017da: 687b ldr r3, [r7, #4]
80017dc: 695b ldr r3, [r3, #20]
80017de: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
80017e0: 687b ldr r3, [r7, #4]
80017e2: 699b ldr r3, [r3, #24]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80017e4: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
80017e6: 687b ldr r3, [r7, #4]
80017e8: 69db ldr r3, [r3, #28]
80017ea: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
80017ec: 68fa ldr r2, [r7, #12]
80017ee: 4313 orrs r3, r2
80017f0: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
80017f2: 687b ldr r3, [r7, #4]
80017f4: 681b ldr r3, [r3, #0]
80017f6: 68fa ldr r2, [r7, #12]
80017f8: 601a str r2, [r3, #0]
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80017fa: 687b ldr r3, [r7, #4]
80017fc: 2200 movs r2, #0
80017fe: 639a str r2, [r3, #56] ; 0x38
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8001800: 687b ldr r3, [r7, #4]
8001802: 2201 movs r2, #1
8001804: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
8001808: 687b ldr r3, [r7, #4]
800180a: 2200 movs r2, #0
800180c: f883 2020 strb.w r2, [r3, #32]
return HAL_OK;
8001810: 2300 movs r3, #0
}
8001812: 4618 mov r0, r3
8001814: 3714 adds r7, #20
8001816: 46bd mov sp, r7
8001818: bc80 pop {r7}
800181a: 4770 bx lr
800181c: bffdfff8 .word 0xbffdfff8
8001820: cccccccd .word 0xcccccccd
8001824: 40020000 .word 0x40020000
08001828 <HAL_DMA_Start_IT>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8001828: b580 push {r7, lr}
800182a: b086 sub sp, #24
800182c: af00 add r7, sp, #0
800182e: 60f8 str r0, [r7, #12]
8001830: 60b9 str r1, [r7, #8]
8001832: 607a str r2, [r7, #4]
8001834: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8001836: 2300 movs r3, #0
8001838: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
800183a: 68fb ldr r3, [r7, #12]
800183c: f893 3020 ldrb.w r3, [r3, #32]
8001840: 2b01 cmp r3, #1
8001842: d101 bne.n 8001848 <HAL_DMA_Start_IT+0x20>
8001844: 2302 movs r3, #2
8001846: e04a b.n 80018de <HAL_DMA_Start_IT+0xb6>
8001848: 68fb ldr r3, [r7, #12]
800184a: 2201 movs r2, #1
800184c: f883 2020 strb.w r2, [r3, #32]
if(HAL_DMA_STATE_READY == hdma->State)
8001850: 68fb ldr r3, [r7, #12]
8001852: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
8001856: 2b01 cmp r3, #1
8001858: d13a bne.n 80018d0 <HAL_DMA_Start_IT+0xa8>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
800185a: 68fb ldr r3, [r7, #12]
800185c: 2202 movs r2, #2
800185e: f883 2021 strb.w r2, [r3, #33] ; 0x21
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8001862: 68fb ldr r3, [r7, #12]
8001864: 2200 movs r2, #0
8001866: 639a str r2, [r3, #56] ; 0x38
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8001868: 68fb ldr r3, [r7, #12]
800186a: 681b ldr r3, [r3, #0]
800186c: 681a ldr r2, [r3, #0]
800186e: 68fb ldr r3, [r7, #12]
8001870: 681b ldr r3, [r3, #0]
8001872: f022 0201 bic.w r2, r2, #1
8001876: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8001878: 683b ldr r3, [r7, #0]
800187a: 687a ldr r2, [r7, #4]
800187c: 68b9 ldr r1, [r7, #8]
800187e: 68f8 ldr r0, [r7, #12]
8001880: f000 f9e8 bl 8001c54 <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback)
8001884: 68fb ldr r3, [r7, #12]
8001886: 6adb ldr r3, [r3, #44] ; 0x2c
8001888: 2b00 cmp r3, #0
800188a: d008 beq.n 800189e <HAL_DMA_Start_IT+0x76>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800188c: 68fb ldr r3, [r7, #12]
800188e: 681b ldr r3, [r3, #0]
8001890: 681a ldr r2, [r3, #0]
8001892: 68fb ldr r3, [r7, #12]
8001894: 681b ldr r3, [r3, #0]
8001896: f042 020e orr.w r2, r2, #14
800189a: 601a str r2, [r3, #0]
800189c: e00f b.n 80018be <HAL_DMA_Start_IT+0x96>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
800189e: 68fb ldr r3, [r7, #12]
80018a0: 681b ldr r3, [r3, #0]
80018a2: 681a ldr r2, [r3, #0]
80018a4: 68fb ldr r3, [r7, #12]
80018a6: 681b ldr r3, [r3, #0]
80018a8: f022 0204 bic.w r2, r2, #4
80018ac: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
80018ae: 68fb ldr r3, [r7, #12]
80018b0: 681b ldr r3, [r3, #0]
80018b2: 681a ldr r2, [r3, #0]
80018b4: 68fb ldr r3, [r7, #12]
80018b6: 681b ldr r3, [r3, #0]
80018b8: f042 020a orr.w r2, r2, #10
80018bc: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
80018be: 68fb ldr r3, [r7, #12]
80018c0: 681b ldr r3, [r3, #0]
80018c2: 681a ldr r2, [r3, #0]
80018c4: 68fb ldr r3, [r7, #12]
80018c6: 681b ldr r3, [r3, #0]
80018c8: f042 0201 orr.w r2, r2, #1
80018cc: 601a str r2, [r3, #0]
80018ce: e005 b.n 80018dc <HAL_DMA_Start_IT+0xb4>
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80018d0: 68fb ldr r3, [r7, #12]
80018d2: 2200 movs r2, #0
80018d4: f883 2020 strb.w r2, [r3, #32]
/* Remain BUSY */
status = HAL_BUSY;
80018d8: 2302 movs r3, #2
80018da: 75fb strb r3, [r7, #23]
}
return status;
80018dc: 7dfb ldrb r3, [r7, #23]
}
80018de: 4618 mov r0, r3
80018e0: 3718 adds r7, #24
80018e2: 46bd mov sp, r7
80018e4: bd80 pop {r7, pc}
080018e6 <HAL_DMA_Abort>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
80018e6: b480 push {r7}
80018e8: b085 sub sp, #20
80018ea: af00 add r7, sp, #0
80018ec: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80018ee: 2300 movs r3, #0
80018f0: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
80018f2: 687b ldr r3, [r7, #4]
80018f4: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
80018f8: 2b02 cmp r3, #2
80018fa: d008 beq.n 800190e <HAL_DMA_Abort+0x28>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
80018fc: 687b ldr r3, [r7, #4]
80018fe: 2204 movs r2, #4
8001900: 639a str r2, [r3, #56] ; 0x38
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001902: 687b ldr r3, [r7, #4]
8001904: 2200 movs r2, #0
8001906: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
800190a: 2301 movs r3, #1
800190c: e020 b.n 8001950 <HAL_DMA_Abort+0x6a>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800190e: 687b ldr r3, [r7, #4]
8001910: 681b ldr r3, [r3, #0]
8001912: 681a ldr r2, [r3, #0]
8001914: 687b ldr r3, [r7, #4]
8001916: 681b ldr r3, [r3, #0]
8001918: f022 020e bic.w r2, r2, #14
800191c: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
800191e: 687b ldr r3, [r7, #4]
8001920: 681b ldr r3, [r3, #0]
8001922: 681a ldr r2, [r3, #0]
8001924: 687b ldr r3, [r7, #4]
8001926: 681b ldr r3, [r3, #0]
8001928: f022 0201 bic.w r2, r2, #1
800192c: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
800192e: 687b ldr r3, [r7, #4]
8001930: 6c1a ldr r2, [r3, #64] ; 0x40
8001932: 687b ldr r3, [r7, #4]
8001934: 6bdb ldr r3, [r3, #60] ; 0x3c
8001936: 2101 movs r1, #1
8001938: fa01 f202 lsl.w r2, r1, r2
800193c: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800193e: 687b ldr r3, [r7, #4]
8001940: 2201 movs r2, #1
8001942: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001946: 687b ldr r3, [r7, #4]
8001948: 2200 movs r2, #0
800194a: f883 2020 strb.w r2, [r3, #32]
return status;
800194e: 7bfb ldrb r3, [r7, #15]
}
8001950: 4618 mov r0, r3
8001952: 3714 adds r7, #20
8001954: 46bd mov sp, r7
8001956: bc80 pop {r7}
8001958: 4770 bx lr
...
0800195c <HAL_DMA_Abort_IT>:
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
800195c: b580 push {r7, lr}
800195e: b084 sub sp, #16
8001960: af00 add r7, sp, #0
8001962: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001964: 2300 movs r3, #0
8001966: 73fb strb r3, [r7, #15]
if(HAL_DMA_STATE_BUSY != hdma->State)
8001968: 687b ldr r3, [r7, #4]
800196a: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
800196e: 2b02 cmp r3, #2
8001970: d005 beq.n 800197e <HAL_DMA_Abort_IT+0x22>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001972: 687b ldr r3, [r7, #4]
8001974: 2204 movs r2, #4
8001976: 639a str r2, [r3, #56] ; 0x38
status = HAL_ERROR;
8001978: 2301 movs r3, #1
800197a: 73fb strb r3, [r7, #15]
800197c: e051 b.n 8001a22 <HAL_DMA_Abort_IT+0xc6>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800197e: 687b ldr r3, [r7, #4]
8001980: 681b ldr r3, [r3, #0]
8001982: 681a ldr r2, [r3, #0]
8001984: 687b ldr r3, [r7, #4]
8001986: 681b ldr r3, [r3, #0]
8001988: f022 020e bic.w r2, r2, #14
800198c: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
800198e: 687b ldr r3, [r7, #4]
8001990: 681b ldr r3, [r3, #0]
8001992: 681a ldr r2, [r3, #0]
8001994: 687b ldr r3, [r7, #4]
8001996: 681b ldr r3, [r3, #0]
8001998: f022 0201 bic.w r2, r2, #1
800199c: 601a str r2, [r3, #0]
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
800199e: 687b ldr r3, [r7, #4]
80019a0: 681b ldr r3, [r3, #0]
80019a2: 4a22 ldr r2, [pc, #136] ; (8001a2c <HAL_DMA_Abort_IT+0xd0>)
80019a4: 4293 cmp r3, r2
80019a6: d029 beq.n 80019fc <HAL_DMA_Abort_IT+0xa0>
80019a8: 687b ldr r3, [r7, #4]
80019aa: 681b ldr r3, [r3, #0]
80019ac: 4a20 ldr r2, [pc, #128] ; (8001a30 <HAL_DMA_Abort_IT+0xd4>)
80019ae: 4293 cmp r3, r2
80019b0: d022 beq.n 80019f8 <HAL_DMA_Abort_IT+0x9c>
80019b2: 687b ldr r3, [r7, #4]
80019b4: 681b ldr r3, [r3, #0]
80019b6: 4a1f ldr r2, [pc, #124] ; (8001a34 <HAL_DMA_Abort_IT+0xd8>)
80019b8: 4293 cmp r3, r2
80019ba: d01a beq.n 80019f2 <HAL_DMA_Abort_IT+0x96>
80019bc: 687b ldr r3, [r7, #4]
80019be: 681b ldr r3, [r3, #0]
80019c0: 4a1d ldr r2, [pc, #116] ; (8001a38 <HAL_DMA_Abort_IT+0xdc>)
80019c2: 4293 cmp r3, r2
80019c4: d012 beq.n 80019ec <HAL_DMA_Abort_IT+0x90>
80019c6: 687b ldr r3, [r7, #4]
80019c8: 681b ldr r3, [r3, #0]
80019ca: 4a1c ldr r2, [pc, #112] ; (8001a3c <HAL_DMA_Abort_IT+0xe0>)
80019cc: 4293 cmp r3, r2
80019ce: d00a beq.n 80019e6 <HAL_DMA_Abort_IT+0x8a>
80019d0: 687b ldr r3, [r7, #4]
80019d2: 681b ldr r3, [r3, #0]
80019d4: 4a1a ldr r2, [pc, #104] ; (8001a40 <HAL_DMA_Abort_IT+0xe4>)
80019d6: 4293 cmp r3, r2
80019d8: d102 bne.n 80019e0 <HAL_DMA_Abort_IT+0x84>
80019da: f44f 1380 mov.w r3, #1048576 ; 0x100000
80019de: e00e b.n 80019fe <HAL_DMA_Abort_IT+0xa2>
80019e0: f04f 7380 mov.w r3, #16777216 ; 0x1000000
80019e4: e00b b.n 80019fe <HAL_DMA_Abort_IT+0xa2>
80019e6: f44f 3380 mov.w r3, #65536 ; 0x10000
80019ea: e008 b.n 80019fe <HAL_DMA_Abort_IT+0xa2>
80019ec: f44f 5380 mov.w r3, #4096 ; 0x1000
80019f0: e005 b.n 80019fe <HAL_DMA_Abort_IT+0xa2>
80019f2: f44f 7380 mov.w r3, #256 ; 0x100
80019f6: e002 b.n 80019fe <HAL_DMA_Abort_IT+0xa2>
80019f8: 2310 movs r3, #16
80019fa: e000 b.n 80019fe <HAL_DMA_Abort_IT+0xa2>
80019fc: 2301 movs r3, #1
80019fe: 4a11 ldr r2, [pc, #68] ; (8001a44 <HAL_DMA_Abort_IT+0xe8>)
8001a00: 6053 str r3, [r2, #4]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001a02: 687b ldr r3, [r7, #4]
8001a04: 2201 movs r2, #1
8001a06: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001a0a: 687b ldr r3, [r7, #4]
8001a0c: 2200 movs r2, #0
8001a0e: f883 2020 strb.w r2, [r3, #32]
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
8001a12: 687b ldr r3, [r7, #4]
8001a14: 6b5b ldr r3, [r3, #52] ; 0x34
8001a16: 2b00 cmp r3, #0
8001a18: d003 beq.n 8001a22 <HAL_DMA_Abort_IT+0xc6>
{
hdma->XferAbortCallback(hdma);
8001a1a: 687b ldr r3, [r7, #4]
8001a1c: 6b5b ldr r3, [r3, #52] ; 0x34
8001a1e: 6878 ldr r0, [r7, #4]
8001a20: 4798 blx r3
}
}
return status;
8001a22: 7bfb ldrb r3, [r7, #15]
}
8001a24: 4618 mov r0, r3
8001a26: 3710 adds r7, #16
8001a28: 46bd mov sp, r7
8001a2a: bd80 pop {r7, pc}
8001a2c: 40020008 .word 0x40020008
8001a30: 4002001c .word 0x4002001c
8001a34: 40020030 .word 0x40020030
8001a38: 40020044 .word 0x40020044
8001a3c: 40020058 .word 0x40020058
8001a40: 4002006c .word 0x4002006c
8001a44: 40020000 .word 0x40020000
08001a48 <HAL_DMA_IRQHandler>:
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
8001a48: b580 push {r7, lr}
8001a4a: b084 sub sp, #16
8001a4c: af00 add r7, sp, #0
8001a4e: 6078 str r0, [r7, #4]
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
8001a50: 687b ldr r3, [r7, #4]
8001a52: 6bdb ldr r3, [r3, #60] ; 0x3c
8001a54: 681b ldr r3, [r3, #0]
8001a56: 60fb str r3, [r7, #12]
uint32_t source_it = hdma->Instance->CCR;
8001a58: 687b ldr r3, [r7, #4]
8001a5a: 681b ldr r3, [r3, #0]
8001a5c: 681b ldr r3, [r3, #0]
8001a5e: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
8001a60: 687b ldr r3, [r7, #4]
8001a62: 6c1b ldr r3, [r3, #64] ; 0x40
8001a64: 2204 movs r2, #4
8001a66: 409a lsls r2, r3
8001a68: 68fb ldr r3, [r7, #12]
8001a6a: 4013 ands r3, r2
8001a6c: 2b00 cmp r3, #0
8001a6e: d04f beq.n 8001b10 <HAL_DMA_IRQHandler+0xc8>
8001a70: 68bb ldr r3, [r7, #8]
8001a72: f003 0304 and.w r3, r3, #4
8001a76: 2b00 cmp r3, #0
8001a78: d04a beq.n 8001b10 <HAL_DMA_IRQHandler+0xc8>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8001a7a: 687b ldr r3, [r7, #4]
8001a7c: 681b ldr r3, [r3, #0]
8001a7e: 681b ldr r3, [r3, #0]
8001a80: f003 0320 and.w r3, r3, #32
8001a84: 2b00 cmp r3, #0
8001a86: d107 bne.n 8001a98 <HAL_DMA_IRQHandler+0x50>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8001a88: 687b ldr r3, [r7, #4]
8001a8a: 681b ldr r3, [r3, #0]
8001a8c: 681a ldr r2, [r3, #0]
8001a8e: 687b ldr r3, [r7, #4]
8001a90: 681b ldr r3, [r3, #0]
8001a92: f022 0204 bic.w r2, r2, #4
8001a96: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
8001a98: 687b ldr r3, [r7, #4]
8001a9a: 681b ldr r3, [r3, #0]
8001a9c: 4a66 ldr r2, [pc, #408] ; (8001c38 <HAL_DMA_IRQHandler+0x1f0>)
8001a9e: 4293 cmp r3, r2
8001aa0: d029 beq.n 8001af6 <HAL_DMA_IRQHandler+0xae>
8001aa2: 687b ldr r3, [r7, #4]
8001aa4: 681b ldr r3, [r3, #0]
8001aa6: 4a65 ldr r2, [pc, #404] ; (8001c3c <HAL_DMA_IRQHandler+0x1f4>)
8001aa8: 4293 cmp r3, r2
8001aaa: d022 beq.n 8001af2 <HAL_DMA_IRQHandler+0xaa>
8001aac: 687b ldr r3, [r7, #4]
8001aae: 681b ldr r3, [r3, #0]
8001ab0: 4a63 ldr r2, [pc, #396] ; (8001c40 <HAL_DMA_IRQHandler+0x1f8>)
8001ab2: 4293 cmp r3, r2
8001ab4: d01a beq.n 8001aec <HAL_DMA_IRQHandler+0xa4>
8001ab6: 687b ldr r3, [r7, #4]
8001ab8: 681b ldr r3, [r3, #0]
8001aba: 4a62 ldr r2, [pc, #392] ; (8001c44 <HAL_DMA_IRQHandler+0x1fc>)
8001abc: 4293 cmp r3, r2
8001abe: d012 beq.n 8001ae6 <HAL_DMA_IRQHandler+0x9e>
8001ac0: 687b ldr r3, [r7, #4]
8001ac2: 681b ldr r3, [r3, #0]
8001ac4: 4a60 ldr r2, [pc, #384] ; (8001c48 <HAL_DMA_IRQHandler+0x200>)
8001ac6: 4293 cmp r3, r2
8001ac8: d00a beq.n 8001ae0 <HAL_DMA_IRQHandler+0x98>
8001aca: 687b ldr r3, [r7, #4]
8001acc: 681b ldr r3, [r3, #0]
8001ace: 4a5f ldr r2, [pc, #380] ; (8001c4c <HAL_DMA_IRQHandler+0x204>)
8001ad0: 4293 cmp r3, r2
8001ad2: d102 bne.n 8001ada <HAL_DMA_IRQHandler+0x92>
8001ad4: f44f 0380 mov.w r3, #4194304 ; 0x400000
8001ad8: e00e b.n 8001af8 <HAL_DMA_IRQHandler+0xb0>
8001ada: f04f 6380 mov.w r3, #67108864 ; 0x4000000
8001ade: e00b b.n 8001af8 <HAL_DMA_IRQHandler+0xb0>
8001ae0: f44f 2380 mov.w r3, #262144 ; 0x40000
8001ae4: e008 b.n 8001af8 <HAL_DMA_IRQHandler+0xb0>
8001ae6: f44f 4380 mov.w r3, #16384 ; 0x4000
8001aea: e005 b.n 8001af8 <HAL_DMA_IRQHandler+0xb0>
8001aec: f44f 6380 mov.w r3, #1024 ; 0x400
8001af0: e002 b.n 8001af8 <HAL_DMA_IRQHandler+0xb0>
8001af2: 2340 movs r3, #64 ; 0x40
8001af4: e000 b.n 8001af8 <HAL_DMA_IRQHandler+0xb0>
8001af6: 2304 movs r3, #4
8001af8: 4a55 ldr r2, [pc, #340] ; (8001c50 <HAL_DMA_IRQHandler+0x208>)
8001afa: 6053 str r3, [r2, #4]
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
8001afc: 687b ldr r3, [r7, #4]
8001afe: 6adb ldr r3, [r3, #44] ; 0x2c
8001b00: 2b00 cmp r3, #0
8001b02: f000 8094 beq.w 8001c2e <HAL_DMA_IRQHandler+0x1e6>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
8001b06: 687b ldr r3, [r7, #4]
8001b08: 6adb ldr r3, [r3, #44] ; 0x2c
8001b0a: 6878 ldr r0, [r7, #4]
8001b0c: 4798 blx r3
if(hdma->XferHalfCpltCallback != NULL)
8001b0e: e08e b.n 8001c2e <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
8001b10: 687b ldr r3, [r7, #4]
8001b12: 6c1b ldr r3, [r3, #64] ; 0x40
8001b14: 2202 movs r2, #2
8001b16: 409a lsls r2, r3
8001b18: 68fb ldr r3, [r7, #12]
8001b1a: 4013 ands r3, r2
8001b1c: 2b00 cmp r3, #0
8001b1e: d056 beq.n 8001bce <HAL_DMA_IRQHandler+0x186>
8001b20: 68bb ldr r3, [r7, #8]
8001b22: f003 0302 and.w r3, r3, #2
8001b26: 2b00 cmp r3, #0
8001b28: d051 beq.n 8001bce <HAL_DMA_IRQHandler+0x186>
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8001b2a: 687b ldr r3, [r7, #4]
8001b2c: 681b ldr r3, [r3, #0]
8001b2e: 681b ldr r3, [r3, #0]
8001b30: f003 0320 and.w r3, r3, #32
8001b34: 2b00 cmp r3, #0
8001b36: d10b bne.n 8001b50 <HAL_DMA_IRQHandler+0x108>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 681b ldr r3, [r3, #0]
8001b3c: 681a ldr r2, [r3, #0]
8001b3e: 687b ldr r3, [r7, #4]
8001b40: 681b ldr r3, [r3, #0]
8001b42: f022 020a bic.w r2, r2, #10
8001b46: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001b48: 687b ldr r3, [r7, #4]
8001b4a: 2201 movs r2, #1
8001b4c: f883 2021 strb.w r2, [r3, #33] ; 0x21
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
8001b50: 687b ldr r3, [r7, #4]
8001b52: 681b ldr r3, [r3, #0]
8001b54: 4a38 ldr r2, [pc, #224] ; (8001c38 <HAL_DMA_IRQHandler+0x1f0>)
8001b56: 4293 cmp r3, r2
8001b58: d029 beq.n 8001bae <HAL_DMA_IRQHandler+0x166>
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 681b ldr r3, [r3, #0]
8001b5e: 4a37 ldr r2, [pc, #220] ; (8001c3c <HAL_DMA_IRQHandler+0x1f4>)
8001b60: 4293 cmp r3, r2
8001b62: d022 beq.n 8001baa <HAL_DMA_IRQHandler+0x162>
8001b64: 687b ldr r3, [r7, #4]
8001b66: 681b ldr r3, [r3, #0]
8001b68: 4a35 ldr r2, [pc, #212] ; (8001c40 <HAL_DMA_IRQHandler+0x1f8>)
8001b6a: 4293 cmp r3, r2
8001b6c: d01a beq.n 8001ba4 <HAL_DMA_IRQHandler+0x15c>
8001b6e: 687b ldr r3, [r7, #4]
8001b70: 681b ldr r3, [r3, #0]
8001b72: 4a34 ldr r2, [pc, #208] ; (8001c44 <HAL_DMA_IRQHandler+0x1fc>)
8001b74: 4293 cmp r3, r2
8001b76: d012 beq.n 8001b9e <HAL_DMA_IRQHandler+0x156>
8001b78: 687b ldr r3, [r7, #4]
8001b7a: 681b ldr r3, [r3, #0]
8001b7c: 4a32 ldr r2, [pc, #200] ; (8001c48 <HAL_DMA_IRQHandler+0x200>)
8001b7e: 4293 cmp r3, r2
8001b80: d00a beq.n 8001b98 <HAL_DMA_IRQHandler+0x150>
8001b82: 687b ldr r3, [r7, #4]
8001b84: 681b ldr r3, [r3, #0]
8001b86: 4a31 ldr r2, [pc, #196] ; (8001c4c <HAL_DMA_IRQHandler+0x204>)
8001b88: 4293 cmp r3, r2
8001b8a: d102 bne.n 8001b92 <HAL_DMA_IRQHandler+0x14a>
8001b8c: f44f 1300 mov.w r3, #2097152 ; 0x200000
8001b90: e00e b.n 8001bb0 <HAL_DMA_IRQHandler+0x168>
8001b92: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8001b96: e00b b.n 8001bb0 <HAL_DMA_IRQHandler+0x168>
8001b98: f44f 3300 mov.w r3, #131072 ; 0x20000
8001b9c: e008 b.n 8001bb0 <HAL_DMA_IRQHandler+0x168>
8001b9e: f44f 5300 mov.w r3, #8192 ; 0x2000
8001ba2: e005 b.n 8001bb0 <HAL_DMA_IRQHandler+0x168>
8001ba4: f44f 7300 mov.w r3, #512 ; 0x200
8001ba8: e002 b.n 8001bb0 <HAL_DMA_IRQHandler+0x168>
8001baa: 2320 movs r3, #32
8001bac: e000 b.n 8001bb0 <HAL_DMA_IRQHandler+0x168>
8001bae: 2302 movs r3, #2
8001bb0: 4a27 ldr r2, [pc, #156] ; (8001c50 <HAL_DMA_IRQHandler+0x208>)
8001bb2: 6053 str r3, [r2, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001bb4: 687b ldr r3, [r7, #4]
8001bb6: 2200 movs r2, #0
8001bb8: f883 2020 strb.w r2, [r3, #32]
if(hdma->XferCpltCallback != NULL)
8001bbc: 687b ldr r3, [r7, #4]
8001bbe: 6a9b ldr r3, [r3, #40] ; 0x28
8001bc0: 2b00 cmp r3, #0
8001bc2: d034 beq.n 8001c2e <HAL_DMA_IRQHandler+0x1e6>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
8001bc4: 687b ldr r3, [r7, #4]
8001bc6: 6a9b ldr r3, [r3, #40] ; 0x28
8001bc8: 6878 ldr r0, [r7, #4]
8001bca: 4798 blx r3
if(hdma->XferCpltCallback != NULL)
8001bcc: e02f b.n 8001c2e <HAL_DMA_IRQHandler+0x1e6>
}
}
/* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
8001bce: 687b ldr r3, [r7, #4]
8001bd0: 6c1b ldr r3, [r3, #64] ; 0x40
8001bd2: 2208 movs r2, #8
8001bd4: 409a lsls r2, r3
8001bd6: 68fb ldr r3, [r7, #12]
8001bd8: 4013 ands r3, r2
8001bda: 2b00 cmp r3, #0
8001bdc: d028 beq.n 8001c30 <HAL_DMA_IRQHandler+0x1e8>
8001bde: 68bb ldr r3, [r7, #8]
8001be0: f003 0308 and.w r3, r3, #8
8001be4: 2b00 cmp r3, #0
8001be6: d023 beq.n 8001c30 <HAL_DMA_IRQHandler+0x1e8>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8001be8: 687b ldr r3, [r7, #4]
8001bea: 681b ldr r3, [r3, #0]
8001bec: 681a ldr r2, [r3, #0]
8001bee: 687b ldr r3, [r7, #4]
8001bf0: 681b ldr r3, [r3, #0]
8001bf2: f022 020e bic.w r2, r2, #14
8001bf6: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8001bf8: 687b ldr r3, [r7, #4]
8001bfa: 6c1a ldr r2, [r3, #64] ; 0x40
8001bfc: 687b ldr r3, [r7, #4]
8001bfe: 6bdb ldr r3, [r3, #60] ; 0x3c
8001c00: 2101 movs r1, #1
8001c02: fa01 f202 lsl.w r2, r1, r2
8001c06: 605a str r2, [r3, #4]
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
8001c08: 687b ldr r3, [r7, #4]
8001c0a: 2201 movs r2, #1
8001c0c: 639a str r2, [r3, #56] ; 0x38
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001c0e: 687b ldr r3, [r7, #4]
8001c10: 2201 movs r2, #1
8001c12: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8001c16: 687b ldr r3, [r7, #4]
8001c18: 2200 movs r2, #0
8001c1a: f883 2020 strb.w r2, [r3, #32]
if (hdma->XferErrorCallback != NULL)
8001c1e: 687b ldr r3, [r7, #4]
8001c20: 6b1b ldr r3, [r3, #48] ; 0x30
8001c22: 2b00 cmp r3, #0
8001c24: d004 beq.n 8001c30 <HAL_DMA_IRQHandler+0x1e8>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
8001c26: 687b ldr r3, [r7, #4]
8001c28: 6b1b ldr r3, [r3, #48] ; 0x30
8001c2a: 6878 ldr r0, [r7, #4]
8001c2c: 4798 blx r3
}
}
return;
8001c2e: bf00 nop
8001c30: bf00 nop
}
8001c32: 3710 adds r7, #16
8001c34: 46bd mov sp, r7
8001c36: bd80 pop {r7, pc}
8001c38: 40020008 .word 0x40020008
8001c3c: 4002001c .word 0x4002001c
8001c40: 40020030 .word 0x40020030
8001c44: 40020044 .word 0x40020044
8001c48: 40020058 .word 0x40020058
8001c4c: 4002006c .word 0x4002006c
8001c50: 40020000 .word 0x40020000
08001c54 <DMA_SetConfig>:
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8001c54: b480 push {r7}
8001c56: b085 sub sp, #20
8001c58: af00 add r7, sp, #0
8001c5a: 60f8 str r0, [r7, #12]
8001c5c: 60b9 str r1, [r7, #8]
8001c5e: 607a str r2, [r7, #4]
8001c60: 603b str r3, [r7, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
8001c62: 68fb ldr r3, [r7, #12]
8001c64: 6c1a ldr r2, [r3, #64] ; 0x40
8001c66: 68fb ldr r3, [r7, #12]
8001c68: 6bdb ldr r3, [r3, #60] ; 0x3c
8001c6a: 2101 movs r1, #1
8001c6c: fa01 f202 lsl.w r2, r1, r2
8001c70: 605a str r2, [r3, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8001c72: 68fb ldr r3, [r7, #12]
8001c74: 681b ldr r3, [r3, #0]
8001c76: 683a ldr r2, [r7, #0]
8001c78: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8001c7a: 68fb ldr r3, [r7, #12]
8001c7c: 685b ldr r3, [r3, #4]
8001c7e: 2b10 cmp r3, #16
8001c80: d108 bne.n 8001c94 <DMA_SetConfig+0x40>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8001c82: 68fb ldr r3, [r7, #12]
8001c84: 681b ldr r3, [r3, #0]
8001c86: 687a ldr r2, [r7, #4]
8001c88: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8001c8a: 68fb ldr r3, [r7, #12]
8001c8c: 681b ldr r3, [r3, #0]
8001c8e: 68ba ldr r2, [r7, #8]
8001c90: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8001c92: e007 b.n 8001ca4 <DMA_SetConfig+0x50>
hdma->Instance->CPAR = SrcAddress;
8001c94: 68fb ldr r3, [r7, #12]
8001c96: 681b ldr r3, [r3, #0]
8001c98: 68ba ldr r2, [r7, #8]
8001c9a: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8001c9c: 68fb ldr r3, [r7, #12]
8001c9e: 681b ldr r3, [r3, #0]
8001ca0: 687a ldr r2, [r7, #4]
8001ca2: 60da str r2, [r3, #12]
}
8001ca4: bf00 nop
8001ca6: 3714 adds r7, #20
8001ca8: 46bd mov sp, r7
8001caa: bc80 pop {r7}
8001cac: 4770 bx lr
...
08001cb0 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001cb0: b480 push {r7}
8001cb2: b08b sub sp, #44 ; 0x2c
8001cb4: af00 add r7, sp, #0
8001cb6: 6078 str r0, [r7, #4]
8001cb8: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8001cba: 2300 movs r3, #0
8001cbc: 627b str r3, [r7, #36] ; 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
8001cbe: 2300 movs r3, #0
8001cc0: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001cc2: e127 b.n 8001f14 <HAL_GPIO_Init+0x264>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8001cc4: 2201 movs r2, #1
8001cc6: 6a7b ldr r3, [r7, #36] ; 0x24
8001cc8: fa02 f303 lsl.w r3, r2, r3
8001ccc: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8001cce: 683b ldr r3, [r7, #0]
8001cd0: 681b ldr r3, [r3, #0]
8001cd2: 69fa ldr r2, [r7, #28]
8001cd4: 4013 ands r3, r2
8001cd6: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8001cd8: 69ba ldr r2, [r7, #24]
8001cda: 69fb ldr r3, [r7, #28]
8001cdc: 429a cmp r2, r3
8001cde: f040 8116 bne.w 8001f0e <HAL_GPIO_Init+0x25e>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
8001ce2: 683b ldr r3, [r7, #0]
8001ce4: 685b ldr r3, [r3, #4]
8001ce6: 2b12 cmp r3, #18
8001ce8: d034 beq.n 8001d54 <HAL_GPIO_Init+0xa4>
8001cea: 2b12 cmp r3, #18
8001cec: d80d bhi.n 8001d0a <HAL_GPIO_Init+0x5a>
8001cee: 2b02 cmp r3, #2
8001cf0: d02b beq.n 8001d4a <HAL_GPIO_Init+0x9a>
8001cf2: 2b02 cmp r3, #2
8001cf4: d804 bhi.n 8001d00 <HAL_GPIO_Init+0x50>
8001cf6: 2b00 cmp r3, #0
8001cf8: d031 beq.n 8001d5e <HAL_GPIO_Init+0xae>
8001cfa: 2b01 cmp r3, #1
8001cfc: d01c beq.n 8001d38 <HAL_GPIO_Init+0x88>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
8001cfe: e048 b.n 8001d92 <HAL_GPIO_Init+0xe2>
switch (GPIO_Init->Mode)
8001d00: 2b03 cmp r3, #3
8001d02: d043 beq.n 8001d8c <HAL_GPIO_Init+0xdc>
8001d04: 2b11 cmp r3, #17
8001d06: d01b beq.n 8001d40 <HAL_GPIO_Init+0x90>
break;
8001d08: e043 b.n 8001d92 <HAL_GPIO_Init+0xe2>
switch (GPIO_Init->Mode)
8001d0a: 4a89 ldr r2, [pc, #548] ; (8001f30 <HAL_GPIO_Init+0x280>)
8001d0c: 4293 cmp r3, r2
8001d0e: d026 beq.n 8001d5e <HAL_GPIO_Init+0xae>
8001d10: 4a87 ldr r2, [pc, #540] ; (8001f30 <HAL_GPIO_Init+0x280>)
8001d12: 4293 cmp r3, r2
8001d14: d806 bhi.n 8001d24 <HAL_GPIO_Init+0x74>
8001d16: 4a87 ldr r2, [pc, #540] ; (8001f34 <HAL_GPIO_Init+0x284>)
8001d18: 4293 cmp r3, r2
8001d1a: d020 beq.n 8001d5e <HAL_GPIO_Init+0xae>
8001d1c: 4a86 ldr r2, [pc, #536] ; (8001f38 <HAL_GPIO_Init+0x288>)
8001d1e: 4293 cmp r3, r2
8001d20: d01d beq.n 8001d5e <HAL_GPIO_Init+0xae>
break;
8001d22: e036 b.n 8001d92 <HAL_GPIO_Init+0xe2>
switch (GPIO_Init->Mode)
8001d24: 4a85 ldr r2, [pc, #532] ; (8001f3c <HAL_GPIO_Init+0x28c>)
8001d26: 4293 cmp r3, r2
8001d28: d019 beq.n 8001d5e <HAL_GPIO_Init+0xae>
8001d2a: 4a85 ldr r2, [pc, #532] ; (8001f40 <HAL_GPIO_Init+0x290>)
8001d2c: 4293 cmp r3, r2
8001d2e: d016 beq.n 8001d5e <HAL_GPIO_Init+0xae>
8001d30: 4a84 ldr r2, [pc, #528] ; (8001f44 <HAL_GPIO_Init+0x294>)
8001d32: 4293 cmp r3, r2
8001d34: d013 beq.n 8001d5e <HAL_GPIO_Init+0xae>
break;
8001d36: e02c b.n 8001d92 <HAL_GPIO_Init+0xe2>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8001d38: 683b ldr r3, [r7, #0]
8001d3a: 68db ldr r3, [r3, #12]
8001d3c: 623b str r3, [r7, #32]
break;
8001d3e: e028 b.n 8001d92 <HAL_GPIO_Init+0xe2>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8001d40: 683b ldr r3, [r7, #0]
8001d42: 68db ldr r3, [r3, #12]
8001d44: 3304 adds r3, #4
8001d46: 623b str r3, [r7, #32]
break;
8001d48: e023 b.n 8001d92 <HAL_GPIO_Init+0xe2>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
8001d4a: 683b ldr r3, [r7, #0]
8001d4c: 68db ldr r3, [r3, #12]
8001d4e: 3308 adds r3, #8
8001d50: 623b str r3, [r7, #32]
break;
8001d52: e01e b.n 8001d92 <HAL_GPIO_Init+0xe2>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8001d54: 683b ldr r3, [r7, #0]
8001d56: 68db ldr r3, [r3, #12]
8001d58: 330c adds r3, #12
8001d5a: 623b str r3, [r7, #32]
break;
8001d5c: e019 b.n 8001d92 <HAL_GPIO_Init+0xe2>
if (GPIO_Init->Pull == GPIO_NOPULL)
8001d5e: 683b ldr r3, [r7, #0]
8001d60: 689b ldr r3, [r3, #8]
8001d62: 2b00 cmp r3, #0
8001d64: d102 bne.n 8001d6c <HAL_GPIO_Init+0xbc>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
8001d66: 2304 movs r3, #4
8001d68: 623b str r3, [r7, #32]
break;
8001d6a: e012 b.n 8001d92 <HAL_GPIO_Init+0xe2>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8001d6c: 683b ldr r3, [r7, #0]
8001d6e: 689b ldr r3, [r3, #8]
8001d70: 2b01 cmp r3, #1
8001d72: d105 bne.n 8001d80 <HAL_GPIO_Init+0xd0>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8001d74: 2308 movs r3, #8
8001d76: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8001d78: 687b ldr r3, [r7, #4]
8001d7a: 69fa ldr r2, [r7, #28]
8001d7c: 611a str r2, [r3, #16]
break;
8001d7e: e008 b.n 8001d92 <HAL_GPIO_Init+0xe2>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8001d80: 2308 movs r3, #8
8001d82: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
8001d84: 687b ldr r3, [r7, #4]
8001d86: 69fa ldr r2, [r7, #28]
8001d88: 615a str r2, [r3, #20]
break;
8001d8a: e002 b.n 8001d92 <HAL_GPIO_Init+0xe2>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8001d8c: 2300 movs r3, #0
8001d8e: 623b str r3, [r7, #32]
break;
8001d90: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
8001d92: 69bb ldr r3, [r7, #24]
8001d94: 2bff cmp r3, #255 ; 0xff
8001d96: d801 bhi.n 8001d9c <HAL_GPIO_Init+0xec>
8001d98: 687b ldr r3, [r7, #4]
8001d9a: e001 b.n 8001da0 <HAL_GPIO_Init+0xf0>
8001d9c: 687b ldr r3, [r7, #4]
8001d9e: 3304 adds r3, #4
8001da0: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
8001da2: 69bb ldr r3, [r7, #24]
8001da4: 2bff cmp r3, #255 ; 0xff
8001da6: d802 bhi.n 8001dae <HAL_GPIO_Init+0xfe>
8001da8: 6a7b ldr r3, [r7, #36] ; 0x24
8001daa: 009b lsls r3, r3, #2
8001dac: e002 b.n 8001db4 <HAL_GPIO_Init+0x104>
8001dae: 6a7b ldr r3, [r7, #36] ; 0x24
8001db0: 3b08 subs r3, #8
8001db2: 009b lsls r3, r3, #2
8001db4: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
8001db6: 697b ldr r3, [r7, #20]
8001db8: 681a ldr r2, [r3, #0]
8001dba: 210f movs r1, #15
8001dbc: 693b ldr r3, [r7, #16]
8001dbe: fa01 f303 lsl.w r3, r1, r3
8001dc2: 43db mvns r3, r3
8001dc4: 401a ands r2, r3
8001dc6: 6a39 ldr r1, [r7, #32]
8001dc8: 693b ldr r3, [r7, #16]
8001dca: fa01 f303 lsl.w r3, r1, r3
8001dce: 431a orrs r2, r3
8001dd0: 697b ldr r3, [r7, #20]
8001dd2: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8001dd4: 683b ldr r3, [r7, #0]
8001dd6: 685b ldr r3, [r3, #4]
8001dd8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001ddc: 2b00 cmp r3, #0
8001dde: f000 8096 beq.w 8001f0e <HAL_GPIO_Init+0x25e>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
8001de2: 4b59 ldr r3, [pc, #356] ; (8001f48 <HAL_GPIO_Init+0x298>)
8001de4: 699b ldr r3, [r3, #24]
8001de6: 4a58 ldr r2, [pc, #352] ; (8001f48 <HAL_GPIO_Init+0x298>)
8001de8: f043 0301 orr.w r3, r3, #1
8001dec: 6193 str r3, [r2, #24]
8001dee: 4b56 ldr r3, [pc, #344] ; (8001f48 <HAL_GPIO_Init+0x298>)
8001df0: 699b ldr r3, [r3, #24]
8001df2: f003 0301 and.w r3, r3, #1
8001df6: 60bb str r3, [r7, #8]
8001df8: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8001dfa: 4a54 ldr r2, [pc, #336] ; (8001f4c <HAL_GPIO_Init+0x29c>)
8001dfc: 6a7b ldr r3, [r7, #36] ; 0x24
8001dfe: 089b lsrs r3, r3, #2
8001e00: 3302 adds r3, #2
8001e02: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001e06: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8001e08: 6a7b ldr r3, [r7, #36] ; 0x24
8001e0a: f003 0303 and.w r3, r3, #3
8001e0e: 009b lsls r3, r3, #2
8001e10: 220f movs r2, #15
8001e12: fa02 f303 lsl.w r3, r2, r3
8001e16: 43db mvns r3, r3
8001e18: 68fa ldr r2, [r7, #12]
8001e1a: 4013 ands r3, r2
8001e1c: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8001e1e: 687b ldr r3, [r7, #4]
8001e20: 4a4b ldr r2, [pc, #300] ; (8001f50 <HAL_GPIO_Init+0x2a0>)
8001e22: 4293 cmp r3, r2
8001e24: d013 beq.n 8001e4e <HAL_GPIO_Init+0x19e>
8001e26: 687b ldr r3, [r7, #4]
8001e28: 4a4a ldr r2, [pc, #296] ; (8001f54 <HAL_GPIO_Init+0x2a4>)
8001e2a: 4293 cmp r3, r2
8001e2c: d00d beq.n 8001e4a <HAL_GPIO_Init+0x19a>
8001e2e: 687b ldr r3, [r7, #4]
8001e30: 4a49 ldr r2, [pc, #292] ; (8001f58 <HAL_GPIO_Init+0x2a8>)
8001e32: 4293 cmp r3, r2
8001e34: d007 beq.n 8001e46 <HAL_GPIO_Init+0x196>
8001e36: 687b ldr r3, [r7, #4]
8001e38: 4a48 ldr r2, [pc, #288] ; (8001f5c <HAL_GPIO_Init+0x2ac>)
8001e3a: 4293 cmp r3, r2
8001e3c: d101 bne.n 8001e42 <HAL_GPIO_Init+0x192>
8001e3e: 2303 movs r3, #3
8001e40: e006 b.n 8001e50 <HAL_GPIO_Init+0x1a0>
8001e42: 2304 movs r3, #4
8001e44: e004 b.n 8001e50 <HAL_GPIO_Init+0x1a0>
8001e46: 2302 movs r3, #2
8001e48: e002 b.n 8001e50 <HAL_GPIO_Init+0x1a0>
8001e4a: 2301 movs r3, #1
8001e4c: e000 b.n 8001e50 <HAL_GPIO_Init+0x1a0>
8001e4e: 2300 movs r3, #0
8001e50: 6a7a ldr r2, [r7, #36] ; 0x24
8001e52: f002 0203 and.w r2, r2, #3
8001e56: 0092 lsls r2, r2, #2
8001e58: 4093 lsls r3, r2
8001e5a: 68fa ldr r2, [r7, #12]
8001e5c: 4313 orrs r3, r2
8001e5e: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8001e60: 493a ldr r1, [pc, #232] ; (8001f4c <HAL_GPIO_Init+0x29c>)
8001e62: 6a7b ldr r3, [r7, #36] ; 0x24
8001e64: 089b lsrs r3, r3, #2
8001e66: 3302 adds r3, #2
8001e68: 68fa ldr r2, [r7, #12]
8001e6a: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8001e6e: 683b ldr r3, [r7, #0]
8001e70: 685b ldr r3, [r3, #4]
8001e72: f403 3380 and.w r3, r3, #65536 ; 0x10000
8001e76: 2b00 cmp r3, #0
8001e78: d006 beq.n 8001e88 <HAL_GPIO_Init+0x1d8>
{
SET_BIT(EXTI->IMR, iocurrent);
8001e7a: 4b39 ldr r3, [pc, #228] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001e7c: 681a ldr r2, [r3, #0]
8001e7e: 4938 ldr r1, [pc, #224] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001e80: 69bb ldr r3, [r7, #24]
8001e82: 4313 orrs r3, r2
8001e84: 600b str r3, [r1, #0]
8001e86: e006 b.n 8001e96 <HAL_GPIO_Init+0x1e6>
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8001e88: 4b35 ldr r3, [pc, #212] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001e8a: 681a ldr r2, [r3, #0]
8001e8c: 69bb ldr r3, [r7, #24]
8001e8e: 43db mvns r3, r3
8001e90: 4933 ldr r1, [pc, #204] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001e92: 4013 ands r3, r2
8001e94: 600b str r3, [r1, #0]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8001e96: 683b ldr r3, [r7, #0]
8001e98: 685b ldr r3, [r3, #4]
8001e9a: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001e9e: 2b00 cmp r3, #0
8001ea0: d006 beq.n 8001eb0 <HAL_GPIO_Init+0x200>
{
SET_BIT(EXTI->EMR, iocurrent);
8001ea2: 4b2f ldr r3, [pc, #188] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001ea4: 685a ldr r2, [r3, #4]
8001ea6: 492e ldr r1, [pc, #184] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001ea8: 69bb ldr r3, [r7, #24]
8001eaa: 4313 orrs r3, r2
8001eac: 604b str r3, [r1, #4]
8001eae: e006 b.n 8001ebe <HAL_GPIO_Init+0x20e>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8001eb0: 4b2b ldr r3, [pc, #172] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001eb2: 685a ldr r2, [r3, #4]
8001eb4: 69bb ldr r3, [r7, #24]
8001eb6: 43db mvns r3, r3
8001eb8: 4929 ldr r1, [pc, #164] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001eba: 4013 ands r3, r2
8001ebc: 604b str r3, [r1, #4]
}
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8001ebe: 683b ldr r3, [r7, #0]
8001ec0: 685b ldr r3, [r3, #4]
8001ec2: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8001ec6: 2b00 cmp r3, #0
8001ec8: d006 beq.n 8001ed8 <HAL_GPIO_Init+0x228>
{
SET_BIT(EXTI->RTSR, iocurrent);
8001eca: 4b25 ldr r3, [pc, #148] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001ecc: 689a ldr r2, [r3, #8]
8001ece: 4924 ldr r1, [pc, #144] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001ed0: 69bb ldr r3, [r7, #24]
8001ed2: 4313 orrs r3, r2
8001ed4: 608b str r3, [r1, #8]
8001ed6: e006 b.n 8001ee6 <HAL_GPIO_Init+0x236>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8001ed8: 4b21 ldr r3, [pc, #132] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001eda: 689a ldr r2, [r3, #8]
8001edc: 69bb ldr r3, [r7, #24]
8001ede: 43db mvns r3, r3
8001ee0: 491f ldr r1, [pc, #124] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001ee2: 4013 ands r3, r2
8001ee4: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8001ee6: 683b ldr r3, [r7, #0]
8001ee8: 685b ldr r3, [r3, #4]
8001eea: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001eee: 2b00 cmp r3, #0
8001ef0: d006 beq.n 8001f00 <HAL_GPIO_Init+0x250>
{
SET_BIT(EXTI->FTSR, iocurrent);
8001ef2: 4b1b ldr r3, [pc, #108] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001ef4: 68da ldr r2, [r3, #12]
8001ef6: 491a ldr r1, [pc, #104] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001ef8: 69bb ldr r3, [r7, #24]
8001efa: 4313 orrs r3, r2
8001efc: 60cb str r3, [r1, #12]
8001efe: e006 b.n 8001f0e <HAL_GPIO_Init+0x25e>
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8001f00: 4b17 ldr r3, [pc, #92] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001f02: 68da ldr r2, [r3, #12]
8001f04: 69bb ldr r3, [r7, #24]
8001f06: 43db mvns r3, r3
8001f08: 4915 ldr r1, [pc, #84] ; (8001f60 <HAL_GPIO_Init+0x2b0>)
8001f0a: 4013 ands r3, r2
8001f0c: 60cb str r3, [r1, #12]
}
}
}
position++;
8001f0e: 6a7b ldr r3, [r7, #36] ; 0x24
8001f10: 3301 adds r3, #1
8001f12: 627b str r3, [r7, #36] ; 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001f14: 683b ldr r3, [r7, #0]
8001f16: 681a ldr r2, [r3, #0]
8001f18: 6a7b ldr r3, [r7, #36] ; 0x24
8001f1a: fa22 f303 lsr.w r3, r2, r3
8001f1e: 2b00 cmp r3, #0
8001f20: f47f aed0 bne.w 8001cc4 <HAL_GPIO_Init+0x14>
}
}
8001f24: bf00 nop
8001f26: 372c adds r7, #44 ; 0x2c
8001f28: 46bd mov sp, r7
8001f2a: bc80 pop {r7}
8001f2c: 4770 bx lr
8001f2e: bf00 nop
8001f30: 10210000 .word 0x10210000
8001f34: 10110000 .word 0x10110000
8001f38: 10120000 .word 0x10120000
8001f3c: 10310000 .word 0x10310000
8001f40: 10320000 .word 0x10320000
8001f44: 10220000 .word 0x10220000
8001f48: 40021000 .word 0x40021000
8001f4c: 40010000 .word 0x40010000
8001f50: 40010800 .word 0x40010800
8001f54: 40010c00 .word 0x40010c00
8001f58: 40011000 .word 0x40011000
8001f5c: 40011400 .word 0x40011400
8001f60: 40010400 .word 0x40010400
08001f64 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001f64: b480 push {r7}
8001f66: b083 sub sp, #12
8001f68: af00 add r7, sp, #0
8001f6a: 6078 str r0, [r7, #4]
8001f6c: 460b mov r3, r1
8001f6e: 807b strh r3, [r7, #2]
8001f70: 4613 mov r3, r2
8001f72: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001f74: 787b ldrb r3, [r7, #1]
8001f76: 2b00 cmp r3, #0
8001f78: d003 beq.n 8001f82 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8001f7a: 887a ldrh r2, [r7, #2]
8001f7c: 687b ldr r3, [r7, #4]
8001f7e: 611a str r2, [r3, #16]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
}
}
8001f80: e003 b.n 8001f8a <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
8001f82: 887b ldrh r3, [r7, #2]
8001f84: 041a lsls r2, r3, #16
8001f86: 687b ldr r3, [r7, #4]
8001f88: 611a str r2, [r3, #16]
}
8001f8a: bf00 nop
8001f8c: 370c adds r7, #12
8001f8e: 46bd mov sp, r7
8001f90: bc80 pop {r7}
8001f92: 4770 bx lr
08001f94 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8001f94: b580 push {r7, lr}
8001f96: b084 sub sp, #16
8001f98: af00 add r7, sp, #0
8001f9a: 6078 str r0, [r7, #4]
uint32_t freqrange;
uint32_t pclk1;
/* Check the I2C handle allocation */
if (hi2c == NULL)
8001f9c: 687b ldr r3, [r7, #4]
8001f9e: 2b00 cmp r3, #0
8001fa0: d101 bne.n 8001fa6 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8001fa2: 2301 movs r3, #1
8001fa4: e10f b.n 80021c6 <HAL_I2C_Init+0x232>
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8001fa6: 687b ldr r3, [r7, #4]
8001fa8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001fac: b2db uxtb r3, r3
8001fae: 2b00 cmp r3, #0
8001fb0: d106 bne.n 8001fc0 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8001fb2: 687b ldr r3, [r7, #4]
8001fb4: 2200 movs r2, #0
8001fb6: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
8001fba: 6878 ldr r0, [r7, #4]
8001fbc: f7ff f854 bl 8001068 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8001fc0: 687b ldr r3, [r7, #4]
8001fc2: 2224 movs r2, #36 ; 0x24
8001fc4: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001fc8: 687b ldr r3, [r7, #4]
8001fca: 681b ldr r3, [r3, #0]
8001fcc: 681a ldr r2, [r3, #0]
8001fce: 687b ldr r3, [r7, #4]
8001fd0: 681b ldr r3, [r3, #0]
8001fd2: f022 0201 bic.w r2, r2, #1
8001fd6: 601a str r2, [r3, #0]
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
8001fd8: f001 fbbc bl 8003754 <HAL_RCC_GetPCLK1Freq>
8001fdc: 60f8 str r0, [r7, #12]
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
8001fde: 687b ldr r3, [r7, #4]
8001fe0: 685b ldr r3, [r3, #4]
8001fe2: 4a7b ldr r2, [pc, #492] ; (80021d0 <HAL_I2C_Init+0x23c>)
8001fe4: 4293 cmp r3, r2
8001fe6: d807 bhi.n 8001ff8 <HAL_I2C_Init+0x64>
8001fe8: 68fb ldr r3, [r7, #12]
8001fea: 4a7a ldr r2, [pc, #488] ; (80021d4 <HAL_I2C_Init+0x240>)
8001fec: 4293 cmp r3, r2
8001fee: bf94 ite ls
8001ff0: 2301 movls r3, #1
8001ff2: 2300 movhi r3, #0
8001ff4: b2db uxtb r3, r3
8001ff6: e006 b.n 8002006 <HAL_I2C_Init+0x72>
8001ff8: 68fb ldr r3, [r7, #12]
8001ffa: 4a77 ldr r2, [pc, #476] ; (80021d8 <HAL_I2C_Init+0x244>)
8001ffc: 4293 cmp r3, r2
8001ffe: bf94 ite ls
8002000: 2301 movls r3, #1
8002002: 2300 movhi r3, #0
8002004: b2db uxtb r3, r3
8002006: 2b00 cmp r3, #0
8002008: d001 beq.n 800200e <HAL_I2C_Init+0x7a>
{
return HAL_ERROR;
800200a: 2301 movs r3, #1
800200c: e0db b.n 80021c6 <HAL_I2C_Init+0x232>
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
800200e: 68fb ldr r3, [r7, #12]
8002010: 4a72 ldr r2, [pc, #456] ; (80021dc <HAL_I2C_Init+0x248>)
8002012: fba2 2303 umull r2, r3, r2, r3
8002016: 0c9b lsrs r3, r3, #18
8002018: 60bb str r3, [r7, #8]
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
800201a: 687b ldr r3, [r7, #4]
800201c: 681b ldr r3, [r3, #0]
800201e: 685b ldr r3, [r3, #4]
8002020: f023 013f bic.w r1, r3, #63 ; 0x3f
8002024: 687b ldr r3, [r7, #4]
8002026: 681b ldr r3, [r3, #0]
8002028: 68ba ldr r2, [r7, #8]
800202a: 430a orrs r2, r1
800202c: 605a str r2, [r3, #4]
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
800202e: 687b ldr r3, [r7, #4]
8002030: 681b ldr r3, [r3, #0]
8002032: 6a1b ldr r3, [r3, #32]
8002034: f023 013f bic.w r1, r3, #63 ; 0x3f
8002038: 687b ldr r3, [r7, #4]
800203a: 685b ldr r3, [r3, #4]
800203c: 4a64 ldr r2, [pc, #400] ; (80021d0 <HAL_I2C_Init+0x23c>)
800203e: 4293 cmp r3, r2
8002040: d802 bhi.n 8002048 <HAL_I2C_Init+0xb4>
8002042: 68bb ldr r3, [r7, #8]
8002044: 3301 adds r3, #1
8002046: e009 b.n 800205c <HAL_I2C_Init+0xc8>
8002048: 68bb ldr r3, [r7, #8]
800204a: f44f 7296 mov.w r2, #300 ; 0x12c
800204e: fb02 f303 mul.w r3, r2, r3
8002052: 4a63 ldr r2, [pc, #396] ; (80021e0 <HAL_I2C_Init+0x24c>)
8002054: fba2 2303 umull r2, r3, r2, r3
8002058: 099b lsrs r3, r3, #6
800205a: 3301 adds r3, #1
800205c: 687a ldr r2, [r7, #4]
800205e: 6812 ldr r2, [r2, #0]
8002060: 430b orrs r3, r1
8002062: 6213 str r3, [r2, #32]
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
8002064: 687b ldr r3, [r7, #4]
8002066: 681b ldr r3, [r3, #0]
8002068: 69db ldr r3, [r3, #28]
800206a: f423 424f bic.w r2, r3, #52992 ; 0xcf00
800206e: f022 02ff bic.w r2, r2, #255 ; 0xff
8002072: 687b ldr r3, [r7, #4]
8002074: 685b ldr r3, [r3, #4]
8002076: 4956 ldr r1, [pc, #344] ; (80021d0 <HAL_I2C_Init+0x23c>)
8002078: 428b cmp r3, r1
800207a: d80d bhi.n 8002098 <HAL_I2C_Init+0x104>
800207c: 68fb ldr r3, [r7, #12]
800207e: 1e59 subs r1, r3, #1
8002080: 687b ldr r3, [r7, #4]
8002082: 685b ldr r3, [r3, #4]
8002084: 005b lsls r3, r3, #1
8002086: fbb1 f3f3 udiv r3, r1, r3
800208a: 3301 adds r3, #1
800208c: f3c3 030b ubfx r3, r3, #0, #12
8002090: 2b04 cmp r3, #4
8002092: bf38 it cc
8002094: 2304 movcc r3, #4
8002096: e04f b.n 8002138 <HAL_I2C_Init+0x1a4>
8002098: 687b ldr r3, [r7, #4]
800209a: 689b ldr r3, [r3, #8]
800209c: 2b00 cmp r3, #0
800209e: d111 bne.n 80020c4 <HAL_I2C_Init+0x130>
80020a0: 68fb ldr r3, [r7, #12]
80020a2: 1e58 subs r0, r3, #1
80020a4: 687b ldr r3, [r7, #4]
80020a6: 6859 ldr r1, [r3, #4]
80020a8: 460b mov r3, r1
80020aa: 005b lsls r3, r3, #1
80020ac: 440b add r3, r1
80020ae: fbb0 f3f3 udiv r3, r0, r3
80020b2: 3301 adds r3, #1
80020b4: f3c3 030b ubfx r3, r3, #0, #12
80020b8: 2b00 cmp r3, #0
80020ba: bf0c ite eq
80020bc: 2301 moveq r3, #1
80020be: 2300 movne r3, #0
80020c0: b2db uxtb r3, r3
80020c2: e012 b.n 80020ea <HAL_I2C_Init+0x156>
80020c4: 68fb ldr r3, [r7, #12]
80020c6: 1e58 subs r0, r3, #1
80020c8: 687b ldr r3, [r7, #4]
80020ca: 6859 ldr r1, [r3, #4]
80020cc: 460b mov r3, r1
80020ce: 009b lsls r3, r3, #2
80020d0: 440b add r3, r1
80020d2: 0099 lsls r1, r3, #2
80020d4: 440b add r3, r1
80020d6: fbb0 f3f3 udiv r3, r0, r3
80020da: 3301 adds r3, #1
80020dc: f3c3 030b ubfx r3, r3, #0, #12
80020e0: 2b00 cmp r3, #0
80020e2: bf0c ite eq
80020e4: 2301 moveq r3, #1
80020e6: 2300 movne r3, #0
80020e8: b2db uxtb r3, r3
80020ea: 2b00 cmp r3, #0
80020ec: d001 beq.n 80020f2 <HAL_I2C_Init+0x15e>
80020ee: 2301 movs r3, #1
80020f0: e022 b.n 8002138 <HAL_I2C_Init+0x1a4>
80020f2: 687b ldr r3, [r7, #4]
80020f4: 689b ldr r3, [r3, #8]
80020f6: 2b00 cmp r3, #0
80020f8: d10e bne.n 8002118 <HAL_I2C_Init+0x184>
80020fa: 68fb ldr r3, [r7, #12]
80020fc: 1e58 subs r0, r3, #1
80020fe: 687b ldr r3, [r7, #4]
8002100: 6859 ldr r1, [r3, #4]
8002102: 460b mov r3, r1
8002104: 005b lsls r3, r3, #1
8002106: 440b add r3, r1
8002108: fbb0 f3f3 udiv r3, r0, r3
800210c: 3301 adds r3, #1
800210e: f3c3 030b ubfx r3, r3, #0, #12
8002112: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8002116: e00f b.n 8002138 <HAL_I2C_Init+0x1a4>
8002118: 68fb ldr r3, [r7, #12]
800211a: 1e58 subs r0, r3, #1
800211c: 687b ldr r3, [r7, #4]
800211e: 6859 ldr r1, [r3, #4]
8002120: 460b mov r3, r1
8002122: 009b lsls r3, r3, #2
8002124: 440b add r3, r1
8002126: 0099 lsls r1, r3, #2
8002128: 440b add r3, r1
800212a: fbb0 f3f3 udiv r3, r0, r3
800212e: 3301 adds r3, #1
8002130: f3c3 030b ubfx r3, r3, #0, #12
8002134: f443 4340 orr.w r3, r3, #49152 ; 0xc000
8002138: 6879 ldr r1, [r7, #4]
800213a: 6809 ldr r1, [r1, #0]
800213c: 4313 orrs r3, r2
800213e: 61cb str r3, [r1, #28]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
8002140: 687b ldr r3, [r7, #4]
8002142: 681b ldr r3, [r3, #0]
8002144: 681b ldr r3, [r3, #0]
8002146: f023 01c0 bic.w r1, r3, #192 ; 0xc0
800214a: 687b ldr r3, [r7, #4]
800214c: 69da ldr r2, [r3, #28]
800214e: 687b ldr r3, [r7, #4]
8002150: 6a1b ldr r3, [r3, #32]
8002152: 431a orrs r2, r3
8002154: 687b ldr r3, [r7, #4]
8002156: 681b ldr r3, [r3, #0]
8002158: 430a orrs r2, r1
800215a: 601a str r2, [r3, #0]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
800215c: 687b ldr r3, [r7, #4]
800215e: 681b ldr r3, [r3, #0]
8002160: 689b ldr r3, [r3, #8]
8002162: f423 4303 bic.w r3, r3, #33536 ; 0x8300
8002166: f023 03ff bic.w r3, r3, #255 ; 0xff
800216a: 687a ldr r2, [r7, #4]
800216c: 6911 ldr r1, [r2, #16]
800216e: 687a ldr r2, [r7, #4]
8002170: 68d2 ldr r2, [r2, #12]
8002172: 4311 orrs r1, r2
8002174: 687a ldr r2, [r7, #4]
8002176: 6812 ldr r2, [r2, #0]
8002178: 430b orrs r3, r1
800217a: 6093 str r3, [r2, #8]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
800217c: 687b ldr r3, [r7, #4]
800217e: 681b ldr r3, [r3, #0]
8002180: 68db ldr r3, [r3, #12]
8002182: f023 01ff bic.w r1, r3, #255 ; 0xff
8002186: 687b ldr r3, [r7, #4]
8002188: 695a ldr r2, [r3, #20]
800218a: 687b ldr r3, [r7, #4]
800218c: 699b ldr r3, [r3, #24]
800218e: 431a orrs r2, r3
8002190: 687b ldr r3, [r7, #4]
8002192: 681b ldr r3, [r3, #0]
8002194: 430a orrs r2, r1
8002196: 60da str r2, [r3, #12]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8002198: 687b ldr r3, [r7, #4]
800219a: 681b ldr r3, [r3, #0]
800219c: 681a ldr r2, [r3, #0]
800219e: 687b ldr r3, [r7, #4]
80021a0: 681b ldr r3, [r3, #0]
80021a2: f042 0201 orr.w r2, r2, #1
80021a6: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80021a8: 687b ldr r3, [r7, #4]
80021aa: 2200 movs r2, #0
80021ac: 641a str r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_READY;
80021ae: 687b ldr r3, [r7, #4]
80021b0: 2220 movs r2, #32
80021b2: f883 203d strb.w r2, [r3, #61] ; 0x3d
hi2c->PreviousState = I2C_STATE_NONE;
80021b6: 687b ldr r3, [r7, #4]
80021b8: 2200 movs r2, #0
80021ba: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80021bc: 687b ldr r3, [r7, #4]
80021be: 2200 movs r2, #0
80021c0: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
80021c4: 2300 movs r3, #0
}
80021c6: 4618 mov r0, r3
80021c8: 3710 adds r7, #16
80021ca: 46bd mov sp, r7
80021cc: bd80 pop {r7, pc}
80021ce: bf00 nop
80021d0: 000186a0 .word 0x000186a0
80021d4: 001e847f .word 0x001e847f
80021d8: 003d08ff .word 0x003d08ff
80021dc: 431bde83 .word 0x431bde83
80021e0: 10624dd3 .word 0x10624dd3
080021e4 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
80021e4: b5f0 push {r4, r5, r6, r7, lr}
80021e6: b08b sub sp, #44 ; 0x2c
80021e8: af06 add r7, sp, #24
80021ea: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx;
#endif /* defined (USB_OTG_FS) */
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
80021ec: 687b ldr r3, [r7, #4]
80021ee: 2b00 cmp r3, #0
80021f0: d101 bne.n 80021f6 <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
80021f2: 2301 movs r3, #1
80021f4: e0d3 b.n 800239e <HAL_PCD_Init+0x1ba>
#if defined (USB_OTG_FS)
USBx = hpcd->Instance;
#endif /* defined (USB_OTG_FS) */
if (hpcd->State == HAL_PCD_STATE_RESET)
80021f6: 687b ldr r3, [r7, #4]
80021f8: f893 3229 ldrb.w r3, [r3, #553] ; 0x229
80021fc: b2db uxtb r3, r3
80021fe: 2b00 cmp r3, #0
8002200: d106 bne.n 8002210 <HAL_PCD_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8002202: 687b ldr r3, [r7, #4]
8002204: 2200 movs r2, #0
8002206: f883 2228 strb.w r2, [r3, #552] ; 0x228
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
800220a: 6878 ldr r0, [r7, #4]
800220c: f005 fcce bl 8007bac <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8002210: 687b ldr r3, [r7, #4]
8002212: 2203 movs r2, #3
8002214: f883 2229 strb.w r2, [r3, #553] ; 0x229
hpcd->Init.dma_enable = 0U;
}
#endif /* defined (USB_OTG_FS) */
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
8002218: 687b ldr r3, [r7, #4]
800221a: 681b ldr r3, [r3, #0]
800221c: 4618 mov r0, r3
800221e: f002 fe22 bl 8004e66 <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8002222: 687b ldr r3, [r7, #4]
8002224: 681b ldr r3, [r3, #0]
8002226: 603b str r3, [r7, #0]
8002228: 687e ldr r6, [r7, #4]
800222a: 466d mov r5, sp
800222c: f106 0410 add.w r4, r6, #16
8002230: cc0f ldmia r4!, {r0, r1, r2, r3}
8002232: c50f stmia r5!, {r0, r1, r2, r3}
8002234: 6823 ldr r3, [r4, #0]
8002236: 602b str r3, [r5, #0]
8002238: 1d33 adds r3, r6, #4
800223a: cb0e ldmia r3, {r1, r2, r3}
800223c: 6838 ldr r0, [r7, #0]
800223e: f002 fdeb bl 8004e18 <USB_CoreInit>
8002242: 4603 mov r3, r0
8002244: 2b00 cmp r3, #0
8002246: d005 beq.n 8002254 <HAL_PCD_Init+0x70>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8002248: 687b ldr r3, [r7, #4]
800224a: 2202 movs r2, #2
800224c: f883 2229 strb.w r2, [r3, #553] ; 0x229
return HAL_ERROR;
8002250: 2301 movs r3, #1
8002252: e0a4 b.n 800239e <HAL_PCD_Init+0x1ba>
}
/* Force Device Mode*/
(void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
8002254: 687b ldr r3, [r7, #4]
8002256: 681b ldr r3, [r3, #0]
8002258: 2100 movs r1, #0
800225a: 4618 mov r0, r3
800225c: f002 fe1f bl 8004e9e <USB_SetCurrentMode>
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8002260: 2300 movs r3, #0
8002262: 73fb strb r3, [r7, #15]
8002264: e035 b.n 80022d2 <HAL_PCD_Init+0xee>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
8002266: 7bfb ldrb r3, [r7, #15]
8002268: 687a ldr r2, [r7, #4]
800226a: 015b lsls r3, r3, #5
800226c: 4413 add r3, r2
800226e: 3329 adds r3, #41 ; 0x29
8002270: 2201 movs r2, #1
8002272: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
8002274: 7bfb ldrb r3, [r7, #15]
8002276: 687a ldr r2, [r7, #4]
8002278: 015b lsls r3, r3, #5
800227a: 4413 add r3, r2
800227c: 3328 adds r3, #40 ; 0x28
800227e: 7bfa ldrb r2, [r7, #15]
8002280: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].tx_fifo_num = i;
8002282: 7bfb ldrb r3, [r7, #15]
8002284: 7bfa ldrb r2, [r7, #15]
8002286: b291 uxth r1, r2
8002288: 687a ldr r2, [r7, #4]
800228a: 015b lsls r3, r3, #5
800228c: 4413 add r3, r2
800228e: 3336 adds r3, #54 ; 0x36
8002290: 460a mov r2, r1
8002292: 801a strh r2, [r3, #0]
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8002294: 7bfb ldrb r3, [r7, #15]
8002296: 687a ldr r2, [r7, #4]
8002298: 015b lsls r3, r3, #5
800229a: 4413 add r3, r2
800229c: 332b adds r3, #43 ; 0x2b
800229e: 2200 movs r2, #0
80022a0: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
80022a2: 7bfb ldrb r3, [r7, #15]
80022a4: 687a ldr r2, [r7, #4]
80022a6: 015b lsls r3, r3, #5
80022a8: 4413 add r3, r2
80022aa: 3338 adds r3, #56 ; 0x38
80022ac: 2200 movs r2, #0
80022ae: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
80022b0: 7bfb ldrb r3, [r7, #15]
80022b2: 687a ldr r2, [r7, #4]
80022b4: 015b lsls r3, r3, #5
80022b6: 4413 add r3, r2
80022b8: 333c adds r3, #60 ; 0x3c
80022ba: 2200 movs r2, #0
80022bc: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
80022be: 7bfb ldrb r3, [r7, #15]
80022c0: 687a ldr r2, [r7, #4]
80022c2: 3302 adds r3, #2
80022c4: 015b lsls r3, r3, #5
80022c6: 4413 add r3, r2
80022c8: 2200 movs r2, #0
80022ca: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80022cc: 7bfb ldrb r3, [r7, #15]
80022ce: 3301 adds r3, #1
80022d0: 73fb strb r3, [r7, #15]
80022d2: 7bfa ldrb r2, [r7, #15]
80022d4: 687b ldr r3, [r7, #4]
80022d6: 685b ldr r3, [r3, #4]
80022d8: 429a cmp r2, r3
80022da: d3c4 bcc.n 8002266 <HAL_PCD_Init+0x82>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
80022dc: 2300 movs r3, #0
80022de: 73fb strb r3, [r7, #15]
80022e0: e031 b.n 8002346 <HAL_PCD_Init+0x162>
{
hpcd->OUT_ep[i].is_in = 0U;
80022e2: 7bfb ldrb r3, [r7, #15]
80022e4: 687a ldr r2, [r7, #4]
80022e6: 015b lsls r3, r3, #5
80022e8: 4413 add r3, r2
80022ea: f203 1329 addw r3, r3, #297 ; 0x129
80022ee: 2200 movs r2, #0
80022f0: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
80022f2: 7bfb ldrb r3, [r7, #15]
80022f4: 687a ldr r2, [r7, #4]
80022f6: 015b lsls r3, r3, #5
80022f8: 4413 add r3, r2
80022fa: f503 7394 add.w r3, r3, #296 ; 0x128
80022fe: 7bfa ldrb r2, [r7, #15]
8002300: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8002302: 7bfb ldrb r3, [r7, #15]
8002304: 687a ldr r2, [r7, #4]
8002306: 015b lsls r3, r3, #5
8002308: 4413 add r3, r2
800230a: f203 132b addw r3, r3, #299 ; 0x12b
800230e: 2200 movs r2, #0
8002310: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
8002312: 7bfb ldrb r3, [r7, #15]
8002314: 687a ldr r2, [r7, #4]
8002316: 015b lsls r3, r3, #5
8002318: 4413 add r3, r2
800231a: f503 739c add.w r3, r3, #312 ; 0x138
800231e: 2200 movs r2, #0
8002320: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8002322: 7bfb ldrb r3, [r7, #15]
8002324: 687a ldr r2, [r7, #4]
8002326: 015b lsls r3, r3, #5
8002328: 4413 add r3, r2
800232a: f503 739e add.w r3, r3, #316 ; 0x13c
800232e: 2200 movs r2, #0
8002330: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8002332: 7bfb ldrb r3, [r7, #15]
8002334: 687a ldr r2, [r7, #4]
8002336: 330a adds r3, #10
8002338: 015b lsls r3, r3, #5
800233a: 4413 add r3, r2
800233c: 2200 movs r2, #0
800233e: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8002340: 7bfb ldrb r3, [r7, #15]
8002342: 3301 adds r3, #1
8002344: 73fb strb r3, [r7, #15]
8002346: 7bfa ldrb r2, [r7, #15]
8002348: 687b ldr r3, [r7, #4]
800234a: 685b ldr r3, [r3, #4]
800234c: 429a cmp r2, r3
800234e: d3c8 bcc.n 80022e2 <HAL_PCD_Init+0xfe>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8002350: 687b ldr r3, [r7, #4]
8002352: 681b ldr r3, [r3, #0]
8002354: 603b str r3, [r7, #0]
8002356: 687e ldr r6, [r7, #4]
8002358: 466d mov r5, sp
800235a: f106 0410 add.w r4, r6, #16
800235e: cc0f ldmia r4!, {r0, r1, r2, r3}
8002360: c50f stmia r5!, {r0, r1, r2, r3}
8002362: 6823 ldr r3, [r4, #0]
8002364: 602b str r3, [r5, #0]
8002366: 1d33 adds r3, r6, #4
8002368: cb0e ldmia r3, {r1, r2, r3}
800236a: 6838 ldr r0, [r7, #0]
800236c: f002 fda3 bl 8004eb6 <USB_DevInit>
8002370: 4603 mov r3, r0
8002372: 2b00 cmp r3, #0
8002374: d005 beq.n 8002382 <HAL_PCD_Init+0x19e>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8002376: 687b ldr r3, [r7, #4]
8002378: 2202 movs r2, #2
800237a: f883 2229 strb.w r2, [r3, #553] ; 0x229
return HAL_ERROR;
800237e: 2301 movs r3, #1
8002380: e00d b.n 800239e <HAL_PCD_Init+0x1ba>
}
hpcd->USB_Address = 0U;
8002382: 687b ldr r3, [r7, #4]
8002384: 2200 movs r2, #0
8002386: f883 2024 strb.w r2, [r3, #36] ; 0x24
hpcd->State = HAL_PCD_STATE_READY;
800238a: 687b ldr r3, [r7, #4]
800238c: 2201 movs r2, #1
800238e: f883 2229 strb.w r2, [r3, #553] ; 0x229
(void)USB_DevDisconnect(hpcd->Instance);
8002392: 687b ldr r3, [r7, #4]
8002394: 681b ldr r3, [r3, #0]
8002396: 4618 mov r0, r3
8002398: f003 fde1 bl 8005f5e <USB_DevDisconnect>
return HAL_OK;
800239c: 2300 movs r3, #0
}
800239e: 4618 mov r0, r3
80023a0: 3714 adds r7, #20
80023a2: 46bd mov sp, r7
80023a4: bdf0 pop {r4, r5, r6, r7, pc}
080023a6 <HAL_PCD_Start>:
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
80023a6: b580 push {r7, lr}
80023a8: b082 sub sp, #8
80023aa: af00 add r7, sp, #0
80023ac: 6078 str r0, [r7, #4]
__HAL_LOCK(hpcd);
80023ae: 687b ldr r3, [r7, #4]
80023b0: f893 3228 ldrb.w r3, [r3, #552] ; 0x228
80023b4: 2b01 cmp r3, #1
80023b6: d101 bne.n 80023bc <HAL_PCD_Start+0x16>
80023b8: 2302 movs r3, #2
80023ba: e016 b.n 80023ea <HAL_PCD_Start+0x44>
80023bc: 687b ldr r3, [r7, #4]
80023be: 2201 movs r2, #1
80023c0: f883 2228 strb.w r2, [r3, #552] ; 0x228
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 1U);
80023c4: 2101 movs r1, #1
80023c6: 6878 ldr r0, [r7, #4]
80023c8: f005 fe57 bl 800807a <HAL_PCDEx_SetConnectionState>
#endif /* defined (USB) */
(void)USB_DevConnect(hpcd->Instance);
80023cc: 687b ldr r3, [r7, #4]
80023ce: 681b ldr r3, [r3, #0]
80023d0: 4618 mov r0, r3
80023d2: f003 fdba bl 8005f4a <USB_DevConnect>
__HAL_PCD_ENABLE(hpcd);
80023d6: 687b ldr r3, [r7, #4]
80023d8: 681b ldr r3, [r3, #0]
80023da: 4618 mov r0, r3
80023dc: f002 fd2c bl 8004e38 <USB_EnableGlobalInt>
__HAL_UNLOCK(hpcd);
80023e0: 687b ldr r3, [r7, #4]
80023e2: 2200 movs r2, #0
80023e4: f883 2228 strb.w r2, [r3, #552] ; 0x228
return HAL_OK;
80023e8: 2300 movs r3, #0
}
80023ea: 4618 mov r0, r3
80023ec: 3708 adds r7, #8
80023ee: 46bd mov sp, r7
80023f0: bd80 pop {r7, pc}
080023f2 <HAL_PCD_IRQHandler>:
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
80023f2: b580 push {r7, lr}
80023f4: b082 sub sp, #8
80023f6: af00 add r7, sp, #0
80023f8: 6078 str r0, [r7, #4]
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
80023fa: 687b ldr r3, [r7, #4]
80023fc: 681b ldr r3, [r3, #0]
80023fe: 4618 mov r0, r3
8002400: f003 fdb7 bl 8005f72 <USB_ReadInterrupts>
8002404: 4603 mov r3, r0
8002406: f403 4300 and.w r3, r3, #32768 ; 0x8000
800240a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
800240e: d102 bne.n 8002416 <HAL_PCD_IRQHandler+0x24>
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
8002410: 6878 ldr r0, [r7, #4]
8002412: f000 faf3 bl 80029fc <PCD_EP_ISR_Handler>
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))
8002416: 687b ldr r3, [r7, #4]
8002418: 681b ldr r3, [r3, #0]
800241a: 4618 mov r0, r3
800241c: f003 fda9 bl 8005f72 <USB_ReadInterrupts>
8002420: 4603 mov r3, r0
8002422: f403 6380 and.w r3, r3, #1024 ; 0x400
8002426: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800242a: d112 bne.n 8002452 <HAL_PCD_IRQHandler+0x60>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
800242c: 687b ldr r3, [r7, #4]
800242e: 681b ldr r3, [r3, #0]
8002430: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
8002434: b29a uxth r2, r3
8002436: 687b ldr r3, [r7, #4]
8002438: 681b ldr r3, [r3, #0]
800243a: f422 6280 bic.w r2, r2, #1024 ; 0x400
800243e: b292 uxth r2, r2
8002440: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
8002444: 6878 ldr r0, [r7, #4]
8002446: f005 fc26 bl 8007c96 <HAL_PCD_ResetCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
800244a: 2100 movs r1, #0
800244c: 6878 ldr r0, [r7, #4]
800244e: f000 f8de bl 800260e <HAL_PCD_SetAddress>
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))
8002452: 687b ldr r3, [r7, #4]
8002454: 681b ldr r3, [r3, #0]
8002456: 4618 mov r0, r3
8002458: f003 fd8b bl 8005f72 <USB_ReadInterrupts>
800245c: 4603 mov r3, r0
800245e: f403 4380 and.w r3, r3, #16384 ; 0x4000
8002462: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
8002466: d10b bne.n 8002480 <HAL_PCD_IRQHandler+0x8e>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
8002468: 687b ldr r3, [r7, #4]
800246a: 681b ldr r3, [r3, #0]
800246c: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
8002470: b29a uxth r2, r3
8002472: 687b ldr r3, [r7, #4]
8002474: 681b ldr r3, [r3, #0]
8002476: f422 4280 bic.w r2, r2, #16384 ; 0x4000
800247a: b292 uxth r2, r2
800247c: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))
8002480: 687b ldr r3, [r7, #4]
8002482: 681b ldr r3, [r3, #0]
8002484: 4618 mov r0, r3
8002486: f003 fd74 bl 8005f72 <USB_ReadInterrupts>
800248a: 4603 mov r3, r0
800248c: f403 5300 and.w r3, r3, #8192 ; 0x2000
8002490: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8002494: d10b bne.n 80024ae <HAL_PCD_IRQHandler+0xbc>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
8002496: 687b ldr r3, [r7, #4]
8002498: 681b ldr r3, [r3, #0]
800249a: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
800249e: b29a uxth r2, r3
80024a0: 687b ldr r3, [r7, #4]
80024a2: 681b ldr r3, [r3, #0]
80024a4: f422 5200 bic.w r2, r2, #8192 ; 0x2000
80024a8: b292 uxth r2, r2
80024aa: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
80024ae: 687b ldr r3, [r7, #4]
80024b0: 681b ldr r3, [r3, #0]
80024b2: 4618 mov r0, r3
80024b4: f003 fd5d bl 8005f72 <USB_ReadInterrupts>
80024b8: 4603 mov r3, r0
80024ba: f403 5380 and.w r3, r3, #4096 ; 0x1000
80024be: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80024c2: d126 bne.n 8002512 <HAL_PCD_IRQHandler+0x120>
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
80024c4: 687b ldr r3, [r7, #4]
80024c6: 681b ldr r3, [r3, #0]
80024c8: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40
80024cc: b29a uxth r2, r3
80024ce: 687b ldr r3, [r7, #4]
80024d0: 681b ldr r3, [r3, #0]
80024d2: f022 0204 bic.w r2, r2, #4
80024d6: b292 uxth r2, r2
80024d8: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
80024dc: 687b ldr r3, [r7, #4]
80024de: 681b ldr r3, [r3, #0]
80024e0: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40
80024e4: b29a uxth r2, r3
80024e6: 687b ldr r3, [r7, #4]
80024e8: 681b ldr r3, [r3, #0]
80024ea: f022 0208 bic.w r2, r2, #8
80024ee: b292 uxth r2, r2
80024f0: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
80024f4: 6878 ldr r0, [r7, #4]
80024f6: f005 fc07 bl 8007d08 <HAL_PCD_ResumeCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
80024fa: 687b ldr r3, [r7, #4]
80024fc: 681b ldr r3, [r3, #0]
80024fe: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
8002502: b29a uxth r2, r3
8002504: 687b ldr r3, [r7, #4]
8002506: 681b ldr r3, [r3, #0]
8002508: f422 5280 bic.w r2, r2, #4096 ; 0x1000
800250c: b292 uxth r2, r2
800250e: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
8002512: 687b ldr r3, [r7, #4]
8002514: 681b ldr r3, [r3, #0]
8002516: 4618 mov r0, r3
8002518: f003 fd2b bl 8005f72 <USB_ReadInterrupts>
800251c: 4603 mov r3, r0
800251e: f403 6300 and.w r3, r3, #2048 ; 0x800
8002522: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8002526: d13d bne.n 80025a4 <HAL_PCD_IRQHandler+0x1b2>
{
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
8002528: 687b ldr r3, [r7, #4]
800252a: 681b ldr r3, [r3, #0]
800252c: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40
8002530: b29a uxth r2, r3
8002532: 687b ldr r3, [r7, #4]
8002534: 681b ldr r3, [r3, #0]
8002536: f042 0208 orr.w r2, r2, #8
800253a: b292 uxth r2, r2
800253c: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
8002540: 687b ldr r3, [r7, #4]
8002542: 681b ldr r3, [r3, #0]
8002544: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
8002548: b29a uxth r2, r3
800254a: 687b ldr r3, [r7, #4]
800254c: 681b ldr r3, [r3, #0]
800254e: f422 6200 bic.w r2, r2, #2048 ; 0x800
8002552: b292 uxth r2, r2
8002554: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
hpcd->Instance->CNTR |= USB_CNTR_LP_MODE;
8002558: 687b ldr r3, [r7, #4]
800255a: 681b ldr r3, [r3, #0]
800255c: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40
8002560: b29a uxth r2, r3
8002562: 687b ldr r3, [r7, #4]
8002564: 681b ldr r3, [r3, #0]
8002566: f042 0204 orr.w r2, r2, #4
800256a: b292 uxth r2, r2
800256c: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/* WA: Clear Wakeup flag if raised with suspend signal */
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
8002570: 687b ldr r3, [r7, #4]
8002572: 681b ldr r3, [r3, #0]
8002574: 4618 mov r0, r3
8002576: f003 fcfc bl 8005f72 <USB_ReadInterrupts>
800257a: 4603 mov r3, r0
800257c: f403 5380 and.w r3, r3, #4096 ; 0x1000
8002580: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002584: d10b bne.n 800259e <HAL_PCD_IRQHandler+0x1ac>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
8002586: 687b ldr r3, [r7, #4]
8002588: 681b ldr r3, [r3, #0]
800258a: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
800258e: b29a uxth r2, r3
8002590: 687b ldr r3, [r7, #4]
8002592: 681b ldr r3, [r3, #0]
8002594: f422 5280 bic.w r2, r2, #4096 ; 0x1000
8002598: b292 uxth r2, r2
800259a: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
800259e: 6878 ldr r0, [r7, #4]
80025a0: f005 fb98 bl 8007cd4 <HAL_PCD_SuspendCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))
80025a4: 687b ldr r3, [r7, #4]
80025a6: 681b ldr r3, [r3, #0]
80025a8: 4618 mov r0, r3
80025aa: f003 fce2 bl 8005f72 <USB_ReadInterrupts>
80025ae: 4603 mov r3, r0
80025b0: f403 7300 and.w r3, r3, #512 ; 0x200
80025b4: f5b3 7f00 cmp.w r3, #512 ; 0x200
80025b8: d10e bne.n 80025d8 <HAL_PCD_IRQHandler+0x1e6>
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
80025ba: 687b ldr r3, [r7, #4]
80025bc: 681b ldr r3, [r3, #0]
80025be: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
80025c2: b29a uxth r2, r3
80025c4: 687b ldr r3, [r7, #4]
80025c6: 681b ldr r3, [r3, #0]
80025c8: f422 7200 bic.w r2, r2, #512 ; 0x200
80025cc: b292 uxth r2, r2
80025ce: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
80025d2: 6878 ldr r0, [r7, #4]
80025d4: f005 fb51 bl 8007c7a <HAL_PCD_SOFCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))
80025d8: 687b ldr r3, [r7, #4]
80025da: 681b ldr r3, [r3, #0]
80025dc: 4618 mov r0, r3
80025de: f003 fcc8 bl 8005f72 <USB_ReadInterrupts>
80025e2: 4603 mov r3, r0
80025e4: f403 7380 and.w r3, r3, #256 ; 0x100
80025e8: f5b3 7f80 cmp.w r3, #256 ; 0x100
80025ec: d10b bne.n 8002606 <HAL_PCD_IRQHandler+0x214>
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
80025ee: 687b ldr r3, [r7, #4]
80025f0: 681b ldr r3, [r3, #0]
80025f2: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
80025f6: b29a uxth r2, r3
80025f8: 687b ldr r3, [r7, #4]
80025fa: 681b ldr r3, [r3, #0]
80025fc: f422 7280 bic.w r2, r2, #256 ; 0x100
8002600: b292 uxth r2, r2
8002602: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
}
}
8002606: bf00 nop
8002608: 3708 adds r7, #8
800260a: 46bd mov sp, r7
800260c: bd80 pop {r7, pc}
0800260e <HAL_PCD_SetAddress>:
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
800260e: b580 push {r7, lr}
8002610: b082 sub sp, #8
8002612: af00 add r7, sp, #0
8002614: 6078 str r0, [r7, #4]
8002616: 460b mov r3, r1
8002618: 70fb strb r3, [r7, #3]
__HAL_LOCK(hpcd);
800261a: 687b ldr r3, [r7, #4]
800261c: f893 3228 ldrb.w r3, [r3, #552] ; 0x228
8002620: 2b01 cmp r3, #1
8002622: d101 bne.n 8002628 <HAL_PCD_SetAddress+0x1a>
8002624: 2302 movs r3, #2
8002626: e013 b.n 8002650 <HAL_PCD_SetAddress+0x42>
8002628: 687b ldr r3, [r7, #4]
800262a: 2201 movs r2, #1
800262c: f883 2228 strb.w r2, [r3, #552] ; 0x228
hpcd->USB_Address = address;
8002630: 687b ldr r3, [r7, #4]
8002632: 78fa ldrb r2, [r7, #3]
8002634: f883 2024 strb.w r2, [r3, #36] ; 0x24
(void)USB_SetDevAddress(hpcd->Instance, address);
8002638: 687b ldr r3, [r7, #4]
800263a: 681b ldr r3, [r3, #0]
800263c: 78fa ldrb r2, [r7, #3]
800263e: 4611 mov r1, r2
8002640: 4618 mov r0, r3
8002642: f003 fc6f bl 8005f24 <USB_SetDevAddress>
__HAL_UNLOCK(hpcd);
8002646: 687b ldr r3, [r7, #4]
8002648: 2200 movs r2, #0
800264a: f883 2228 strb.w r2, [r3, #552] ; 0x228
return HAL_OK;
800264e: 2300 movs r3, #0
}
8002650: 4618 mov r0, r3
8002652: 3708 adds r7, #8
8002654: 46bd mov sp, r7
8002656: bd80 pop {r7, pc}
08002658 <HAL_PCD_EP_Open>:
* @param ep_mps endpoint max packet size
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
{
8002658: b580 push {r7, lr}
800265a: b084 sub sp, #16
800265c: af00 add r7, sp, #0
800265e: 6078 str r0, [r7, #4]
8002660: 4608 mov r0, r1
8002662: 4611 mov r1, r2
8002664: 461a mov r2, r3
8002666: 4603 mov r3, r0
8002668: 70fb strb r3, [r7, #3]
800266a: 460b mov r3, r1
800266c: 803b strh r3, [r7, #0]
800266e: 4613 mov r3, r2
8002670: 70bb strb r3, [r7, #2]
HAL_StatusTypeDef ret = HAL_OK;
8002672: 2300 movs r3, #0
8002674: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8002676: f997 3003 ldrsb.w r3, [r7, #3]
800267a: 2b00 cmp r3, #0
800267c: da0b bge.n 8002696 <HAL_PCD_EP_Open+0x3e>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800267e: 78fb ldrb r3, [r7, #3]
8002680: f003 0307 and.w r3, r3, #7
8002684: 015b lsls r3, r3, #5
8002686: 3328 adds r3, #40 ; 0x28
8002688: 687a ldr r2, [r7, #4]
800268a: 4413 add r3, r2
800268c: 60fb str r3, [r7, #12]
ep->is_in = 1U;
800268e: 68fb ldr r3, [r7, #12]
8002690: 2201 movs r2, #1
8002692: 705a strb r2, [r3, #1]
8002694: e00b b.n 80026ae <HAL_PCD_EP_Open+0x56>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8002696: 78fb ldrb r3, [r7, #3]
8002698: f003 0307 and.w r3, r3, #7
800269c: 015b lsls r3, r3, #5
800269e: f503 7394 add.w r3, r3, #296 ; 0x128
80026a2: 687a ldr r2, [r7, #4]
80026a4: 4413 add r3, r2
80026a6: 60fb str r3, [r7, #12]
ep->is_in = 0U;
80026a8: 68fb ldr r3, [r7, #12]
80026aa: 2200 movs r2, #0
80026ac: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
80026ae: 78fb ldrb r3, [r7, #3]
80026b0: f003 0307 and.w r3, r3, #7
80026b4: b2da uxtb r2, r3
80026b6: 68fb ldr r3, [r7, #12]
80026b8: 701a strb r2, [r3, #0]
ep->maxpacket = ep_mps;
80026ba: 883a ldrh r2, [r7, #0]
80026bc: 68fb ldr r3, [r7, #12]
80026be: 611a str r2, [r3, #16]
ep->type = ep_type;
80026c0: 68fb ldr r3, [r7, #12]
80026c2: 78ba ldrb r2, [r7, #2]
80026c4: 70da strb r2, [r3, #3]
if (ep->is_in != 0U)
80026c6: 68fb ldr r3, [r7, #12]
80026c8: 785b ldrb r3, [r3, #1]
80026ca: 2b00 cmp r3, #0
80026cc: d004 beq.n 80026d8 <HAL_PCD_EP_Open+0x80>
{
/* Assign a Tx FIFO */
ep->tx_fifo_num = ep->num;
80026ce: 68fb ldr r3, [r7, #12]
80026d0: 781b ldrb r3, [r3, #0]
80026d2: b29a uxth r2, r3
80026d4: 68fb ldr r3, [r7, #12]
80026d6: 81da strh r2, [r3, #14]
}
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
80026d8: 78bb ldrb r3, [r7, #2]
80026da: 2b02 cmp r3, #2
80026dc: d102 bne.n 80026e4 <HAL_PCD_EP_Open+0x8c>
{
ep->data_pid_start = 0U;
80026de: 68fb ldr r3, [r7, #12]
80026e0: 2200 movs r2, #0
80026e2: 711a strb r2, [r3, #4]
}
__HAL_LOCK(hpcd);
80026e4: 687b ldr r3, [r7, #4]
80026e6: f893 3228 ldrb.w r3, [r3, #552] ; 0x228
80026ea: 2b01 cmp r3, #1
80026ec: d101 bne.n 80026f2 <HAL_PCD_EP_Open+0x9a>
80026ee: 2302 movs r3, #2
80026f0: e00e b.n 8002710 <HAL_PCD_EP_Open+0xb8>
80026f2: 687b ldr r3, [r7, #4]
80026f4: 2201 movs r2, #1
80026f6: f883 2228 strb.w r2, [r3, #552] ; 0x228
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
80026fa: 687b ldr r3, [r7, #4]
80026fc: 681b ldr r3, [r3, #0]
80026fe: 68f9 ldr r1, [r7, #12]
8002700: 4618 mov r0, r3
8002702: f002 fbfd bl 8004f00 <USB_ActivateEndpoint>
__HAL_UNLOCK(hpcd);
8002706: 687b ldr r3, [r7, #4]
8002708: 2200 movs r2, #0
800270a: f883 2228 strb.w r2, [r3, #552] ; 0x228
return ret;
800270e: 7afb ldrb r3, [r7, #11]
}
8002710: 4618 mov r0, r3
8002712: 3710 adds r7, #16
8002714: 46bd mov sp, r7
8002716: bd80 pop {r7, pc}
08002718 <HAL_PCD_EP_Close>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8002718: b580 push {r7, lr}
800271a: b084 sub sp, #16
800271c: af00 add r7, sp, #0
800271e: 6078 str r0, [r7, #4]
8002720: 460b mov r3, r1
8002722: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
8002724: f997 3003 ldrsb.w r3, [r7, #3]
8002728: 2b00 cmp r3, #0
800272a: da0b bge.n 8002744 <HAL_PCD_EP_Close+0x2c>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
800272c: 78fb ldrb r3, [r7, #3]
800272e: f003 0307 and.w r3, r3, #7
8002732: 015b lsls r3, r3, #5
8002734: 3328 adds r3, #40 ; 0x28
8002736: 687a ldr r2, [r7, #4]
8002738: 4413 add r3, r2
800273a: 60fb str r3, [r7, #12]
ep->is_in = 1U;
800273c: 68fb ldr r3, [r7, #12]
800273e: 2201 movs r2, #1
8002740: 705a strb r2, [r3, #1]
8002742: e00b b.n 800275c <HAL_PCD_EP_Close+0x44>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
8002744: 78fb ldrb r3, [r7, #3]
8002746: f003 0307 and.w r3, r3, #7
800274a: 015b lsls r3, r3, #5
800274c: f503 7394 add.w r3, r3, #296 ; 0x128
8002750: 687a ldr r2, [r7, #4]
8002752: 4413 add r3, r2
8002754: 60fb str r3, [r7, #12]
ep->is_in = 0U;
8002756: 68fb ldr r3, [r7, #12]
8002758: 2200 movs r2, #0
800275a: 705a strb r2, [r3, #1]
}
ep->num = ep_addr & EP_ADDR_MSK;
800275c: 78fb ldrb r3, [r7, #3]
800275e: f003 0307 and.w r3, r3, #7
8002762: b2da uxtb r2, r3
8002764: 68fb ldr r3, [r7, #12]
8002766: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
8002768: 687b ldr r3, [r7, #4]
800276a: f893 3228 ldrb.w r3, [r3, #552] ; 0x228
800276e: 2b01 cmp r3, #1
8002770: d101 bne.n 8002776 <HAL_PCD_EP_Close+0x5e>
8002772: 2302 movs r3, #2
8002774: e00e b.n 8002794 <HAL_PCD_EP_Close+0x7c>
8002776: 687b ldr r3, [r7, #4]
8002778: 2201 movs r2, #1
800277a: f883 2228 strb.w r2, [r3, #552] ; 0x228
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
800277e: 687b ldr r3, [r7, #4]
8002780: 681b ldr r3, [r3, #0]
8002782: 68f9 ldr r1, [r7, #12]
8002784: 4618 mov r0, r3
8002786: f002 fea9 bl 80054dc <USB_DeactivateEndpoint>
__HAL_UNLOCK(hpcd);
800278a: 687b ldr r3, [r7, #4]
800278c: 2200 movs r2, #0
800278e: f883 2228 strb.w r2, [r3, #552] ; 0x228
return HAL_OK;
8002792: 2300 movs r3, #0
}
8002794: 4618 mov r0, r3
8002796: 3710 adds r7, #16
8002798: 46bd mov sp, r7
800279a: bd80 pop {r7, pc}
0800279c <HAL_PCD_EP_Receive>:
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
800279c: b580 push {r7, lr}
800279e: b086 sub sp, #24
80027a0: af00 add r7, sp, #0
80027a2: 60f8 str r0, [r7, #12]
80027a4: 607a str r2, [r7, #4]
80027a6: 603b str r3, [r7, #0]
80027a8: 460b mov r3, r1
80027aa: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
80027ac: 7afb ldrb r3, [r7, #11]
80027ae: f003 0307 and.w r3, r3, #7
80027b2: 015b lsls r3, r3, #5
80027b4: f503 7394 add.w r3, r3, #296 ; 0x128
80027b8: 68fa ldr r2, [r7, #12]
80027ba: 4413 add r3, r2
80027bc: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
80027be: 697b ldr r3, [r7, #20]
80027c0: 687a ldr r2, [r7, #4]
80027c2: 615a str r2, [r3, #20]
ep->xfer_len = len;
80027c4: 697b ldr r3, [r7, #20]
80027c6: 683a ldr r2, [r7, #0]
80027c8: 619a str r2, [r3, #24]
ep->xfer_count = 0U;
80027ca: 697b ldr r3, [r7, #20]
80027cc: 2200 movs r2, #0
80027ce: 61da str r2, [r3, #28]
ep->is_in = 0U;
80027d0: 697b ldr r3, [r7, #20]
80027d2: 2200 movs r2, #0
80027d4: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
80027d6: 7afb ldrb r3, [r7, #11]
80027d8: f003 0307 and.w r3, r3, #7
80027dc: b2da uxtb r2, r3
80027de: 697b ldr r3, [r7, #20]
80027e0: 701a strb r2, [r3, #0]
if ((ep_addr & EP_ADDR_MSK) == 0U)
80027e2: 7afb ldrb r3, [r7, #11]
80027e4: f003 0307 and.w r3, r3, #7
80027e8: 2b00 cmp r3, #0
80027ea: d106 bne.n 80027fa <HAL_PCD_EP_Receive+0x5e>
{
(void)USB_EP0StartXfer(hpcd->Instance, ep);
80027ec: 68fb ldr r3, [r7, #12]
80027ee: 681b ldr r3, [r3, #0]
80027f0: 6979 ldr r1, [r7, #20]
80027f2: 4618 mov r0, r3
80027f4: f003 f808 bl 8005808 <USB_EPStartXfer>
80027f8: e005 b.n 8002806 <HAL_PCD_EP_Receive+0x6a>
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep);
80027fa: 68fb ldr r3, [r7, #12]
80027fc: 681b ldr r3, [r3, #0]
80027fe: 6979 ldr r1, [r7, #20]
8002800: 4618 mov r0, r3
8002802: f003 f801 bl 8005808 <USB_EPStartXfer>
}
return HAL_OK;
8002806: 2300 movs r3, #0
}
8002808: 4618 mov r0, r3
800280a: 3718 adds r7, #24
800280c: 46bd mov sp, r7
800280e: bd80 pop {r7, pc}
08002810 <HAL_PCD_EP_GetRxCount>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
8002810: b480 push {r7}
8002812: b083 sub sp, #12
8002814: af00 add r7, sp, #0
8002816: 6078 str r0, [r7, #4]
8002818: 460b mov r3, r1
800281a: 70fb strb r3, [r7, #3]
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
800281c: 78fb ldrb r3, [r7, #3]
800281e: f003 0307 and.w r3, r3, #7
8002822: 687a ldr r2, [r7, #4]
8002824: 330a adds r3, #10
8002826: 015b lsls r3, r3, #5
8002828: 4413 add r3, r2
800282a: 3304 adds r3, #4
800282c: 681b ldr r3, [r3, #0]
}
800282e: 4618 mov r0, r3
8002830: 370c adds r7, #12
8002832: 46bd mov sp, r7
8002834: bc80 pop {r7}
8002836: 4770 bx lr
08002838 <HAL_PCD_EP_Transmit>:
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
8002838: b580 push {r7, lr}
800283a: b086 sub sp, #24
800283c: af00 add r7, sp, #0
800283e: 60f8 str r0, [r7, #12]
8002840: 607a str r2, [r7, #4]
8002842: 603b str r3, [r7, #0]
8002844: 460b mov r3, r1
8002846: 72fb strb r3, [r7, #11]
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8002848: 7afb ldrb r3, [r7, #11]
800284a: f003 0307 and.w r3, r3, #7
800284e: 015b lsls r3, r3, #5
8002850: 3328 adds r3, #40 ; 0x28
8002852: 68fa ldr r2, [r7, #12]
8002854: 4413 add r3, r2
8002856: 617b str r3, [r7, #20]
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
8002858: 697b ldr r3, [r7, #20]
800285a: 687a ldr r2, [r7, #4]
800285c: 615a str r2, [r3, #20]
ep->xfer_len = len;
800285e: 697b ldr r3, [r7, #20]
8002860: 683a ldr r2, [r7, #0]
8002862: 619a str r2, [r3, #24]
ep->xfer_count = 0U;
8002864: 697b ldr r3, [r7, #20]
8002866: 2200 movs r2, #0
8002868: 61da str r2, [r3, #28]
ep->is_in = 1U;
800286a: 697b ldr r3, [r7, #20]
800286c: 2201 movs r2, #1
800286e: 705a strb r2, [r3, #1]
ep->num = ep_addr & EP_ADDR_MSK;
8002870: 7afb ldrb r3, [r7, #11]
8002872: f003 0307 and.w r3, r3, #7
8002876: b2da uxtb r2, r3
8002878: 697b ldr r3, [r7, #20]
800287a: 701a strb r2, [r3, #0]
if ((ep_addr & EP_ADDR_MSK) == 0U)
800287c: 7afb ldrb r3, [r7, #11]
800287e: f003 0307 and.w r3, r3, #7
8002882: 2b00 cmp r3, #0
8002884: d106 bne.n 8002894 <HAL_PCD_EP_Transmit+0x5c>
{
(void)USB_EP0StartXfer(hpcd->Instance, ep);
8002886: 68fb ldr r3, [r7, #12]
8002888: 681b ldr r3, [r3, #0]
800288a: 6979 ldr r1, [r7, #20]
800288c: 4618 mov r0, r3
800288e: f002 ffbb bl 8005808 <USB_EPStartXfer>
8002892: e005 b.n 80028a0 <HAL_PCD_EP_Transmit+0x68>
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep);
8002894: 68fb ldr r3, [r7, #12]
8002896: 681b ldr r3, [r3, #0]
8002898: 6979 ldr r1, [r7, #20]
800289a: 4618 mov r0, r3
800289c: f002 ffb4 bl 8005808 <USB_EPStartXfer>
}
return HAL_OK;
80028a0: 2300 movs r3, #0
}
80028a2: 4618 mov r0, r3
80028a4: 3718 adds r7, #24
80028a6: 46bd mov sp, r7
80028a8: bd80 pop {r7, pc}
080028aa <HAL_PCD_EP_SetStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
80028aa: b580 push {r7, lr}
80028ac: b084 sub sp, #16
80028ae: af00 add r7, sp, #0
80028b0: 6078 str r0, [r7, #4]
80028b2: 460b mov r3, r1
80028b4: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
80028b6: 78fb ldrb r3, [r7, #3]
80028b8: f003 0207 and.w r2, r3, #7
80028bc: 687b ldr r3, [r7, #4]
80028be: 685b ldr r3, [r3, #4]
80028c0: 429a cmp r2, r3
80028c2: d901 bls.n 80028c8 <HAL_PCD_EP_SetStall+0x1e>
{
return HAL_ERROR;
80028c4: 2301 movs r3, #1
80028c6: e046 b.n 8002956 <HAL_PCD_EP_SetStall+0xac>
}
if ((0x80U & ep_addr) == 0x80U)
80028c8: f997 3003 ldrsb.w r3, [r7, #3]
80028cc: 2b00 cmp r3, #0
80028ce: da0b bge.n 80028e8 <HAL_PCD_EP_SetStall+0x3e>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
80028d0: 78fb ldrb r3, [r7, #3]
80028d2: f003 0307 and.w r3, r3, #7
80028d6: 015b lsls r3, r3, #5
80028d8: 3328 adds r3, #40 ; 0x28
80028da: 687a ldr r2, [r7, #4]
80028dc: 4413 add r3, r2
80028de: 60fb str r3, [r7, #12]
ep->is_in = 1U;
80028e0: 68fb ldr r3, [r7, #12]
80028e2: 2201 movs r2, #1
80028e4: 705a strb r2, [r3, #1]
80028e6: e009 b.n 80028fc <HAL_PCD_EP_SetStall+0x52>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
80028e8: 78fb ldrb r3, [r7, #3]
80028ea: 015b lsls r3, r3, #5
80028ec: f503 7394 add.w r3, r3, #296 ; 0x128
80028f0: 687a ldr r2, [r7, #4]
80028f2: 4413 add r3, r2
80028f4: 60fb str r3, [r7, #12]
ep->is_in = 0U;
80028f6: 68fb ldr r3, [r7, #12]
80028f8: 2200 movs r2, #0
80028fa: 705a strb r2, [r3, #1]
}
ep->is_stall = 1U;
80028fc: 68fb ldr r3, [r7, #12]
80028fe: 2201 movs r2, #1
8002900: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
8002902: 78fb ldrb r3, [r7, #3]
8002904: f003 0307 and.w r3, r3, #7
8002908: b2da uxtb r2, r3
800290a: 68fb ldr r3, [r7, #12]
800290c: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
800290e: 687b ldr r3, [r7, #4]
8002910: f893 3228 ldrb.w r3, [r3, #552] ; 0x228
8002914: 2b01 cmp r3, #1
8002916: d101 bne.n 800291c <HAL_PCD_EP_SetStall+0x72>
8002918: 2302 movs r3, #2
800291a: e01c b.n 8002956 <HAL_PCD_EP_SetStall+0xac>
800291c: 687b ldr r3, [r7, #4]
800291e: 2201 movs r2, #1
8002920: f883 2228 strb.w r2, [r3, #552] ; 0x228
(void)USB_EPSetStall(hpcd->Instance, ep);
8002924: 687b ldr r3, [r7, #4]
8002926: 681b ldr r3, [r3, #0]
8002928: 68f9 ldr r1, [r7, #12]
800292a: 4618 mov r0, r3
800292c: f003 fa24 bl 8005d78 <USB_EPSetStall>
if ((ep_addr & EP_ADDR_MSK) == 0U)
8002930: 78fb ldrb r3, [r7, #3]
8002932: f003 0307 and.w r3, r3, #7
8002936: 2b00 cmp r3, #0
8002938: d108 bne.n 800294c <HAL_PCD_EP_SetStall+0xa2>
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
800293a: 687b ldr r3, [r7, #4]
800293c: 681a ldr r2, [r3, #0]
800293e: 687b ldr r3, [r7, #4]
8002940: f503 730c add.w r3, r3, #560 ; 0x230
8002944: 4619 mov r1, r3
8002946: 4610 mov r0, r2
8002948: f003 fb22 bl 8005f90 <USB_EP0_OutStart>
}
__HAL_UNLOCK(hpcd);
800294c: 687b ldr r3, [r7, #4]
800294e: 2200 movs r2, #0
8002950: f883 2228 strb.w r2, [r3, #552] ; 0x228
return HAL_OK;
8002954: 2300 movs r3, #0
}
8002956: 4618 mov r0, r3
8002958: 3710 adds r7, #16
800295a: 46bd mov sp, r7
800295c: bd80 pop {r7, pc}
0800295e <HAL_PCD_EP_ClrStall>:
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
800295e: b580 push {r7, lr}
8002960: b084 sub sp, #16
8002962: af00 add r7, sp, #0
8002964: 6078 str r0, [r7, #4]
8002966: 460b mov r3, r1
8002968: 70fb strb r3, [r7, #3]
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
800296a: 78fb ldrb r3, [r7, #3]
800296c: f003 020f and.w r2, r3, #15
8002970: 687b ldr r3, [r7, #4]
8002972: 685b ldr r3, [r3, #4]
8002974: 429a cmp r2, r3
8002976: d901 bls.n 800297c <HAL_PCD_EP_ClrStall+0x1e>
{
return HAL_ERROR;
8002978: 2301 movs r3, #1
800297a: e03a b.n 80029f2 <HAL_PCD_EP_ClrStall+0x94>
}
if ((0x80U & ep_addr) == 0x80U)
800297c: f997 3003 ldrsb.w r3, [r7, #3]
8002980: 2b00 cmp r3, #0
8002982: da0b bge.n 800299c <HAL_PCD_EP_ClrStall+0x3e>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8002984: 78fb ldrb r3, [r7, #3]
8002986: f003 0307 and.w r3, r3, #7
800298a: 015b lsls r3, r3, #5
800298c: 3328 adds r3, #40 ; 0x28
800298e: 687a ldr r2, [r7, #4]
8002990: 4413 add r3, r2
8002992: 60fb str r3, [r7, #12]
ep->is_in = 1U;
8002994: 68fb ldr r3, [r7, #12]
8002996: 2201 movs r2, #1
8002998: 705a strb r2, [r3, #1]
800299a: e00b b.n 80029b4 <HAL_PCD_EP_ClrStall+0x56>
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
800299c: 78fb ldrb r3, [r7, #3]
800299e: f003 0307 and.w r3, r3, #7
80029a2: 015b lsls r3, r3, #5
80029a4: f503 7394 add.w r3, r3, #296 ; 0x128
80029a8: 687a ldr r2, [r7, #4]
80029aa: 4413 add r3, r2
80029ac: 60fb str r3, [r7, #12]
ep->is_in = 0U;
80029ae: 68fb ldr r3, [r7, #12]
80029b0: 2200 movs r2, #0
80029b2: 705a strb r2, [r3, #1]
}
ep->is_stall = 0U;
80029b4: 68fb ldr r3, [r7, #12]
80029b6: 2200 movs r2, #0
80029b8: 709a strb r2, [r3, #2]
ep->num = ep_addr & EP_ADDR_MSK;
80029ba: 78fb ldrb r3, [r7, #3]
80029bc: f003 0307 and.w r3, r3, #7
80029c0: b2da uxtb r2, r3
80029c2: 68fb ldr r3, [r7, #12]
80029c4: 701a strb r2, [r3, #0]
__HAL_LOCK(hpcd);
80029c6: 687b ldr r3, [r7, #4]
80029c8: f893 3228 ldrb.w r3, [r3, #552] ; 0x228
80029cc: 2b01 cmp r3, #1
80029ce: d101 bne.n 80029d4 <HAL_PCD_EP_ClrStall+0x76>
80029d0: 2302 movs r3, #2
80029d2: e00e b.n 80029f2 <HAL_PCD_EP_ClrStall+0x94>
80029d4: 687b ldr r3, [r7, #4]
80029d6: 2201 movs r2, #1
80029d8: f883 2228 strb.w r2, [r3, #552] ; 0x228
(void)USB_EPClearStall(hpcd->Instance, ep);
80029dc: 687b ldr r3, [r7, #4]
80029de: 681b ldr r3, [r3, #0]
80029e0: 68f9 ldr r1, [r7, #12]
80029e2: 4618 mov r0, r3
80029e4: f003 fa0a bl 8005dfc <USB_EPClearStall>
__HAL_UNLOCK(hpcd);
80029e8: 687b ldr r3, [r7, #4]
80029ea: 2200 movs r2, #0
80029ec: f883 2228 strb.w r2, [r3, #552] ; 0x228
return HAL_OK;
80029f0: 2300 movs r3, #0
}
80029f2: 4618 mov r0, r3
80029f4: 3710 adds r7, #16
80029f6: 46bd mov sp, r7
80029f8: bd80 pop {r7, pc}
...
080029fc <PCD_EP_ISR_Handler>:
* @brief This function handles PCD Endpoint interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
80029fc: b590 push {r4, r7, lr}
80029fe: b089 sub sp, #36 ; 0x24
8002a00: af00 add r7, sp, #0
8002a02: 6078 str r0, [r7, #4]
uint16_t wIstr;
uint16_t wEPVal;
uint8_t epindex;
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8002a04: e282 b.n 8002f0c <PCD_EP_ISR_Handler+0x510>
{
wIstr = hpcd->Instance->ISTR;
8002a06: 687b ldr r3, [r7, #4]
8002a08: 681b ldr r3, [r3, #0]
8002a0a: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
8002a0e: 82fb strh r3, [r7, #22]
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
8002a10: 8afb ldrh r3, [r7, #22]
8002a12: b2db uxtb r3, r3
8002a14: f003 030f and.w r3, r3, #15
8002a18: 757b strb r3, [r7, #21]
if (epindex == 0U)
8002a1a: 7d7b ldrb r3, [r7, #21]
8002a1c: 2b00 cmp r3, #0
8002a1e: f040 8142 bne.w 8002ca6 <PCD_EP_ISR_Handler+0x2aa>
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
8002a22: 8afb ldrh r3, [r7, #22]
8002a24: f003 0310 and.w r3, r3, #16
8002a28: 2b00 cmp r3, #0
8002a2a: d151 bne.n 8002ad0 <PCD_EP_ISR_Handler+0xd4>
{
/* DIR = 0 */
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8002a2c: 687b ldr r3, [r7, #4]
8002a2e: 681b ldr r3, [r3, #0]
8002a30: 881b ldrh r3, [r3, #0]
8002a32: b29b uxth r3, r3
8002a34: f423 43e1 bic.w r3, r3, #28800 ; 0x7080
8002a38: f023 0370 bic.w r3, r3, #112 ; 0x70
8002a3c: b29c uxth r4, r3
8002a3e: 687b ldr r3, [r7, #4]
8002a40: 681a ldr r2, [r3, #0]
8002a42: ea6f 4344 mvn.w r3, r4, lsl #17
8002a46: ea6f 4353 mvn.w r3, r3, lsr #17
8002a4a: b29b uxth r3, r3
8002a4c: 8013 strh r3, [r2, #0]
ep = &hpcd->IN_ep[0];
8002a4e: 687b ldr r3, [r7, #4]
8002a50: 3328 adds r3, #40 ; 0x28
8002a52: 60fb str r3, [r7, #12]
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
8002a54: 687b ldr r3, [r7, #4]
8002a56: 681b ldr r3, [r3, #0]
8002a58: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8002a5c: b29b uxth r3, r3
8002a5e: 461a mov r2, r3
8002a60: 68fb ldr r3, [r7, #12]
8002a62: 781b ldrb r3, [r3, #0]
8002a64: 00db lsls r3, r3, #3
8002a66: 4413 add r3, r2
8002a68: 3302 adds r3, #2
8002a6a: 005b lsls r3, r3, #1
8002a6c: 687a ldr r2, [r7, #4]
8002a6e: 6812 ldr r2, [r2, #0]
8002a70: 4413 add r3, r2
8002a72: f503 6380 add.w r3, r3, #1024 ; 0x400
8002a76: 881b ldrh r3, [r3, #0]
8002a78: f3c3 0209 ubfx r2, r3, #0, #10
8002a7c: 68fb ldr r3, [r7, #12]
8002a7e: 61da str r2, [r3, #28]
ep->xfer_buff += ep->xfer_count;
8002a80: 68fb ldr r3, [r7, #12]
8002a82: 695a ldr r2, [r3, #20]
8002a84: 68fb ldr r3, [r7, #12]
8002a86: 69db ldr r3, [r3, #28]
8002a88: 441a add r2, r3
8002a8a: 68fb ldr r3, [r7, #12]
8002a8c: 615a str r2, [r3, #20]
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, 0U);
#else
HAL_PCD_DataInStageCallback(hpcd, 0U);
8002a8e: 2100 movs r1, #0
8002a90: 6878 ldr r0, [r7, #4]
8002a92: f005 f8db bl 8007c4c <HAL_PCD_DataInStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
8002a96: 687b ldr r3, [r7, #4]
8002a98: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
8002a9c: b2db uxtb r3, r3
8002a9e: 2b00 cmp r3, #0
8002aa0: f000 8234 beq.w 8002f0c <PCD_EP_ISR_Handler+0x510>
8002aa4: 68fb ldr r3, [r7, #12]
8002aa6: 699b ldr r3, [r3, #24]
8002aa8: 2b00 cmp r3, #0
8002aaa: f040 822f bne.w 8002f0c <PCD_EP_ISR_Handler+0x510>
{
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
8002aae: 687b ldr r3, [r7, #4]
8002ab0: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
8002ab4: b2db uxtb r3, r3
8002ab6: f063 037f orn r3, r3, #127 ; 0x7f
8002aba: b2da uxtb r2, r3
8002abc: 687b ldr r3, [r7, #4]
8002abe: 681b ldr r3, [r3, #0]
8002ac0: b292 uxth r2, r2
8002ac2: f8a3 204c strh.w r2, [r3, #76] ; 0x4c
hpcd->USB_Address = 0U;
8002ac6: 687b ldr r3, [r7, #4]
8002ac8: 2200 movs r2, #0
8002aca: f883 2024 strb.w r2, [r3, #36] ; 0x24
8002ace: e21d b.n 8002f0c <PCD_EP_ISR_Handler+0x510>
{
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
8002ad0: 687b ldr r3, [r7, #4]
8002ad2: f503 7394 add.w r3, r3, #296 ; 0x128
8002ad6: 60fb str r3, [r7, #12]
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
8002ad8: 687b ldr r3, [r7, #4]
8002ada: 681b ldr r3, [r3, #0]
8002adc: 881b ldrh r3, [r3, #0]
8002ade: 827b strh r3, [r7, #18]
if ((wEPVal & USB_EP_SETUP) != 0U)
8002ae0: 8a7b ldrh r3, [r7, #18]
8002ae2: f403 6300 and.w r3, r3, #2048 ; 0x800
8002ae6: 2b00 cmp r3, #0
8002ae8: d033 beq.n 8002b52 <PCD_EP_ISR_Handler+0x156>
{
/* Get SETUP Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
8002aea: 687b ldr r3, [r7, #4]
8002aec: 681b ldr r3, [r3, #0]
8002aee: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8002af2: b29b uxth r3, r3
8002af4: 461a mov r2, r3
8002af6: 68fb ldr r3, [r7, #12]
8002af8: 781b ldrb r3, [r3, #0]
8002afa: 00db lsls r3, r3, #3
8002afc: 4413 add r3, r2
8002afe: 3306 adds r3, #6
8002b00: 005b lsls r3, r3, #1
8002b02: 687a ldr r2, [r7, #4]
8002b04: 6812 ldr r2, [r2, #0]
8002b06: 4413 add r3, r2
8002b08: f503 6380 add.w r3, r3, #1024 ; 0x400
8002b0c: 881b ldrh r3, [r3, #0]
8002b0e: f3c3 0209 ubfx r2, r3, #0, #10
8002b12: 68fb ldr r3, [r7, #12]
8002b14: 61da str r2, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
8002b16: 687b ldr r3, [r7, #4]
8002b18: 6818 ldr r0, [r3, #0]
8002b1a: 687b ldr r3, [r7, #4]
8002b1c: f503 710c add.w r1, r3, #560 ; 0x230
8002b20: 68fb ldr r3, [r7, #12]
8002b22: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
8002b24: 68fb ldr r3, [r7, #12]
8002b26: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
8002b28: b29b uxth r3, r3
8002b2a: f003 fa80 bl 800602e <USB_ReadPMA>
/* SETUP bit kept frozen while CTR_RX = 1*/
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8002b2e: 687b ldr r3, [r7, #4]
8002b30: 681b ldr r3, [r3, #0]
8002b32: 881b ldrh r3, [r3, #0]
8002b34: b29a uxth r2, r3
8002b36: f640 738f movw r3, #3983 ; 0xf8f
8002b3a: 4013 ands r3, r2
8002b3c: b29c uxth r4, r3
8002b3e: 687b ldr r3, [r7, #4]
8002b40: 681b ldr r3, [r3, #0]
8002b42: f044 0280 orr.w r2, r4, #128 ; 0x80
8002b46: b292 uxth r2, r2
8002b48: 801a strh r2, [r3, #0]
/* Process SETUP Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
8002b4a: 6878 ldr r0, [r7, #4]
8002b4c: f005 f854 bl 8007bf8 <HAL_PCD_SetupStageCallback>
8002b50: e1dc b.n 8002f0c <PCD_EP_ISR_Handler+0x510>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
8002b52: f9b7 3012 ldrsh.w r3, [r7, #18]
8002b56: 2b00 cmp r3, #0
8002b58: f280 81d8 bge.w 8002f0c <PCD_EP_ISR_Handler+0x510>
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
8002b5c: 687b ldr r3, [r7, #4]
8002b5e: 681b ldr r3, [r3, #0]
8002b60: 881b ldrh r3, [r3, #0]
8002b62: b29a uxth r2, r3
8002b64: f640 738f movw r3, #3983 ; 0xf8f
8002b68: 4013 ands r3, r2
8002b6a: b29c uxth r4, r3
8002b6c: 687b ldr r3, [r7, #4]
8002b6e: 681b ldr r3, [r3, #0]
8002b70: f044 0280 orr.w r2, r4, #128 ; 0x80
8002b74: b292 uxth r2, r2
8002b76: 801a strh r2, [r3, #0]
/* Get Control Data OUT Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
8002b78: 687b ldr r3, [r7, #4]
8002b7a: 681b ldr r3, [r3, #0]
8002b7c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8002b80: b29b uxth r3, r3
8002b82: 461a mov r2, r3
8002b84: 68fb ldr r3, [r7, #12]
8002b86: 781b ldrb r3, [r3, #0]
8002b88: 00db lsls r3, r3, #3
8002b8a: 4413 add r3, r2
8002b8c: 3306 adds r3, #6
8002b8e: 005b lsls r3, r3, #1
8002b90: 687a ldr r2, [r7, #4]
8002b92: 6812 ldr r2, [r2, #0]
8002b94: 4413 add r3, r2
8002b96: f503 6380 add.w r3, r3, #1024 ; 0x400
8002b9a: 881b ldrh r3, [r3, #0]
8002b9c: f3c3 0209 ubfx r2, r3, #0, #10
8002ba0: 68fb ldr r3, [r7, #12]
8002ba2: 61da str r2, [r3, #28]
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
8002ba4: 68fb ldr r3, [r7, #12]
8002ba6: 69db ldr r3, [r3, #28]
8002ba8: 2b00 cmp r3, #0
8002baa: d019 beq.n 8002be0 <PCD_EP_ISR_Handler+0x1e4>
8002bac: 68fb ldr r3, [r7, #12]
8002bae: 695b ldr r3, [r3, #20]
8002bb0: 2b00 cmp r3, #0
8002bb2: d015 beq.n 8002be0 <PCD_EP_ISR_Handler+0x1e4>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
8002bb4: 687b ldr r3, [r7, #4]
8002bb6: 6818 ldr r0, [r3, #0]
8002bb8: 68fb ldr r3, [r7, #12]
8002bba: 6959 ldr r1, [r3, #20]
8002bbc: 68fb ldr r3, [r7, #12]
8002bbe: 88da ldrh r2, [r3, #6]
ep->pmaadress, (uint16_t)ep->xfer_count);
8002bc0: 68fb ldr r3, [r7, #12]
8002bc2: 69db ldr r3, [r3, #28]
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
8002bc4: b29b uxth r3, r3
8002bc6: f003 fa32 bl 800602e <USB_ReadPMA>
ep->xfer_buff += ep->xfer_count;
8002bca: 68fb ldr r3, [r7, #12]
8002bcc: 695a ldr r2, [r3, #20]
8002bce: 68fb ldr r3, [r7, #12]
8002bd0: 69db ldr r3, [r3, #28]
8002bd2: 441a add r2, r3
8002bd4: 68fb ldr r3, [r7, #12]
8002bd6: 615a str r2, [r3, #20]
/* Process Control Data OUT Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U);
#else
HAL_PCD_DataOutStageCallback(hpcd, 0U);
8002bd8: 2100 movs r1, #0
8002bda: 6878 ldr r0, [r7, #4]
8002bdc: f005 f81e bl 8007c1c <HAL_PCD_DataOutStageCallback>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
8002be0: 687b ldr r3, [r7, #4]
8002be2: 681b ldr r3, [r3, #0]
8002be4: 461c mov r4, r3
8002be6: 687b ldr r3, [r7, #4]
8002be8: 681b ldr r3, [r3, #0]
8002bea: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8002bee: b29b uxth r3, r3
8002bf0: 441c add r4, r3
8002bf2: f204 430c addw r3, r4, #1036 ; 0x40c
8002bf6: 461c mov r4, r3
8002bf8: 68fb ldr r3, [r7, #12]
8002bfa: 691b ldr r3, [r3, #16]
8002bfc: 2b00 cmp r3, #0
8002bfe: d10e bne.n 8002c1e <PCD_EP_ISR_Handler+0x222>
8002c00: 8823 ldrh r3, [r4, #0]
8002c02: b29b uxth r3, r3
8002c04: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
8002c08: b29b uxth r3, r3
8002c0a: 8023 strh r3, [r4, #0]
8002c0c: 8823 ldrh r3, [r4, #0]
8002c0e: b29b uxth r3, r3
8002c10: ea6f 4343 mvn.w r3, r3, lsl #17
8002c14: ea6f 4353 mvn.w r3, r3, lsr #17
8002c18: b29b uxth r3, r3
8002c1a: 8023 strh r3, [r4, #0]
8002c1c: e02d b.n 8002c7a <PCD_EP_ISR_Handler+0x27e>
8002c1e: 68fb ldr r3, [r7, #12]
8002c20: 691b ldr r3, [r3, #16]
8002c22: 2b3e cmp r3, #62 ; 0x3e
8002c24: d812 bhi.n 8002c4c <PCD_EP_ISR_Handler+0x250>
8002c26: 68fb ldr r3, [r7, #12]
8002c28: 691b ldr r3, [r3, #16]
8002c2a: 085b lsrs r3, r3, #1
8002c2c: 61bb str r3, [r7, #24]
8002c2e: 68fb ldr r3, [r7, #12]
8002c30: 691b ldr r3, [r3, #16]
8002c32: f003 0301 and.w r3, r3, #1
8002c36: 2b00 cmp r3, #0
8002c38: d002 beq.n 8002c40 <PCD_EP_ISR_Handler+0x244>
8002c3a: 69bb ldr r3, [r7, #24]
8002c3c: 3301 adds r3, #1
8002c3e: 61bb str r3, [r7, #24]
8002c40: 69bb ldr r3, [r7, #24]
8002c42: b29b uxth r3, r3
8002c44: 029b lsls r3, r3, #10
8002c46: b29b uxth r3, r3
8002c48: 8023 strh r3, [r4, #0]
8002c4a: e016 b.n 8002c7a <PCD_EP_ISR_Handler+0x27e>
8002c4c: 68fb ldr r3, [r7, #12]
8002c4e: 691b ldr r3, [r3, #16]
8002c50: 095b lsrs r3, r3, #5
8002c52: 61bb str r3, [r7, #24]
8002c54: 68fb ldr r3, [r7, #12]
8002c56: 691b ldr r3, [r3, #16]
8002c58: f003 031f and.w r3, r3, #31
8002c5c: 2b00 cmp r3, #0
8002c5e: d102 bne.n 8002c66 <PCD_EP_ISR_Handler+0x26a>
8002c60: 69bb ldr r3, [r7, #24]
8002c62: 3b01 subs r3, #1
8002c64: 61bb str r3, [r7, #24]
8002c66: 69bb ldr r3, [r7, #24]
8002c68: b29b uxth r3, r3
8002c6a: 029b lsls r3, r3, #10
8002c6c: b29b uxth r3, r3
8002c6e: ea6f 4343 mvn.w r3, r3, lsl #17
8002c72: ea6f 4353 mvn.w r3, r3, lsr #17
8002c76: b29b uxth r3, r3
8002c78: 8023 strh r3, [r4, #0]
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
8002c7a: 687b ldr r3, [r7, #4]
8002c7c: 681b ldr r3, [r3, #0]
8002c7e: 881b ldrh r3, [r3, #0]
8002c80: b29b uxth r3, r3
8002c82: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8002c86: f023 0370 bic.w r3, r3, #112 ; 0x70
8002c8a: b29c uxth r4, r3
8002c8c: f484 5380 eor.w r3, r4, #4096 ; 0x1000
8002c90: b29c uxth r4, r3
8002c92: f484 5300 eor.w r3, r4, #8192 ; 0x2000
8002c96: b29c uxth r4, r3
8002c98: 687b ldr r3, [r7, #4]
8002c9a: 681a ldr r2, [r3, #0]
8002c9c: 4ba2 ldr r3, [pc, #648] ; (8002f28 <PCD_EP_ISR_Handler+0x52c>)
8002c9e: 4323 orrs r3, r4
8002ca0: b29b uxth r3, r3
8002ca2: 8013 strh r3, [r2, #0]
8002ca4: e132 b.n 8002f0c <PCD_EP_ISR_Handler+0x510>
else
{
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
8002ca6: 687b ldr r3, [r7, #4]
8002ca8: 681b ldr r3, [r3, #0]
8002caa: 461a mov r2, r3
8002cac: 7d7b ldrb r3, [r7, #21]
8002cae: 009b lsls r3, r3, #2
8002cb0: 4413 add r3, r2
8002cb2: 881b ldrh r3, [r3, #0]
8002cb4: 827b strh r3, [r7, #18]
if ((wEPVal & USB_EP_CTR_RX) != 0U)
8002cb6: f9b7 3012 ldrsh.w r3, [r7, #18]
8002cba: 2b00 cmp r3, #0
8002cbc: f280 80d1 bge.w 8002e62 <PCD_EP_ISR_Handler+0x466>
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
8002cc0: 687b ldr r3, [r7, #4]
8002cc2: 681b ldr r3, [r3, #0]
8002cc4: 461a mov r2, r3
8002cc6: 7d7b ldrb r3, [r7, #21]
8002cc8: 009b lsls r3, r3, #2
8002cca: 4413 add r3, r2
8002ccc: 881b ldrh r3, [r3, #0]
8002cce: b29a uxth r2, r3
8002cd0: f640 738f movw r3, #3983 ; 0xf8f
8002cd4: 4013 ands r3, r2
8002cd6: b29c uxth r4, r3
8002cd8: 687b ldr r3, [r7, #4]
8002cda: 681b ldr r3, [r3, #0]
8002cdc: 461a mov r2, r3
8002cde: 7d7b ldrb r3, [r7, #21]
8002ce0: 009b lsls r3, r3, #2
8002ce2: 4413 add r3, r2
8002ce4: f044 0280 orr.w r2, r4, #128 ; 0x80
8002ce8: b292 uxth r2, r2
8002cea: 801a strh r2, [r3, #0]
ep = &hpcd->OUT_ep[epindex];
8002cec: 7d7b ldrb r3, [r7, #21]
8002cee: 015b lsls r3, r3, #5
8002cf0: f503 7394 add.w r3, r3, #296 ; 0x128
8002cf4: 687a ldr r2, [r7, #4]
8002cf6: 4413 add r3, r2
8002cf8: 60fb str r3, [r7, #12]
/* OUT double Buffering*/
if (ep->doublebuffer == 0U)
8002cfa: 68fb ldr r3, [r7, #12]
8002cfc: 7b1b ldrb r3, [r3, #12]
8002cfe: 2b00 cmp r3, #0
8002d00: d121 bne.n 8002d46 <PCD_EP_ISR_Handler+0x34a>
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
8002d02: 687b ldr r3, [r7, #4]
8002d04: 681b ldr r3, [r3, #0]
8002d06: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8002d0a: b29b uxth r3, r3
8002d0c: 461a mov r2, r3
8002d0e: 68fb ldr r3, [r7, #12]
8002d10: 781b ldrb r3, [r3, #0]
8002d12: 00db lsls r3, r3, #3
8002d14: 4413 add r3, r2
8002d16: 3306 adds r3, #6
8002d18: 005b lsls r3, r3, #1
8002d1a: 687a ldr r2, [r7, #4]
8002d1c: 6812 ldr r2, [r2, #0]
8002d1e: 4413 add r3, r2
8002d20: f503 6380 add.w r3, r3, #1024 ; 0x400
8002d24: 881b ldrh r3, [r3, #0]
8002d26: f3c3 0309 ubfx r3, r3, #0, #10
8002d2a: 83fb strh r3, [r7, #30]
if (count != 0U)
8002d2c: 8bfb ldrh r3, [r7, #30]
8002d2e: 2b00 cmp r3, #0
8002d30: d072 beq.n 8002e18 <PCD_EP_ISR_Handler+0x41c>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
8002d32: 687b ldr r3, [r7, #4]
8002d34: 6818 ldr r0, [r3, #0]
8002d36: 68fb ldr r3, [r7, #12]
8002d38: 6959 ldr r1, [r3, #20]
8002d3a: 68fb ldr r3, [r7, #12]
8002d3c: 88da ldrh r2, [r3, #6]
8002d3e: 8bfb ldrh r3, [r7, #30]
8002d40: f003 f975 bl 800602e <USB_ReadPMA>
8002d44: e068 b.n 8002e18 <PCD_EP_ISR_Handler+0x41c>
}
}
else
{
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
8002d46: 687b ldr r3, [r7, #4]
8002d48: 681b ldr r3, [r3, #0]
8002d4a: 461a mov r2, r3
8002d4c: 68fb ldr r3, [r7, #12]
8002d4e: 781b ldrb r3, [r3, #0]
8002d50: 009b lsls r3, r3, #2
8002d52: 4413 add r3, r2
8002d54: 881b ldrh r3, [r3, #0]
8002d56: b29b uxth r3, r3
8002d58: f403 4380 and.w r3, r3, #16384 ; 0x4000
8002d5c: 2b00 cmp r3, #0
8002d5e: d021 beq.n 8002da4 <PCD_EP_ISR_Handler+0x3a8>
{
/*read from endpoint BUF0Addr buffer*/
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
8002d60: 687b ldr r3, [r7, #4]
8002d62: 681b ldr r3, [r3, #0]
8002d64: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8002d68: b29b uxth r3, r3
8002d6a: 461a mov r2, r3
8002d6c: 68fb ldr r3, [r7, #12]
8002d6e: 781b ldrb r3, [r3, #0]
8002d70: 00db lsls r3, r3, #3
8002d72: 4413 add r3, r2
8002d74: 3302 adds r3, #2
8002d76: 005b lsls r3, r3, #1
8002d78: 687a ldr r2, [r7, #4]
8002d7a: 6812 ldr r2, [r2, #0]
8002d7c: 4413 add r3, r2
8002d7e: f503 6380 add.w r3, r3, #1024 ; 0x400
8002d82: 881b ldrh r3, [r3, #0]
8002d84: f3c3 0309 ubfx r3, r3, #0, #10
8002d88: 83fb strh r3, [r7, #30]
if (count != 0U)
8002d8a: 8bfb ldrh r3, [r7, #30]
8002d8c: 2b00 cmp r3, #0
8002d8e: d02a beq.n 8002de6 <PCD_EP_ISR_Handler+0x3ea>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
8002d90: 687b ldr r3, [r7, #4]
8002d92: 6818 ldr r0, [r3, #0]
8002d94: 68fb ldr r3, [r7, #12]
8002d96: 6959 ldr r1, [r3, #20]
8002d98: 68fb ldr r3, [r7, #12]
8002d9a: 891a ldrh r2, [r3, #8]
8002d9c: 8bfb ldrh r3, [r7, #30]
8002d9e: f003 f946 bl 800602e <USB_ReadPMA>
8002da2: e020 b.n 8002de6 <PCD_EP_ISR_Handler+0x3ea>
}
}
else
{
/*read from endpoint BUF1Addr buffer*/
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
8002da4: 687b ldr r3, [r7, #4]
8002da6: 681b ldr r3, [r3, #0]
8002da8: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8002dac: b29b uxth r3, r3
8002dae: 461a mov r2, r3
8002db0: 68fb ldr r3, [r7, #12]
8002db2: 781b ldrb r3, [r3, #0]
8002db4: 00db lsls r3, r3, #3
8002db6: 4413 add r3, r2
8002db8: 3306 adds r3, #6
8002dba: 005b lsls r3, r3, #1
8002dbc: 687a ldr r2, [r7, #4]
8002dbe: 6812 ldr r2, [r2, #0]
8002dc0: 4413 add r3, r2
8002dc2: f503 6380 add.w r3, r3, #1024 ; 0x400
8002dc6: 881b ldrh r3, [r3, #0]
8002dc8: f3c3 0309 ubfx r3, r3, #0, #10
8002dcc: 83fb strh r3, [r7, #30]
if (count != 0U)
8002dce: 8bfb ldrh r3, [r7, #30]
8002dd0: 2b00 cmp r3, #0
8002dd2: d008 beq.n 8002de6 <PCD_EP_ISR_Handler+0x3ea>
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
8002dd4: 687b ldr r3, [r7, #4]
8002dd6: 6818 ldr r0, [r3, #0]
8002dd8: 68fb ldr r3, [r7, #12]
8002dda: 6959 ldr r1, [r3, #20]
8002ddc: 68fb ldr r3, [r7, #12]
8002dde: 895a ldrh r2, [r3, #10]
8002de0: 8bfb ldrh r3, [r7, #30]
8002de2: f003 f924 bl 800602e <USB_ReadPMA>
}
}
/* free EP OUT Buffer */
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
8002de6: 687b ldr r3, [r7, #4]
8002de8: 681b ldr r3, [r3, #0]
8002dea: 461a mov r2, r3
8002dec: 68fb ldr r3, [r7, #12]
8002dee: 781b ldrb r3, [r3, #0]
8002df0: 009b lsls r3, r3, #2
8002df2: 4413 add r3, r2
8002df4: 881b ldrh r3, [r3, #0]
8002df6: b29b uxth r3, r3
8002df8: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8002dfc: f023 0370 bic.w r3, r3, #112 ; 0x70
8002e00: b29c uxth r4, r3
8002e02: 687b ldr r3, [r7, #4]
8002e04: 681b ldr r3, [r3, #0]
8002e06: 461a mov r2, r3
8002e08: 68fb ldr r3, [r7, #12]
8002e0a: 781b ldrb r3, [r3, #0]
8002e0c: 009b lsls r3, r3, #2
8002e0e: 441a add r2, r3
8002e10: 4b46 ldr r3, [pc, #280] ; (8002f2c <PCD_EP_ISR_Handler+0x530>)
8002e12: 4323 orrs r3, r4
8002e14: b29b uxth r3, r3
8002e16: 8013 strh r3, [r2, #0]
}
/*multi-packet on the NON control OUT endpoint*/
ep->xfer_count += count;
8002e18: 68fb ldr r3, [r7, #12]
8002e1a: 69da ldr r2, [r3, #28]
8002e1c: 8bfb ldrh r3, [r7, #30]
8002e1e: 441a add r2, r3
8002e20: 68fb ldr r3, [r7, #12]
8002e22: 61da str r2, [r3, #28]
ep->xfer_buff += count;
8002e24: 68fb ldr r3, [r7, #12]
8002e26: 695a ldr r2, [r3, #20]
8002e28: 8bfb ldrh r3, [r7, #30]
8002e2a: 441a add r2, r3
8002e2c: 68fb ldr r3, [r7, #12]
8002e2e: 615a str r2, [r3, #20]
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
8002e30: 68fb ldr r3, [r7, #12]
8002e32: 699b ldr r3, [r3, #24]
8002e34: 2b00 cmp r3, #0
8002e36: d004 beq.n 8002e42 <PCD_EP_ISR_Handler+0x446>
8002e38: 8bfa ldrh r2, [r7, #30]
8002e3a: 68fb ldr r3, [r7, #12]
8002e3c: 691b ldr r3, [r3, #16]
8002e3e: 429a cmp r2, r3
8002e40: d206 bcs.n 8002e50 <PCD_EP_ISR_Handler+0x454>
{
/* RX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
8002e42: 68fb ldr r3, [r7, #12]
8002e44: 781b ldrb r3, [r3, #0]
8002e46: 4619 mov r1, r3
8002e48: 6878 ldr r0, [r7, #4]
8002e4a: f004 fee7 bl 8007c1c <HAL_PCD_DataOutStageCallback>
8002e4e: e008 b.n 8002e62 <PCD_EP_ISR_Handler+0x466>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
(void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
8002e50: 68fb ldr r3, [r7, #12]
8002e52: 7819 ldrb r1, [r3, #0]
8002e54: 68fb ldr r3, [r7, #12]
8002e56: 695a ldr r2, [r3, #20]
8002e58: 68fb ldr r3, [r7, #12]
8002e5a: 699b ldr r3, [r3, #24]
8002e5c: 6878 ldr r0, [r7, #4]
8002e5e: f7ff fc9d bl 800279c <HAL_PCD_EP_Receive>
}
} /* if((wEPVal & EP_CTR_RX) */
if ((wEPVal & USB_EP_CTR_TX) != 0U)
8002e62: 8a7b ldrh r3, [r7, #18]
8002e64: f003 0380 and.w r3, r3, #128 ; 0x80
8002e68: 2b00 cmp r3, #0
8002e6a: d04f beq.n 8002f0c <PCD_EP_ISR_Handler+0x510>
{
ep = &hpcd->IN_ep[epindex];
8002e6c: 7d7b ldrb r3, [r7, #21]
8002e6e: 015b lsls r3, r3, #5
8002e70: 3328 adds r3, #40 ; 0x28
8002e72: 687a ldr r2, [r7, #4]
8002e74: 4413 add r3, r2
8002e76: 60fb str r3, [r7, #12]
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
8002e78: 687b ldr r3, [r7, #4]
8002e7a: 681b ldr r3, [r3, #0]
8002e7c: 461a mov r2, r3
8002e7e: 7d7b ldrb r3, [r7, #21]
8002e80: 009b lsls r3, r3, #2
8002e82: 4413 add r3, r2
8002e84: 881b ldrh r3, [r3, #0]
8002e86: b29b uxth r3, r3
8002e88: f423 43e1 bic.w r3, r3, #28800 ; 0x7080
8002e8c: f023 0370 bic.w r3, r3, #112 ; 0x70
8002e90: b29c uxth r4, r3
8002e92: 687b ldr r3, [r7, #4]
8002e94: 681b ldr r3, [r3, #0]
8002e96: 461a mov r2, r3
8002e98: 7d7b ldrb r3, [r7, #21]
8002e9a: 009b lsls r3, r3, #2
8002e9c: 441a add r2, r3
8002e9e: ea6f 4344 mvn.w r3, r4, lsl #17
8002ea2: ea6f 4353 mvn.w r3, r3, lsr #17
8002ea6: b29b uxth r3, r3
8002ea8: 8013 strh r3, [r2, #0]
/*multi-packet on the NON control IN endpoint*/
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
8002eaa: 687b ldr r3, [r7, #4]
8002eac: 681b ldr r3, [r3, #0]
8002eae: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8002eb2: b29b uxth r3, r3
8002eb4: 461a mov r2, r3
8002eb6: 68fb ldr r3, [r7, #12]
8002eb8: 781b ldrb r3, [r3, #0]
8002eba: 00db lsls r3, r3, #3
8002ebc: 4413 add r3, r2
8002ebe: 3302 adds r3, #2
8002ec0: 005b lsls r3, r3, #1
8002ec2: 687a ldr r2, [r7, #4]
8002ec4: 6812 ldr r2, [r2, #0]
8002ec6: 4413 add r3, r2
8002ec8: f503 6380 add.w r3, r3, #1024 ; 0x400
8002ecc: 881b ldrh r3, [r3, #0]
8002ece: f3c3 0209 ubfx r2, r3, #0, #10
8002ed2: 68fb ldr r3, [r7, #12]
8002ed4: 61da str r2, [r3, #28]
ep->xfer_buff += ep->xfer_count;
8002ed6: 68fb ldr r3, [r7, #12]
8002ed8: 695a ldr r2, [r3, #20]
8002eda: 68fb ldr r3, [r7, #12]
8002edc: 69db ldr r3, [r3, #28]
8002ede: 441a add r2, r3
8002ee0: 68fb ldr r3, [r7, #12]
8002ee2: 615a str r2, [r3, #20]
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
8002ee4: 68fb ldr r3, [r7, #12]
8002ee6: 699b ldr r3, [r3, #24]
8002ee8: 2b00 cmp r3, #0
8002eea: d106 bne.n 8002efa <PCD_EP_ISR_Handler+0x4fe>
{
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
8002eec: 68fb ldr r3, [r7, #12]
8002eee: 781b ldrb r3, [r3, #0]
8002ef0: 4619 mov r1, r3
8002ef2: 6878 ldr r0, [r7, #4]
8002ef4: f004 feaa bl 8007c4c <HAL_PCD_DataInStageCallback>
8002ef8: e008 b.n 8002f0c <PCD_EP_ISR_Handler+0x510>
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
(void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
8002efa: 68fb ldr r3, [r7, #12]
8002efc: 7819 ldrb r1, [r3, #0]
8002efe: 68fb ldr r3, [r7, #12]
8002f00: 695a ldr r2, [r3, #20]
8002f02: 68fb ldr r3, [r7, #12]
8002f04: 699b ldr r3, [r3, #24]
8002f06: 6878 ldr r0, [r7, #4]
8002f08: f7ff fc96 bl 8002838 <HAL_PCD_EP_Transmit>
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
8002f0c: 687b ldr r3, [r7, #4]
8002f0e: 681b ldr r3, [r3, #0]
8002f10: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
8002f14: b29b uxth r3, r3
8002f16: b21b sxth r3, r3
8002f18: 2b00 cmp r3, #0
8002f1a: f6ff ad74 blt.w 8002a06 <PCD_EP_ISR_Handler+0xa>
}
}
}
}
return HAL_OK;
8002f1e: 2300 movs r3, #0
}
8002f20: 4618 mov r0, r3
8002f22: 3724 adds r7, #36 ; 0x24
8002f24: 46bd mov sp, r7
8002f26: bd90 pop {r4, r7, pc}
8002f28: ffff8080 .word 0xffff8080
8002f2c: ffff80c0 .word 0xffff80c0
08002f30 <HAL_PCDEx_PMAConfig>:
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress)
{
8002f30: b480 push {r7}
8002f32: b087 sub sp, #28
8002f34: af00 add r7, sp, #0
8002f36: 60f8 str r0, [r7, #12]
8002f38: 607b str r3, [r7, #4]
8002f3a: 460b mov r3, r1
8002f3c: 817b strh r3, [r7, #10]
8002f3e: 4613 mov r3, r2
8002f40: 813b strh r3, [r7, #8]
PCD_EPTypeDef *ep;
/* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U)
8002f42: 897b ldrh r3, [r7, #10]
8002f44: f003 0380 and.w r3, r3, #128 ; 0x80
8002f48: b29b uxth r3, r3
8002f4a: 2b00 cmp r3, #0
8002f4c: d008 beq.n 8002f60 <HAL_PCDEx_PMAConfig+0x30>
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
8002f4e: 897b ldrh r3, [r7, #10]
8002f50: f003 0307 and.w r3, r3, #7
8002f54: 015b lsls r3, r3, #5
8002f56: 3328 adds r3, #40 ; 0x28
8002f58: 68fa ldr r2, [r7, #12]
8002f5a: 4413 add r3, r2
8002f5c: 617b str r3, [r7, #20]
8002f5e: e006 b.n 8002f6e <HAL_PCDEx_PMAConfig+0x3e>
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
8002f60: 897b ldrh r3, [r7, #10]
8002f62: 015b lsls r3, r3, #5
8002f64: f503 7394 add.w r3, r3, #296 ; 0x128
8002f68: 68fa ldr r2, [r7, #12]
8002f6a: 4413 add r3, r2
8002f6c: 617b str r3, [r7, #20]
}
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
8002f6e: 893b ldrh r3, [r7, #8]
8002f70: 2b00 cmp r3, #0
8002f72: d107 bne.n 8002f84 <HAL_PCDEx_PMAConfig+0x54>
{
/* Single Buffer */
ep->doublebuffer = 0U;
8002f74: 697b ldr r3, [r7, #20]
8002f76: 2200 movs r2, #0
8002f78: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
8002f7a: 687b ldr r3, [r7, #4]
8002f7c: b29a uxth r2, r3
8002f7e: 697b ldr r3, [r7, #20]
8002f80: 80da strh r2, [r3, #6]
8002f82: e00b b.n 8002f9c <HAL_PCDEx_PMAConfig+0x6c>
}
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
ep->doublebuffer = 1U;
8002f84: 697b ldr r3, [r7, #20]
8002f86: 2201 movs r2, #1
8002f88: 731a strb r2, [r3, #12]
/* Configure the PMA */
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
8002f8a: 687b ldr r3, [r7, #4]
8002f8c: b29a uxth r2, r3
8002f8e: 697b ldr r3, [r7, #20]
8002f90: 811a strh r2, [r3, #8]
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
8002f92: 687b ldr r3, [r7, #4]
8002f94: 0c1b lsrs r3, r3, #16
8002f96: b29a uxth r2, r3
8002f98: 697b ldr r3, [r7, #20]
8002f9a: 815a strh r2, [r3, #10]
}
return HAL_OK;
8002f9c: 2300 movs r3, #0
}
8002f9e: 4618 mov r0, r3
8002fa0: 371c adds r7, #28
8002fa2: 46bd mov sp, r7
8002fa4: bc80 pop {r7}
8002fa6: 4770 bx lr
08002fa8 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8002fa8: b580 push {r7, lr}
8002faa: b086 sub sp, #24
8002fac: af00 add r7, sp, #0
8002fae: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8002fb0: 687b ldr r3, [r7, #4]
8002fb2: 2b00 cmp r3, #0
8002fb4: d101 bne.n 8002fba <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8002fb6: 2301 movs r3, #1
8002fb8: e26c b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002fba: 687b ldr r3, [r7, #4]
8002fbc: 681b ldr r3, [r3, #0]
8002fbe: f003 0301 and.w r3, r3, #1
8002fc2: 2b00 cmp r3, #0
8002fc4: f000 8087 beq.w 80030d6 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8002fc8: 4b92 ldr r3, [pc, #584] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8002fca: 685b ldr r3, [r3, #4]
8002fcc: f003 030c and.w r3, r3, #12
8002fd0: 2b04 cmp r3, #4
8002fd2: d00c beq.n 8002fee <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8002fd4: 4b8f ldr r3, [pc, #572] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8002fd6: 685b ldr r3, [r3, #4]
8002fd8: f003 030c and.w r3, r3, #12
8002fdc: 2b08 cmp r3, #8
8002fde: d112 bne.n 8003006 <HAL_RCC_OscConfig+0x5e>
8002fe0: 4b8c ldr r3, [pc, #560] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8002fe2: 685b ldr r3, [r3, #4]
8002fe4: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002fe8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002fec: d10b bne.n 8003006 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002fee: 4b89 ldr r3, [pc, #548] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8002ff0: 681b ldr r3, [r3, #0]
8002ff2: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002ff6: 2b00 cmp r3, #0
8002ff8: d06c beq.n 80030d4 <HAL_RCC_OscConfig+0x12c>
8002ffa: 687b ldr r3, [r7, #4]
8002ffc: 685b ldr r3, [r3, #4]
8002ffe: 2b00 cmp r3, #0
8003000: d168 bne.n 80030d4 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8003002: 2301 movs r3, #1
8003004: e246 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8003006: 687b ldr r3, [r7, #4]
8003008: 685b ldr r3, [r3, #4]
800300a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800300e: d106 bne.n 800301e <HAL_RCC_OscConfig+0x76>
8003010: 4b80 ldr r3, [pc, #512] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003012: 681b ldr r3, [r3, #0]
8003014: 4a7f ldr r2, [pc, #508] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003016: f443 3380 orr.w r3, r3, #65536 ; 0x10000
800301a: 6013 str r3, [r2, #0]
800301c: e02e b.n 800307c <HAL_RCC_OscConfig+0xd4>
800301e: 687b ldr r3, [r7, #4]
8003020: 685b ldr r3, [r3, #4]
8003022: 2b00 cmp r3, #0
8003024: d10c bne.n 8003040 <HAL_RCC_OscConfig+0x98>
8003026: 4b7b ldr r3, [pc, #492] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003028: 681b ldr r3, [r3, #0]
800302a: 4a7a ldr r2, [pc, #488] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
800302c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8003030: 6013 str r3, [r2, #0]
8003032: 4b78 ldr r3, [pc, #480] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003034: 681b ldr r3, [r3, #0]
8003036: 4a77 ldr r2, [pc, #476] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003038: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800303c: 6013 str r3, [r2, #0]
800303e: e01d b.n 800307c <HAL_RCC_OscConfig+0xd4>
8003040: 687b ldr r3, [r7, #4]
8003042: 685b ldr r3, [r3, #4]
8003044: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8003048: d10c bne.n 8003064 <HAL_RCC_OscConfig+0xbc>
800304a: 4b72 ldr r3, [pc, #456] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
800304c: 681b ldr r3, [r3, #0]
800304e: 4a71 ldr r2, [pc, #452] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003050: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8003054: 6013 str r3, [r2, #0]
8003056: 4b6f ldr r3, [pc, #444] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003058: 681b ldr r3, [r3, #0]
800305a: 4a6e ldr r2, [pc, #440] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
800305c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8003060: 6013 str r3, [r2, #0]
8003062: e00b b.n 800307c <HAL_RCC_OscConfig+0xd4>
8003064: 4b6b ldr r3, [pc, #428] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003066: 681b ldr r3, [r3, #0]
8003068: 4a6a ldr r2, [pc, #424] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
800306a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800306e: 6013 str r3, [r2, #0]
8003070: 4b68 ldr r3, [pc, #416] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003072: 681b ldr r3, [r3, #0]
8003074: 4a67 ldr r2, [pc, #412] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003076: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800307a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800307c: 687b ldr r3, [r7, #4]
800307e: 685b ldr r3, [r3, #4]
8003080: 2b00 cmp r3, #0
8003082: d013 beq.n 80030ac <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8003084: f7fe fa6a bl 800155c <HAL_GetTick>
8003088: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800308a: e008 b.n 800309e <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800308c: f7fe fa66 bl 800155c <HAL_GetTick>
8003090: 4602 mov r2, r0
8003092: 693b ldr r3, [r7, #16]
8003094: 1ad3 subs r3, r2, r3
8003096: 2b64 cmp r3, #100 ; 0x64
8003098: d901 bls.n 800309e <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
800309a: 2303 movs r3, #3
800309c: e1fa b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800309e: 4b5d ldr r3, [pc, #372] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
80030a0: 681b ldr r3, [r3, #0]
80030a2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80030a6: 2b00 cmp r3, #0
80030a8: d0f0 beq.n 800308c <HAL_RCC_OscConfig+0xe4>
80030aa: e014 b.n 80030d6 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80030ac: f7fe fa56 bl 800155c <HAL_GetTick>
80030b0: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80030b2: e008 b.n 80030c6 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80030b4: f7fe fa52 bl 800155c <HAL_GetTick>
80030b8: 4602 mov r2, r0
80030ba: 693b ldr r3, [r7, #16]
80030bc: 1ad3 subs r3, r2, r3
80030be: 2b64 cmp r3, #100 ; 0x64
80030c0: d901 bls.n 80030c6 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
80030c2: 2303 movs r3, #3
80030c4: e1e6 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80030c6: 4b53 ldr r3, [pc, #332] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
80030c8: 681b ldr r3, [r3, #0]
80030ca: f403 3300 and.w r3, r3, #131072 ; 0x20000
80030ce: 2b00 cmp r3, #0
80030d0: d1f0 bne.n 80030b4 <HAL_RCC_OscConfig+0x10c>
80030d2: e000 b.n 80030d6 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80030d4: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80030d6: 687b ldr r3, [r7, #4]
80030d8: 681b ldr r3, [r3, #0]
80030da: f003 0302 and.w r3, r3, #2
80030de: 2b00 cmp r3, #0
80030e0: d063 beq.n 80031aa <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80030e2: 4b4c ldr r3, [pc, #304] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
80030e4: 685b ldr r3, [r3, #4]
80030e6: f003 030c and.w r3, r3, #12
80030ea: 2b00 cmp r3, #0
80030ec: d00b beq.n 8003106 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
80030ee: 4b49 ldr r3, [pc, #292] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
80030f0: 685b ldr r3, [r3, #4]
80030f2: f003 030c and.w r3, r3, #12
80030f6: 2b08 cmp r3, #8
80030f8: d11c bne.n 8003134 <HAL_RCC_OscConfig+0x18c>
80030fa: 4b46 ldr r3, [pc, #280] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
80030fc: 685b ldr r3, [r3, #4]
80030fe: f403 3380 and.w r3, r3, #65536 ; 0x10000
8003102: 2b00 cmp r3, #0
8003104: d116 bne.n 8003134 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8003106: 4b43 ldr r3, [pc, #268] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003108: 681b ldr r3, [r3, #0]
800310a: f003 0302 and.w r3, r3, #2
800310e: 2b00 cmp r3, #0
8003110: d005 beq.n 800311e <HAL_RCC_OscConfig+0x176>
8003112: 687b ldr r3, [r7, #4]
8003114: 691b ldr r3, [r3, #16]
8003116: 2b01 cmp r3, #1
8003118: d001 beq.n 800311e <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
800311a: 2301 movs r3, #1
800311c: e1ba b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800311e: 4b3d ldr r3, [pc, #244] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003120: 681b ldr r3, [r3, #0]
8003122: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8003126: 687b ldr r3, [r7, #4]
8003128: 695b ldr r3, [r3, #20]
800312a: 00db lsls r3, r3, #3
800312c: 4939 ldr r1, [pc, #228] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
800312e: 4313 orrs r3, r2
8003130: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8003132: e03a b.n 80031aa <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8003134: 687b ldr r3, [r7, #4]
8003136: 691b ldr r3, [r3, #16]
8003138: 2b00 cmp r3, #0
800313a: d020 beq.n 800317e <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800313c: 4b36 ldr r3, [pc, #216] ; (8003218 <HAL_RCC_OscConfig+0x270>)
800313e: 2201 movs r2, #1
8003140: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003142: f7fe fa0b bl 800155c <HAL_GetTick>
8003146: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003148: e008 b.n 800315c <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800314a: f7fe fa07 bl 800155c <HAL_GetTick>
800314e: 4602 mov r2, r0
8003150: 693b ldr r3, [r7, #16]
8003152: 1ad3 subs r3, r2, r3
8003154: 2b02 cmp r3, #2
8003156: d901 bls.n 800315c <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8003158: 2303 movs r3, #3
800315a: e19b b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800315c: 4b2d ldr r3, [pc, #180] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
800315e: 681b ldr r3, [r3, #0]
8003160: f003 0302 and.w r3, r3, #2
8003164: 2b00 cmp r3, #0
8003166: d0f0 beq.n 800314a <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003168: 4b2a ldr r3, [pc, #168] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
800316a: 681b ldr r3, [r3, #0]
800316c: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8003170: 687b ldr r3, [r7, #4]
8003172: 695b ldr r3, [r3, #20]
8003174: 00db lsls r3, r3, #3
8003176: 4927 ldr r1, [pc, #156] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
8003178: 4313 orrs r3, r2
800317a: 600b str r3, [r1, #0]
800317c: e015 b.n 80031aa <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800317e: 4b26 ldr r3, [pc, #152] ; (8003218 <HAL_RCC_OscConfig+0x270>)
8003180: 2200 movs r2, #0
8003182: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003184: f7fe f9ea bl 800155c <HAL_GetTick>
8003188: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800318a: e008 b.n 800319e <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800318c: f7fe f9e6 bl 800155c <HAL_GetTick>
8003190: 4602 mov r2, r0
8003192: 693b ldr r3, [r7, #16]
8003194: 1ad3 subs r3, r2, r3
8003196: 2b02 cmp r3, #2
8003198: d901 bls.n 800319e <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
800319a: 2303 movs r3, #3
800319c: e17a b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800319e: 4b1d ldr r3, [pc, #116] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
80031a0: 681b ldr r3, [r3, #0]
80031a2: f003 0302 and.w r3, r3, #2
80031a6: 2b00 cmp r3, #0
80031a8: d1f0 bne.n 800318c <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80031aa: 687b ldr r3, [r7, #4]
80031ac: 681b ldr r3, [r3, #0]
80031ae: f003 0308 and.w r3, r3, #8
80031b2: 2b00 cmp r3, #0
80031b4: d03a beq.n 800322c <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80031b6: 687b ldr r3, [r7, #4]
80031b8: 699b ldr r3, [r3, #24]
80031ba: 2b00 cmp r3, #0
80031bc: d019 beq.n 80031f2 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80031be: 4b17 ldr r3, [pc, #92] ; (800321c <HAL_RCC_OscConfig+0x274>)
80031c0: 2201 movs r2, #1
80031c2: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80031c4: f7fe f9ca bl 800155c <HAL_GetTick>
80031c8: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80031ca: e008 b.n 80031de <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80031cc: f7fe f9c6 bl 800155c <HAL_GetTick>
80031d0: 4602 mov r2, r0
80031d2: 693b ldr r3, [r7, #16]
80031d4: 1ad3 subs r3, r2, r3
80031d6: 2b02 cmp r3, #2
80031d8: d901 bls.n 80031de <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
80031da: 2303 movs r3, #3
80031dc: e15a b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80031de: 4b0d ldr r3, [pc, #52] ; (8003214 <HAL_RCC_OscConfig+0x26c>)
80031e0: 6a5b ldr r3, [r3, #36] ; 0x24
80031e2: f003 0302 and.w r3, r3, #2
80031e6: 2b00 cmp r3, #0
80031e8: d0f0 beq.n 80031cc <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
80031ea: 2001 movs r0, #1
80031ec: f000 fb0a bl 8003804 <RCC_Delay>
80031f0: e01c b.n 800322c <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80031f2: 4b0a ldr r3, [pc, #40] ; (800321c <HAL_RCC_OscConfig+0x274>)
80031f4: 2200 movs r2, #0
80031f6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80031f8: f7fe f9b0 bl 800155c <HAL_GetTick>
80031fc: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80031fe: e00f b.n 8003220 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8003200: f7fe f9ac bl 800155c <HAL_GetTick>
8003204: 4602 mov r2, r0
8003206: 693b ldr r3, [r7, #16]
8003208: 1ad3 subs r3, r2, r3
800320a: 2b02 cmp r3, #2
800320c: d908 bls.n 8003220 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
800320e: 2303 movs r3, #3
8003210: e140 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
8003212: bf00 nop
8003214: 40021000 .word 0x40021000
8003218: 42420000 .word 0x42420000
800321c: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8003220: 4b9e ldr r3, [pc, #632] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003222: 6a5b ldr r3, [r3, #36] ; 0x24
8003224: f003 0302 and.w r3, r3, #2
8003228: 2b00 cmp r3, #0
800322a: d1e9 bne.n 8003200 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800322c: 687b ldr r3, [r7, #4]
800322e: 681b ldr r3, [r3, #0]
8003230: f003 0304 and.w r3, r3, #4
8003234: 2b00 cmp r3, #0
8003236: f000 80a6 beq.w 8003386 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
800323a: 2300 movs r3, #0
800323c: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800323e: 4b97 ldr r3, [pc, #604] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003240: 69db ldr r3, [r3, #28]
8003242: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003246: 2b00 cmp r3, #0
8003248: d10d bne.n 8003266 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
800324a: 4b94 ldr r3, [pc, #592] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
800324c: 69db ldr r3, [r3, #28]
800324e: 4a93 ldr r2, [pc, #588] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003250: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8003254: 61d3 str r3, [r2, #28]
8003256: 4b91 ldr r3, [pc, #580] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003258: 69db ldr r3, [r3, #28]
800325a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800325e: 60bb str r3, [r7, #8]
8003260: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8003262: 2301 movs r3, #1
8003264: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003266: 4b8e ldr r3, [pc, #568] ; (80034a0 <HAL_RCC_OscConfig+0x4f8>)
8003268: 681b ldr r3, [r3, #0]
800326a: f403 7380 and.w r3, r3, #256 ; 0x100
800326e: 2b00 cmp r3, #0
8003270: d118 bne.n 80032a4 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8003272: 4b8b ldr r3, [pc, #556] ; (80034a0 <HAL_RCC_OscConfig+0x4f8>)
8003274: 681b ldr r3, [r3, #0]
8003276: 4a8a ldr r2, [pc, #552] ; (80034a0 <HAL_RCC_OscConfig+0x4f8>)
8003278: f443 7380 orr.w r3, r3, #256 ; 0x100
800327c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800327e: f7fe f96d bl 800155c <HAL_GetTick>
8003282: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003284: e008 b.n 8003298 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003286: f7fe f969 bl 800155c <HAL_GetTick>
800328a: 4602 mov r2, r0
800328c: 693b ldr r3, [r7, #16]
800328e: 1ad3 subs r3, r2, r3
8003290: 2b64 cmp r3, #100 ; 0x64
8003292: d901 bls.n 8003298 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8003294: 2303 movs r3, #3
8003296: e0fd b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003298: 4b81 ldr r3, [pc, #516] ; (80034a0 <HAL_RCC_OscConfig+0x4f8>)
800329a: 681b ldr r3, [r3, #0]
800329c: f403 7380 and.w r3, r3, #256 ; 0x100
80032a0: 2b00 cmp r3, #0
80032a2: d0f0 beq.n 8003286 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80032a4: 687b ldr r3, [r7, #4]
80032a6: 68db ldr r3, [r3, #12]
80032a8: 2b01 cmp r3, #1
80032aa: d106 bne.n 80032ba <HAL_RCC_OscConfig+0x312>
80032ac: 4b7b ldr r3, [pc, #492] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032ae: 6a1b ldr r3, [r3, #32]
80032b0: 4a7a ldr r2, [pc, #488] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032b2: f043 0301 orr.w r3, r3, #1
80032b6: 6213 str r3, [r2, #32]
80032b8: e02d b.n 8003316 <HAL_RCC_OscConfig+0x36e>
80032ba: 687b ldr r3, [r7, #4]
80032bc: 68db ldr r3, [r3, #12]
80032be: 2b00 cmp r3, #0
80032c0: d10c bne.n 80032dc <HAL_RCC_OscConfig+0x334>
80032c2: 4b76 ldr r3, [pc, #472] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032c4: 6a1b ldr r3, [r3, #32]
80032c6: 4a75 ldr r2, [pc, #468] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032c8: f023 0301 bic.w r3, r3, #1
80032cc: 6213 str r3, [r2, #32]
80032ce: 4b73 ldr r3, [pc, #460] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032d0: 6a1b ldr r3, [r3, #32]
80032d2: 4a72 ldr r2, [pc, #456] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032d4: f023 0304 bic.w r3, r3, #4
80032d8: 6213 str r3, [r2, #32]
80032da: e01c b.n 8003316 <HAL_RCC_OscConfig+0x36e>
80032dc: 687b ldr r3, [r7, #4]
80032de: 68db ldr r3, [r3, #12]
80032e0: 2b05 cmp r3, #5
80032e2: d10c bne.n 80032fe <HAL_RCC_OscConfig+0x356>
80032e4: 4b6d ldr r3, [pc, #436] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032e6: 6a1b ldr r3, [r3, #32]
80032e8: 4a6c ldr r2, [pc, #432] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032ea: f043 0304 orr.w r3, r3, #4
80032ee: 6213 str r3, [r2, #32]
80032f0: 4b6a ldr r3, [pc, #424] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032f2: 6a1b ldr r3, [r3, #32]
80032f4: 4a69 ldr r2, [pc, #420] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80032f6: f043 0301 orr.w r3, r3, #1
80032fa: 6213 str r3, [r2, #32]
80032fc: e00b b.n 8003316 <HAL_RCC_OscConfig+0x36e>
80032fe: 4b67 ldr r3, [pc, #412] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003300: 6a1b ldr r3, [r3, #32]
8003302: 4a66 ldr r2, [pc, #408] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003304: f023 0301 bic.w r3, r3, #1
8003308: 6213 str r3, [r2, #32]
800330a: 4b64 ldr r3, [pc, #400] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
800330c: 6a1b ldr r3, [r3, #32]
800330e: 4a63 ldr r2, [pc, #396] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003310: f023 0304 bic.w r3, r3, #4
8003314: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8003316: 687b ldr r3, [r7, #4]
8003318: 68db ldr r3, [r3, #12]
800331a: 2b00 cmp r3, #0
800331c: d015 beq.n 800334a <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800331e: f7fe f91d bl 800155c <HAL_GetTick>
8003322: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003324: e00a b.n 800333c <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003326: f7fe f919 bl 800155c <HAL_GetTick>
800332a: 4602 mov r2, r0
800332c: 693b ldr r3, [r7, #16]
800332e: 1ad3 subs r3, r2, r3
8003330: f241 3288 movw r2, #5000 ; 0x1388
8003334: 4293 cmp r3, r2
8003336: d901 bls.n 800333c <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8003338: 2303 movs r3, #3
800333a: e0ab b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800333c: 4b57 ldr r3, [pc, #348] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
800333e: 6a1b ldr r3, [r3, #32]
8003340: f003 0302 and.w r3, r3, #2
8003344: 2b00 cmp r3, #0
8003346: d0ee beq.n 8003326 <HAL_RCC_OscConfig+0x37e>
8003348: e014 b.n 8003374 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800334a: f7fe f907 bl 800155c <HAL_GetTick>
800334e: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8003350: e00a b.n 8003368 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003352: f7fe f903 bl 800155c <HAL_GetTick>
8003356: 4602 mov r2, r0
8003358: 693b ldr r3, [r7, #16]
800335a: 1ad3 subs r3, r2, r3
800335c: f241 3288 movw r2, #5000 ; 0x1388
8003360: 4293 cmp r3, r2
8003362: d901 bls.n 8003368 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8003364: 2303 movs r3, #3
8003366: e095 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8003368: 4b4c ldr r3, [pc, #304] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
800336a: 6a1b ldr r3, [r3, #32]
800336c: f003 0302 and.w r3, r3, #2
8003370: 2b00 cmp r3, #0
8003372: d1ee bne.n 8003352 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8003374: 7dfb ldrb r3, [r7, #23]
8003376: 2b01 cmp r3, #1
8003378: d105 bne.n 8003386 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
800337a: 4b48 ldr r3, [pc, #288] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
800337c: 69db ldr r3, [r3, #28]
800337e: 4a47 ldr r2, [pc, #284] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003380: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8003384: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8003386: 687b ldr r3, [r7, #4]
8003388: 69db ldr r3, [r3, #28]
800338a: 2b00 cmp r3, #0
800338c: f000 8081 beq.w 8003492 <HAL_RCC_OscConfig+0x4ea>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8003390: 4b42 ldr r3, [pc, #264] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003392: 685b ldr r3, [r3, #4]
8003394: f003 030c and.w r3, r3, #12
8003398: 2b08 cmp r3, #8
800339a: d061 beq.n 8003460 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
800339c: 687b ldr r3, [r7, #4]
800339e: 69db ldr r3, [r3, #28]
80033a0: 2b02 cmp r3, #2
80033a2: d146 bne.n 8003432 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80033a4: 4b3f ldr r3, [pc, #252] ; (80034a4 <HAL_RCC_OscConfig+0x4fc>)
80033a6: 2200 movs r2, #0
80033a8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80033aa: f7fe f8d7 bl 800155c <HAL_GetTick>
80033ae: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80033b0: e008 b.n 80033c4 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80033b2: f7fe f8d3 bl 800155c <HAL_GetTick>
80033b6: 4602 mov r2, r0
80033b8: 693b ldr r3, [r7, #16]
80033ba: 1ad3 subs r3, r2, r3
80033bc: 2b02 cmp r3, #2
80033be: d901 bls.n 80033c4 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
80033c0: 2303 movs r3, #3
80033c2: e067 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80033c4: 4b35 ldr r3, [pc, #212] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80033c6: 681b ldr r3, [r3, #0]
80033c8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80033cc: 2b00 cmp r3, #0
80033ce: d1f0 bne.n 80033b2 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
80033d0: 687b ldr r3, [r7, #4]
80033d2: 6a1b ldr r3, [r3, #32]
80033d4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80033d8: d108 bne.n 80033ec <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
80033da: 4b30 ldr r3, [pc, #192] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80033dc: 685b ldr r3, [r3, #4]
80033de: f423 3200 bic.w r2, r3, #131072 ; 0x20000
80033e2: 687b ldr r3, [r7, #4]
80033e4: 689b ldr r3, [r3, #8]
80033e6: 492d ldr r1, [pc, #180] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80033e8: 4313 orrs r3, r2
80033ea: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80033ec: 4b2b ldr r3, [pc, #172] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
80033ee: 685b ldr r3, [r3, #4]
80033f0: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
80033f4: 687b ldr r3, [r7, #4]
80033f6: 6a19 ldr r1, [r3, #32]
80033f8: 687b ldr r3, [r7, #4]
80033fa: 6a5b ldr r3, [r3, #36] ; 0x24
80033fc: 430b orrs r3, r1
80033fe: 4927 ldr r1, [pc, #156] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003400: 4313 orrs r3, r2
8003402: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8003404: 4b27 ldr r3, [pc, #156] ; (80034a4 <HAL_RCC_OscConfig+0x4fc>)
8003406: 2201 movs r2, #1
8003408: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800340a: f7fe f8a7 bl 800155c <HAL_GetTick>
800340e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003410: e008 b.n 8003424 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003412: f7fe f8a3 bl 800155c <HAL_GetTick>
8003416: 4602 mov r2, r0
8003418: 693b ldr r3, [r7, #16]
800341a: 1ad3 subs r3, r2, r3
800341c: 2b02 cmp r3, #2
800341e: d901 bls.n 8003424 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8003420: 2303 movs r3, #3
8003422: e037 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003424: 4b1d ldr r3, [pc, #116] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003426: 681b ldr r3, [r3, #0]
8003428: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800342c: 2b00 cmp r3, #0
800342e: d0f0 beq.n 8003412 <HAL_RCC_OscConfig+0x46a>
8003430: e02f b.n 8003492 <HAL_RCC_OscConfig+0x4ea>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003432: 4b1c ldr r3, [pc, #112] ; (80034a4 <HAL_RCC_OscConfig+0x4fc>)
8003434: 2200 movs r2, #0
8003436: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003438: f7fe f890 bl 800155c <HAL_GetTick>
800343c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800343e: e008 b.n 8003452 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003440: f7fe f88c bl 800155c <HAL_GetTick>
8003444: 4602 mov r2, r0
8003446: 693b ldr r3, [r7, #16]
8003448: 1ad3 subs r3, r2, r3
800344a: 2b02 cmp r3, #2
800344c: d901 bls.n 8003452 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
800344e: 2303 movs r3, #3
8003450: e020 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003452: 4b12 ldr r3, [pc, #72] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
8003454: 681b ldr r3, [r3, #0]
8003456: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800345a: 2b00 cmp r3, #0
800345c: d1f0 bne.n 8003440 <HAL_RCC_OscConfig+0x498>
800345e: e018 b.n 8003492 <HAL_RCC_OscConfig+0x4ea>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8003460: 687b ldr r3, [r7, #4]
8003462: 69db ldr r3, [r3, #28]
8003464: 2b01 cmp r3, #1
8003466: d101 bne.n 800346c <HAL_RCC_OscConfig+0x4c4>
{
return HAL_ERROR;
8003468: 2301 movs r3, #1
800346a: e013 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800346c: 4b0b ldr r3, [pc, #44] ; (800349c <HAL_RCC_OscConfig+0x4f4>)
800346e: 685b ldr r3, [r3, #4]
8003470: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003472: 68fb ldr r3, [r7, #12]
8003474: f403 3280 and.w r2, r3, #65536 ; 0x10000
8003478: 687b ldr r3, [r7, #4]
800347a: 6a1b ldr r3, [r3, #32]
800347c: 429a cmp r2, r3
800347e: d106 bne.n 800348e <HAL_RCC_OscConfig+0x4e6>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8003480: 68fb ldr r3, [r7, #12]
8003482: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
8003486: 687b ldr r3, [r7, #4]
8003488: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800348a: 429a cmp r2, r3
800348c: d001 beq.n 8003492 <HAL_RCC_OscConfig+0x4ea>
{
return HAL_ERROR;
800348e: 2301 movs r3, #1
8003490: e000 b.n 8003494 <HAL_RCC_OscConfig+0x4ec>
}
}
}
}
return HAL_OK;
8003492: 2300 movs r3, #0
}
8003494: 4618 mov r0, r3
8003496: 3718 adds r7, #24
8003498: 46bd mov sp, r7
800349a: bd80 pop {r7, pc}
800349c: 40021000 .word 0x40021000
80034a0: 40007000 .word 0x40007000
80034a4: 42420060 .word 0x42420060
080034a8 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80034a8: b580 push {r7, lr}
80034aa: b084 sub sp, #16
80034ac: af00 add r7, sp, #0
80034ae: 6078 str r0, [r7, #4]
80034b0: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80034b2: 687b ldr r3, [r7, #4]
80034b4: 2b00 cmp r3, #0
80034b6: d101 bne.n 80034bc <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80034b8: 2301 movs r3, #1
80034ba: e0d0 b.n 800365e <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
80034bc: 4b6a ldr r3, [pc, #424] ; (8003668 <HAL_RCC_ClockConfig+0x1c0>)
80034be: 681b ldr r3, [r3, #0]
80034c0: f003 0307 and.w r3, r3, #7
80034c4: 683a ldr r2, [r7, #0]
80034c6: 429a cmp r2, r3
80034c8: d910 bls.n 80034ec <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80034ca: 4b67 ldr r3, [pc, #412] ; (8003668 <HAL_RCC_ClockConfig+0x1c0>)
80034cc: 681b ldr r3, [r3, #0]
80034ce: f023 0207 bic.w r2, r3, #7
80034d2: 4965 ldr r1, [pc, #404] ; (8003668 <HAL_RCC_ClockConfig+0x1c0>)
80034d4: 683b ldr r3, [r7, #0]
80034d6: 4313 orrs r3, r2
80034d8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80034da: 4b63 ldr r3, [pc, #396] ; (8003668 <HAL_RCC_ClockConfig+0x1c0>)
80034dc: 681b ldr r3, [r3, #0]
80034de: f003 0307 and.w r3, r3, #7
80034e2: 683a ldr r2, [r7, #0]
80034e4: 429a cmp r2, r3
80034e6: d001 beq.n 80034ec <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
80034e8: 2301 movs r3, #1
80034ea: e0b8 b.n 800365e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80034ec: 687b ldr r3, [r7, #4]
80034ee: 681b ldr r3, [r3, #0]
80034f0: f003 0302 and.w r3, r3, #2
80034f4: 2b00 cmp r3, #0
80034f6: d020 beq.n 800353a <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80034f8: 687b ldr r3, [r7, #4]
80034fa: 681b ldr r3, [r3, #0]
80034fc: f003 0304 and.w r3, r3, #4
8003500: 2b00 cmp r3, #0
8003502: d005 beq.n 8003510 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8003504: 4b59 ldr r3, [pc, #356] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003506: 685b ldr r3, [r3, #4]
8003508: 4a58 ldr r2, [pc, #352] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
800350a: f443 63e0 orr.w r3, r3, #1792 ; 0x700
800350e: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8003510: 687b ldr r3, [r7, #4]
8003512: 681b ldr r3, [r3, #0]
8003514: f003 0308 and.w r3, r3, #8
8003518: 2b00 cmp r3, #0
800351a: d005 beq.n 8003528 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
800351c: 4b53 ldr r3, [pc, #332] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
800351e: 685b ldr r3, [r3, #4]
8003520: 4a52 ldr r2, [pc, #328] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003522: f443 5360 orr.w r3, r3, #14336 ; 0x3800
8003526: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003528: 4b50 ldr r3, [pc, #320] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
800352a: 685b ldr r3, [r3, #4]
800352c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8003530: 687b ldr r3, [r7, #4]
8003532: 689b ldr r3, [r3, #8]
8003534: 494d ldr r1, [pc, #308] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003536: 4313 orrs r3, r2
8003538: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800353a: 687b ldr r3, [r7, #4]
800353c: 681b ldr r3, [r3, #0]
800353e: f003 0301 and.w r3, r3, #1
8003542: 2b00 cmp r3, #0
8003544: d040 beq.n 80035c8 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8003546: 687b ldr r3, [r7, #4]
8003548: 685b ldr r3, [r3, #4]
800354a: 2b01 cmp r3, #1
800354c: d107 bne.n 800355e <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800354e: 4b47 ldr r3, [pc, #284] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003550: 681b ldr r3, [r3, #0]
8003552: f403 3300 and.w r3, r3, #131072 ; 0x20000
8003556: 2b00 cmp r3, #0
8003558: d115 bne.n 8003586 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800355a: 2301 movs r3, #1
800355c: e07f b.n 800365e <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800355e: 687b ldr r3, [r7, #4]
8003560: 685b ldr r3, [r3, #4]
8003562: 2b02 cmp r3, #2
8003564: d107 bne.n 8003576 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003566: 4b41 ldr r3, [pc, #260] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003568: 681b ldr r3, [r3, #0]
800356a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800356e: 2b00 cmp r3, #0
8003570: d109 bne.n 8003586 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003572: 2301 movs r3, #1
8003574: e073 b.n 800365e <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003576: 4b3d ldr r3, [pc, #244] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003578: 681b ldr r3, [r3, #0]
800357a: f003 0302 and.w r3, r3, #2
800357e: 2b00 cmp r3, #0
8003580: d101 bne.n 8003586 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003582: 2301 movs r3, #1
8003584: e06b b.n 800365e <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8003586: 4b39 ldr r3, [pc, #228] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003588: 685b ldr r3, [r3, #4]
800358a: f023 0203 bic.w r2, r3, #3
800358e: 687b ldr r3, [r7, #4]
8003590: 685b ldr r3, [r3, #4]
8003592: 4936 ldr r1, [pc, #216] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003594: 4313 orrs r3, r2
8003596: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003598: f7fd ffe0 bl 800155c <HAL_GetTick>
800359c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800359e: e00a b.n 80035b6 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80035a0: f7fd ffdc bl 800155c <HAL_GetTick>
80035a4: 4602 mov r2, r0
80035a6: 68fb ldr r3, [r7, #12]
80035a8: 1ad3 subs r3, r2, r3
80035aa: f241 3288 movw r2, #5000 ; 0x1388
80035ae: 4293 cmp r3, r2
80035b0: d901 bls.n 80035b6 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80035b2: 2303 movs r3, #3
80035b4: e053 b.n 800365e <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80035b6: 4b2d ldr r3, [pc, #180] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
80035b8: 685b ldr r3, [r3, #4]
80035ba: f003 020c and.w r2, r3, #12
80035be: 687b ldr r3, [r7, #4]
80035c0: 685b ldr r3, [r3, #4]
80035c2: 009b lsls r3, r3, #2
80035c4: 429a cmp r2, r3
80035c6: d1eb bne.n 80035a0 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
80035c8: 4b27 ldr r3, [pc, #156] ; (8003668 <HAL_RCC_ClockConfig+0x1c0>)
80035ca: 681b ldr r3, [r3, #0]
80035cc: f003 0307 and.w r3, r3, #7
80035d0: 683a ldr r2, [r7, #0]
80035d2: 429a cmp r2, r3
80035d4: d210 bcs.n 80035f8 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80035d6: 4b24 ldr r3, [pc, #144] ; (8003668 <HAL_RCC_ClockConfig+0x1c0>)
80035d8: 681b ldr r3, [r3, #0]
80035da: f023 0207 bic.w r2, r3, #7
80035de: 4922 ldr r1, [pc, #136] ; (8003668 <HAL_RCC_ClockConfig+0x1c0>)
80035e0: 683b ldr r3, [r7, #0]
80035e2: 4313 orrs r3, r2
80035e4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80035e6: 4b20 ldr r3, [pc, #128] ; (8003668 <HAL_RCC_ClockConfig+0x1c0>)
80035e8: 681b ldr r3, [r3, #0]
80035ea: f003 0307 and.w r3, r3, #7
80035ee: 683a ldr r2, [r7, #0]
80035f0: 429a cmp r2, r3
80035f2: d001 beq.n 80035f8 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
80035f4: 2301 movs r3, #1
80035f6: e032 b.n 800365e <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80035f8: 687b ldr r3, [r7, #4]
80035fa: 681b ldr r3, [r3, #0]
80035fc: f003 0304 and.w r3, r3, #4
8003600: 2b00 cmp r3, #0
8003602: d008 beq.n 8003616 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8003604: 4b19 ldr r3, [pc, #100] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003606: 685b ldr r3, [r3, #4]
8003608: f423 62e0 bic.w r2, r3, #1792 ; 0x700
800360c: 687b ldr r3, [r7, #4]
800360e: 68db ldr r3, [r3, #12]
8003610: 4916 ldr r1, [pc, #88] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003612: 4313 orrs r3, r2
8003614: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8003616: 687b ldr r3, [r7, #4]
8003618: 681b ldr r3, [r3, #0]
800361a: f003 0308 and.w r3, r3, #8
800361e: 2b00 cmp r3, #0
8003620: d009 beq.n 8003636 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8003622: 4b12 ldr r3, [pc, #72] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003624: 685b ldr r3, [r3, #4]
8003626: f423 5260 bic.w r2, r3, #14336 ; 0x3800
800362a: 687b ldr r3, [r7, #4]
800362c: 691b ldr r3, [r3, #16]
800362e: 00db lsls r3, r3, #3
8003630: 490e ldr r1, [pc, #56] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
8003632: 4313 orrs r3, r2
8003634: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8003636: f000 f821 bl 800367c <HAL_RCC_GetSysClockFreq>
800363a: 4601 mov r1, r0
800363c: 4b0b ldr r3, [pc, #44] ; (800366c <HAL_RCC_ClockConfig+0x1c4>)
800363e: 685b ldr r3, [r3, #4]
8003640: 091b lsrs r3, r3, #4
8003642: f003 030f and.w r3, r3, #15
8003646: 4a0a ldr r2, [pc, #40] ; (8003670 <HAL_RCC_ClockConfig+0x1c8>)
8003648: 5cd3 ldrb r3, [r2, r3]
800364a: fa21 f303 lsr.w r3, r1, r3
800364e: 4a09 ldr r2, [pc, #36] ; (8003674 <HAL_RCC_ClockConfig+0x1cc>)
8003650: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8003652: 4b09 ldr r3, [pc, #36] ; (8003678 <HAL_RCC_ClockConfig+0x1d0>)
8003654: 681b ldr r3, [r3, #0]
8003656: 4618 mov r0, r3
8003658: f7fd fe42 bl 80012e0 <HAL_InitTick>
return HAL_OK;
800365c: 2300 movs r3, #0
}
800365e: 4618 mov r0, r3
8003660: 3710 adds r7, #16
8003662: 46bd mov sp, r7
8003664: bd80 pop {r7, pc}
8003666: bf00 nop
8003668: 40022000 .word 0x40022000
800366c: 40021000 .word 0x40021000
8003670: 080081a4 .word 0x080081a4
8003674: 2000000c .word 0x2000000c
8003678: 20000010 .word 0x20000010
0800367c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800367c: b490 push {r4, r7}
800367e: b08a sub sp, #40 ; 0x28
8003680: af00 add r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
8003682: 4b2a ldr r3, [pc, #168] ; (800372c <HAL_RCC_GetSysClockFreq+0xb0>)
8003684: 1d3c adds r4, r7, #4
8003686: cb0f ldmia r3, {r0, r1, r2, r3}
8003688: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
800368c: 4b28 ldr r3, [pc, #160] ; (8003730 <HAL_RCC_GetSysClockFreq+0xb4>)
800368e: 881b ldrh r3, [r3, #0]
8003690: 803b strh r3, [r7, #0]
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
8003692: 2300 movs r3, #0
8003694: 61fb str r3, [r7, #28]
8003696: 2300 movs r3, #0
8003698: 61bb str r3, [r7, #24]
800369a: 2300 movs r3, #0
800369c: 627b str r3, [r7, #36] ; 0x24
800369e: 2300 movs r3, #0
80036a0: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
80036a2: 2300 movs r3, #0
80036a4: 623b str r3, [r7, #32]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
80036a6: 4b23 ldr r3, [pc, #140] ; (8003734 <HAL_RCC_GetSysClockFreq+0xb8>)
80036a8: 685b ldr r3, [r3, #4]
80036aa: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80036ac: 69fb ldr r3, [r7, #28]
80036ae: f003 030c and.w r3, r3, #12
80036b2: 2b04 cmp r3, #4
80036b4: d002 beq.n 80036bc <HAL_RCC_GetSysClockFreq+0x40>
80036b6: 2b08 cmp r3, #8
80036b8: d003 beq.n 80036c2 <HAL_RCC_GetSysClockFreq+0x46>
80036ba: e02d b.n 8003718 <HAL_RCC_GetSysClockFreq+0x9c>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80036bc: 4b1e ldr r3, [pc, #120] ; (8003738 <HAL_RCC_GetSysClockFreq+0xbc>)
80036be: 623b str r3, [r7, #32]
break;
80036c0: e02d b.n 800371e <HAL_RCC_GetSysClockFreq+0xa2>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
80036c2: 69fb ldr r3, [r7, #28]
80036c4: 0c9b lsrs r3, r3, #18
80036c6: f003 030f and.w r3, r3, #15
80036ca: f107 0228 add.w r2, r7, #40 ; 0x28
80036ce: 4413 add r3, r2
80036d0: f813 3c24 ldrb.w r3, [r3, #-36]
80036d4: 617b str r3, [r7, #20]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
80036d6: 69fb ldr r3, [r7, #28]
80036d8: f403 3380 and.w r3, r3, #65536 ; 0x10000
80036dc: 2b00 cmp r3, #0
80036de: d013 beq.n 8003708 <HAL_RCC_GetSysClockFreq+0x8c>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
80036e0: 4b14 ldr r3, [pc, #80] ; (8003734 <HAL_RCC_GetSysClockFreq+0xb8>)
80036e2: 685b ldr r3, [r3, #4]
80036e4: 0c5b lsrs r3, r3, #17
80036e6: f003 0301 and.w r3, r3, #1
80036ea: f107 0228 add.w r2, r7, #40 ; 0x28
80036ee: 4413 add r3, r2
80036f0: f813 3c28 ldrb.w r3, [r3, #-40]
80036f4: 61bb str r3, [r7, #24]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
80036f6: 697b ldr r3, [r7, #20]
80036f8: 4a0f ldr r2, [pc, #60] ; (8003738 <HAL_RCC_GetSysClockFreq+0xbc>)
80036fa: fb02 f203 mul.w r2, r2, r3
80036fe: 69bb ldr r3, [r7, #24]
8003700: fbb2 f3f3 udiv r3, r2, r3
8003704: 627b str r3, [r7, #36] ; 0x24
8003706: e004 b.n 8003712 <HAL_RCC_GetSysClockFreq+0x96>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8003708: 697b ldr r3, [r7, #20]
800370a: 4a0c ldr r2, [pc, #48] ; (800373c <HAL_RCC_GetSysClockFreq+0xc0>)
800370c: fb02 f303 mul.w r3, r2, r3
8003710: 627b str r3, [r7, #36] ; 0x24
}
sysclockfreq = pllclk;
8003712: 6a7b ldr r3, [r7, #36] ; 0x24
8003714: 623b str r3, [r7, #32]
break;
8003716: e002 b.n 800371e <HAL_RCC_GetSysClockFreq+0xa2>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8003718: 4b07 ldr r3, [pc, #28] ; (8003738 <HAL_RCC_GetSysClockFreq+0xbc>)
800371a: 623b str r3, [r7, #32]
break;
800371c: bf00 nop
}
}
return sysclockfreq;
800371e: 6a3b ldr r3, [r7, #32]
}
8003720: 4618 mov r0, r3
8003722: 3728 adds r7, #40 ; 0x28
8003724: 46bd mov sp, r7
8003726: bc90 pop {r4, r7}
8003728: 4770 bx lr
800372a: bf00 nop
800372c: 08008170 .word 0x08008170
8003730: 08008180 .word 0x08008180
8003734: 40021000 .word 0x40021000
8003738: 007a1200 .word 0x007a1200
800373c: 003d0900 .word 0x003d0900
08003740 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8003740: b480 push {r7}
8003742: af00 add r7, sp, #0
return SystemCoreClock;
8003744: 4b02 ldr r3, [pc, #8] ; (8003750 <HAL_RCC_GetHCLKFreq+0x10>)
8003746: 681b ldr r3, [r3, #0]
}
8003748: 4618 mov r0, r3
800374a: 46bd mov sp, r7
800374c: bc80 pop {r7}
800374e: 4770 bx lr
8003750: 2000000c .word 0x2000000c
08003754 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8003754: b580 push {r7, lr}
8003756: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8003758: f7ff fff2 bl 8003740 <HAL_RCC_GetHCLKFreq>
800375c: 4601 mov r1, r0
800375e: 4b05 ldr r3, [pc, #20] ; (8003774 <HAL_RCC_GetPCLK1Freq+0x20>)
8003760: 685b ldr r3, [r3, #4]
8003762: 0a1b lsrs r3, r3, #8
8003764: f003 0307 and.w r3, r3, #7
8003768: 4a03 ldr r2, [pc, #12] ; (8003778 <HAL_RCC_GetPCLK1Freq+0x24>)
800376a: 5cd3 ldrb r3, [r2, r3]
800376c: fa21 f303 lsr.w r3, r1, r3
}
8003770: 4618 mov r0, r3
8003772: bd80 pop {r7, pc}
8003774: 40021000 .word 0x40021000
8003778: 080081b4 .word 0x080081b4
0800377c <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
800377c: b580 push {r7, lr}
800377e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8003780: f7ff ffde bl 8003740 <HAL_RCC_GetHCLKFreq>
8003784: 4601 mov r1, r0
8003786: 4b05 ldr r3, [pc, #20] ; (800379c <HAL_RCC_GetPCLK2Freq+0x20>)
8003788: 685b ldr r3, [r3, #4]
800378a: 0adb lsrs r3, r3, #11
800378c: f003 0307 and.w r3, r3, #7
8003790: 4a03 ldr r2, [pc, #12] ; (80037a0 <HAL_RCC_GetPCLK2Freq+0x24>)
8003792: 5cd3 ldrb r3, [r2, r3]
8003794: fa21 f303 lsr.w r3, r1, r3
}
8003798: 4618 mov r0, r3
800379a: bd80 pop {r7, pc}
800379c: 40021000 .word 0x40021000
80037a0: 080081b4 .word 0x080081b4
080037a4 <HAL_RCC_GetClockConfig>:
* contains the current clock configuration.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
80037a4: b480 push {r7}
80037a6: b083 sub sp, #12
80037a8: af00 add r7, sp, #0
80037aa: 6078 str r0, [r7, #4]
80037ac: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(RCC_ClkInitStruct != NULL);
assert_param(pFLatency != NULL);
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
80037ae: 687b ldr r3, [r7, #4]
80037b0: 220f movs r2, #15
80037b2: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
80037b4: 4b11 ldr r3, [pc, #68] ; (80037fc <HAL_RCC_GetClockConfig+0x58>)
80037b6: 685b ldr r3, [r3, #4]
80037b8: f003 0203 and.w r2, r3, #3
80037bc: 687b ldr r3, [r7, #4]
80037be: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
80037c0: 4b0e ldr r3, [pc, #56] ; (80037fc <HAL_RCC_GetClockConfig+0x58>)
80037c2: 685b ldr r3, [r3, #4]
80037c4: f003 02f0 and.w r2, r3, #240 ; 0xf0
80037c8: 687b ldr r3, [r7, #4]
80037ca: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
80037cc: 4b0b ldr r3, [pc, #44] ; (80037fc <HAL_RCC_GetClockConfig+0x58>)
80037ce: 685b ldr r3, [r3, #4]
80037d0: f403 62e0 and.w r2, r3, #1792 ; 0x700
80037d4: 687b ldr r3, [r7, #4]
80037d6: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
80037d8: 4b08 ldr r3, [pc, #32] ; (80037fc <HAL_RCC_GetClockConfig+0x58>)
80037da: 685b ldr r3, [r3, #4]
80037dc: 08db lsrs r3, r3, #3
80037de: f403 62e0 and.w r2, r3, #1792 ; 0x700
80037e2: 687b ldr r3, [r7, #4]
80037e4: 611a str r2, [r3, #16]
#if defined(FLASH_ACR_LATENCY)
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
80037e6: 4b06 ldr r3, [pc, #24] ; (8003800 <HAL_RCC_GetClockConfig+0x5c>)
80037e8: 681b ldr r3, [r3, #0]
80037ea: f003 0207 and.w r2, r3, #7
80037ee: 683b ldr r3, [r7, #0]
80037f0: 601a str r2, [r3, #0]
#else
/* For VALUE lines devices, only LATENCY_0 can be set*/
*pFLatency = (uint32_t)FLASH_LATENCY_0;
#endif
}
80037f2: bf00 nop
80037f4: 370c adds r7, #12
80037f6: 46bd mov sp, r7
80037f8: bc80 pop {r7}
80037fa: 4770 bx lr
80037fc: 40021000 .word 0x40021000
8003800: 40022000 .word 0x40022000
08003804 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8003804: b480 push {r7}
8003806: b085 sub sp, #20
8003808: af00 add r7, sp, #0
800380a: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
800380c: 4b0a ldr r3, [pc, #40] ; (8003838 <RCC_Delay+0x34>)
800380e: 681b ldr r3, [r3, #0]
8003810: 4a0a ldr r2, [pc, #40] ; (800383c <RCC_Delay+0x38>)
8003812: fba2 2303 umull r2, r3, r2, r3
8003816: 0a5b lsrs r3, r3, #9
8003818: 687a ldr r2, [r7, #4]
800381a: fb02 f303 mul.w r3, r2, r3
800381e: 60fb str r3, [r7, #12]
do
{
__NOP();
8003820: bf00 nop
}
while (Delay --);
8003822: 68fb ldr r3, [r7, #12]
8003824: 1e5a subs r2, r3, #1
8003826: 60fa str r2, [r7, #12]
8003828: 2b00 cmp r3, #0
800382a: d1f9 bne.n 8003820 <RCC_Delay+0x1c>
}
800382c: bf00 nop
800382e: 3714 adds r7, #20
8003830: 46bd mov sp, r7
8003832: bc80 pop {r7}
8003834: 4770 bx lr
8003836: bf00 nop
8003838: 2000000c .word 0x2000000c
800383c: 10624dd3 .word 0x10624dd3
08003840 <HAL_RCCEx_PeriphCLKConfig>:
* manually disable it.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8003840: b580 push {r7, lr}
8003842: b086 sub sp, #24
8003844: af00 add r7, sp, #0
8003846: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U, temp_reg = 0U;
8003848: 2300 movs r3, #0
800384a: 613b str r3, [r7, #16]
800384c: 2300 movs r3, #0
800384e: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
8003850: 687b ldr r3, [r7, #4]
8003852: 681b ldr r3, [r3, #0]
8003854: f003 0301 and.w r3, r3, #1
8003858: 2b00 cmp r3, #0
800385a: d07d beq.n 8003958 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
FlagStatus pwrclkchanged = RESET;
800385c: 2300 movs r3, #0
800385e: 75fb strb r3, [r7, #23]
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8003860: 4b4f ldr r3, [pc, #316] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003862: 69db ldr r3, [r3, #28]
8003864: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003868: 2b00 cmp r3, #0
800386a: d10d bne.n 8003888 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
__HAL_RCC_PWR_CLK_ENABLE();
800386c: 4b4c ldr r3, [pc, #304] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800386e: 69db ldr r3, [r3, #28]
8003870: 4a4b ldr r2, [pc, #300] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003872: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8003876: 61d3 str r3, [r2, #28]
8003878: 4b49 ldr r3, [pc, #292] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800387a: 69db ldr r3, [r3, #28]
800387c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003880: 60bb str r3, [r7, #8]
8003882: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8003884: 2301 movs r3, #1
8003886: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003888: 4b46 ldr r3, [pc, #280] ; (80039a4 <HAL_RCCEx_PeriphCLKConfig+0x164>)
800388a: 681b ldr r3, [r3, #0]
800388c: f403 7380 and.w r3, r3, #256 ; 0x100
8003890: 2b00 cmp r3, #0
8003892: d118 bne.n 80038c6 <HAL_RCCEx_PeriphCLKConfig+0x86>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8003894: 4b43 ldr r3, [pc, #268] ; (80039a4 <HAL_RCCEx_PeriphCLKConfig+0x164>)
8003896: 681b ldr r3, [r3, #0]
8003898: 4a42 ldr r2, [pc, #264] ; (80039a4 <HAL_RCCEx_PeriphCLKConfig+0x164>)
800389a: f443 7380 orr.w r3, r3, #256 ; 0x100
800389e: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80038a0: f7fd fe5c bl 800155c <HAL_GetTick>
80038a4: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80038a6: e008 b.n 80038ba <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80038a8: f7fd fe58 bl 800155c <HAL_GetTick>
80038ac: 4602 mov r2, r0
80038ae: 693b ldr r3, [r7, #16]
80038b0: 1ad3 subs r3, r2, r3
80038b2: 2b64 cmp r3, #100 ; 0x64
80038b4: d901 bls.n 80038ba <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
return HAL_TIMEOUT;
80038b6: 2303 movs r3, #3
80038b8: e06d b.n 8003996 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80038ba: 4b3a ldr r3, [pc, #232] ; (80039a4 <HAL_RCCEx_PeriphCLKConfig+0x164>)
80038bc: 681b ldr r3, [r3, #0]
80038be: f403 7380 and.w r3, r3, #256 ; 0x100
80038c2: 2b00 cmp r3, #0
80038c4: d0f0 beq.n 80038a8 <HAL_RCCEx_PeriphCLKConfig+0x68>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
80038c6: 4b36 ldr r3, [pc, #216] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80038c8: 6a1b ldr r3, [r3, #32]
80038ca: f403 7340 and.w r3, r3, #768 ; 0x300
80038ce: 60fb str r3, [r7, #12]
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
80038d0: 68fb ldr r3, [r7, #12]
80038d2: 2b00 cmp r3, #0
80038d4: d02e beq.n 8003934 <HAL_RCCEx_PeriphCLKConfig+0xf4>
80038d6: 687b ldr r3, [r7, #4]
80038d8: 685b ldr r3, [r3, #4]
80038da: f403 7340 and.w r3, r3, #768 ; 0x300
80038de: 68fa ldr r2, [r7, #12]
80038e0: 429a cmp r2, r3
80038e2: d027 beq.n 8003934 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80038e4: 4b2e ldr r3, [pc, #184] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80038e6: 6a1b ldr r3, [r3, #32]
80038e8: f423 7340 bic.w r3, r3, #768 ; 0x300
80038ec: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80038ee: 4b2e ldr r3, [pc, #184] ; (80039a8 <HAL_RCCEx_PeriphCLKConfig+0x168>)
80038f0: 2201 movs r2, #1
80038f2: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
80038f4: 4b2c ldr r3, [pc, #176] ; (80039a8 <HAL_RCCEx_PeriphCLKConfig+0x168>)
80038f6: 2200 movs r2, #0
80038f8: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
80038fa: 4a29 ldr r2, [pc, #164] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
80038fc: 68fb ldr r3, [r7, #12]
80038fe: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8003900: 68fb ldr r3, [r7, #12]
8003902: f003 0301 and.w r3, r3, #1
8003906: 2b00 cmp r3, #0
8003908: d014 beq.n 8003934 <HAL_RCCEx_PeriphCLKConfig+0xf4>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800390a: f7fd fe27 bl 800155c <HAL_GetTick>
800390e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003910: e00a b.n 8003928 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003912: f7fd fe23 bl 800155c <HAL_GetTick>
8003916: 4602 mov r2, r0
8003918: 693b ldr r3, [r7, #16]
800391a: 1ad3 subs r3, r2, r3
800391c: f241 3288 movw r2, #5000 ; 0x1388
8003920: 4293 cmp r3, r2
8003922: d901 bls.n 8003928 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
return HAL_TIMEOUT;
8003924: 2303 movs r3, #3
8003926: e036 b.n 8003996 <HAL_RCCEx_PeriphCLKConfig+0x156>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003928: 4b1d ldr r3, [pc, #116] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800392a: 6a1b ldr r3, [r3, #32]
800392c: f003 0302 and.w r3, r3, #2
8003930: 2b00 cmp r3, #0
8003932: d0ee beq.n 8003912 <HAL_RCCEx_PeriphCLKConfig+0xd2>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003934: 4b1a ldr r3, [pc, #104] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003936: 6a1b ldr r3, [r3, #32]
8003938: f423 7240 bic.w r2, r3, #768 ; 0x300
800393c: 687b ldr r3, [r7, #4]
800393e: 685b ldr r3, [r3, #4]
8003940: 4917 ldr r1, [pc, #92] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003942: 4313 orrs r3, r2
8003944: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8003946: 7dfb ldrb r3, [r7, #23]
8003948: 2b01 cmp r3, #1
800394a: d105 bne.n 8003958 <HAL_RCCEx_PeriphCLKConfig+0x118>
{
__HAL_RCC_PWR_CLK_DISABLE();
800394c: 4b14 ldr r3, [pc, #80] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
800394e: 69db ldr r3, [r3, #28]
8003950: 4a13 ldr r2, [pc, #76] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003952: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8003956: 61d3 str r3, [r2, #28]
}
}
/*------------------------------ ADC clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003958: 687b ldr r3, [r7, #4]
800395a: 681b ldr r3, [r3, #0]
800395c: f003 0302 and.w r3, r3, #2
8003960: 2b00 cmp r3, #0
8003962: d008 beq.n 8003976 <HAL_RCCEx_PeriphCLKConfig+0x136>
{
/* Check the parameters */
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
/* Configure the ADC clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8003964: 4b0e ldr r3, [pc, #56] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003966: 685b ldr r3, [r3, #4]
8003968: f423 4240 bic.w r2, r3, #49152 ; 0xc000
800396c: 687b ldr r3, [r7, #4]
800396e: 689b ldr r3, [r3, #8]
8003970: 490b ldr r1, [pc, #44] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003972: 4313 orrs r3, r2
8003974: 604b str r3, [r1, #4]
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
/*------------------------------ USB clock Configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8003976: 687b ldr r3, [r7, #4]
8003978: 681b ldr r3, [r3, #0]
800397a: f003 0310 and.w r3, r3, #16
800397e: 2b00 cmp r3, #0
8003980: d008 beq.n 8003994 <HAL_RCCEx_PeriphCLKConfig+0x154>
{
/* Check the parameters */
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8003982: 4b07 ldr r3, [pc, #28] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003984: 685b ldr r3, [r3, #4]
8003986: f423 0280 bic.w r2, r3, #4194304 ; 0x400000
800398a: 687b ldr r3, [r7, #4]
800398c: 68db ldr r3, [r3, #12]
800398e: 4904 ldr r1, [pc, #16] ; (80039a0 <HAL_RCCEx_PeriphCLKConfig+0x160>)
8003990: 4313 orrs r3, r2
8003992: 604b str r3, [r1, #4]
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
return HAL_OK;
8003994: 2300 movs r3, #0
}
8003996: 4618 mov r0, r3
8003998: 3718 adds r7, #24
800399a: 46bd mov sp, r7
800399c: bd80 pop {r7, pc}
800399e: bf00 nop
80039a0: 40021000 .word 0x40021000
80039a4: 40007000 .word 0x40007000
80039a8: 42420440 .word 0x42420440
080039ac <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
80039ac: b580 push {r7, lr}
80039ae: b082 sub sp, #8
80039b0: af00 add r7, sp, #0
80039b2: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
80039b4: 687b ldr r3, [r7, #4]
80039b6: 2b00 cmp r3, #0
80039b8: d101 bne.n 80039be <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
80039ba: 2301 movs r3, #1
80039bc: e053 b.n 8003a66 <HAL_SPI_Init+0xba>
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80039be: 687b ldr r3, [r7, #4]
80039c0: 2200 movs r2, #0
80039c2: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
80039c4: 687b ldr r3, [r7, #4]
80039c6: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
80039ca: b2db uxtb r3, r3
80039cc: 2b00 cmp r3, #0
80039ce: d106 bne.n 80039de <HAL_SPI_Init+0x32>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
80039d0: 687b ldr r3, [r7, #4]
80039d2: 2200 movs r2, #0
80039d4: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
80039d8: 6878 ldr r0, [r7, #4]
80039da: f7fd fb83 bl 80010e4 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
80039de: 687b ldr r3, [r7, #4]
80039e0: 2202 movs r2, #2
80039e2: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80039e6: 687b ldr r3, [r7, #4]
80039e8: 681b ldr r3, [r3, #0]
80039ea: 681a ldr r2, [r3, #0]
80039ec: 687b ldr r3, [r7, #4]
80039ee: 681b ldr r3, [r3, #0]
80039f0: f022 0240 bic.w r2, r2, #64 ; 0x40
80039f4: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
80039f6: 687b ldr r3, [r7, #4]
80039f8: 685a ldr r2, [r3, #4]
80039fa: 687b ldr r3, [r7, #4]
80039fc: 689b ldr r3, [r3, #8]
80039fe: 431a orrs r2, r3
8003a00: 687b ldr r3, [r7, #4]
8003a02: 68db ldr r3, [r3, #12]
8003a04: 431a orrs r2, r3
8003a06: 687b ldr r3, [r7, #4]
8003a08: 691b ldr r3, [r3, #16]
8003a0a: 431a orrs r2, r3
8003a0c: 687b ldr r3, [r7, #4]
8003a0e: 695b ldr r3, [r3, #20]
8003a10: 431a orrs r2, r3
8003a12: 687b ldr r3, [r7, #4]
8003a14: 699b ldr r3, [r3, #24]
8003a16: f403 7300 and.w r3, r3, #512 ; 0x200
8003a1a: 431a orrs r2, r3
8003a1c: 687b ldr r3, [r7, #4]
8003a1e: 69db ldr r3, [r3, #28]
8003a20: 431a orrs r2, r3
8003a22: 687b ldr r3, [r7, #4]
8003a24: 6a1b ldr r3, [r3, #32]
8003a26: ea42 0103 orr.w r1, r2, r3
8003a2a: 687b ldr r3, [r7, #4]
8003a2c: 6a9a ldr r2, [r3, #40] ; 0x28
8003a2e: 687b ldr r3, [r7, #4]
8003a30: 681b ldr r3, [r3, #0]
8003a32: 430a orrs r2, r1
8003a34: 601a str r2, [r3, #0]
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
/* Configure : NSS management */
WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
8003a36: 687b ldr r3, [r7, #4]
8003a38: 699b ldr r3, [r3, #24]
8003a3a: 0c1a lsrs r2, r3, #16
8003a3c: 687b ldr r3, [r7, #4]
8003a3e: 681b ldr r3, [r3, #0]
8003a40: f002 0204 and.w r2, r2, #4
8003a44: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8003a46: 687b ldr r3, [r7, #4]
8003a48: 681b ldr r3, [r3, #0]
8003a4a: 69da ldr r2, [r3, #28]
8003a4c: 687b ldr r3, [r7, #4]
8003a4e: 681b ldr r3, [r3, #0]
8003a50: f422 6200 bic.w r2, r2, #2048 ; 0x800
8003a54: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8003a56: 687b ldr r3, [r7, #4]
8003a58: 2200 movs r2, #0
8003a5a: 655a str r2, [r3, #84] ; 0x54
hspi->State = HAL_SPI_STATE_READY;
8003a5c: 687b ldr r3, [r7, #4]
8003a5e: 2201 movs r2, #1
8003a60: f883 2051 strb.w r2, [r3, #81] ; 0x51
return HAL_OK;
8003a64: 2300 movs r3, #0
}
8003a66: 4618 mov r0, r3
8003a68: 3708 adds r7, #8
8003a6a: 46bd mov sp, r7
8003a6c: bd80 pop {r7, pc}
08003a6e <HAL_SPI_TransmitReceive>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
8003a6e: b580 push {r7, lr}
8003a70: b08c sub sp, #48 ; 0x30
8003a72: af00 add r7, sp, #0
8003a74: 60f8 str r0, [r7, #12]
8003a76: 60b9 str r1, [r7, #8]
8003a78: 607a str r2, [r7, #4]
8003a7a: 807b strh r3, [r7, #2]
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
uint32_t tickstart;
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
8003a7c: 2301 movs r3, #1
8003a7e: 62fb str r3, [r7, #44] ; 0x2c
HAL_StatusTypeDef errorcode = HAL_OK;
8003a80: 2300 movs r3, #0
8003a82: f887 302b strb.w r3, [r7, #43] ; 0x2b
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
8003a86: 68fb ldr r3, [r7, #12]
8003a88: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
8003a8c: 2b01 cmp r3, #1
8003a8e: d101 bne.n 8003a94 <HAL_SPI_TransmitReceive+0x26>
8003a90: 2302 movs r3, #2
8003a92: e18a b.n 8003daa <HAL_SPI_TransmitReceive+0x33c>
8003a94: 68fb ldr r3, [r7, #12]
8003a96: 2201 movs r2, #1
8003a98: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8003a9c: f7fd fd5e bl 800155c <HAL_GetTick>
8003aa0: 6278 str r0, [r7, #36] ; 0x24
/* Init temporary variables */
tmp_state = hspi->State;
8003aa2: 68fb ldr r3, [r7, #12]
8003aa4: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8003aa8: f887 3023 strb.w r3, [r7, #35] ; 0x23
tmp_mode = hspi->Init.Mode;
8003aac: 68fb ldr r3, [r7, #12]
8003aae: 685b ldr r3, [r3, #4]
8003ab0: 61fb str r3, [r7, #28]
initial_TxXferCount = Size;
8003ab2: 887b ldrh r3, [r7, #2]
8003ab4: 837b strh r3, [r7, #26]
if (!((tmp_state == HAL_SPI_STATE_READY) || \
8003ab6: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
8003aba: 2b01 cmp r3, #1
8003abc: d00f beq.n 8003ade <HAL_SPI_TransmitReceive+0x70>
8003abe: 69fb ldr r3, [r7, #28]
8003ac0: f5b3 7f82 cmp.w r3, #260 ; 0x104
8003ac4: d107 bne.n 8003ad6 <HAL_SPI_TransmitReceive+0x68>
((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
8003ac6: 68fb ldr r3, [r7, #12]
8003ac8: 689b ldr r3, [r3, #8]
8003aca: 2b00 cmp r3, #0
8003acc: d103 bne.n 8003ad6 <HAL_SPI_TransmitReceive+0x68>
8003ace: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
8003ad2: 2b04 cmp r3, #4
8003ad4: d003 beq.n 8003ade <HAL_SPI_TransmitReceive+0x70>
{
errorcode = HAL_BUSY;
8003ad6: 2302 movs r3, #2
8003ad8: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8003adc: e15b b.n 8003d96 <HAL_SPI_TransmitReceive+0x328>
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
8003ade: 68bb ldr r3, [r7, #8]
8003ae0: 2b00 cmp r3, #0
8003ae2: d005 beq.n 8003af0 <HAL_SPI_TransmitReceive+0x82>
8003ae4: 687b ldr r3, [r7, #4]
8003ae6: 2b00 cmp r3, #0
8003ae8: d002 beq.n 8003af0 <HAL_SPI_TransmitReceive+0x82>
8003aea: 887b ldrh r3, [r7, #2]
8003aec: 2b00 cmp r3, #0
8003aee: d103 bne.n 8003af8 <HAL_SPI_TransmitReceive+0x8a>
{
errorcode = HAL_ERROR;
8003af0: 2301 movs r3, #1
8003af2: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8003af6: e14e b.n 8003d96 <HAL_SPI_TransmitReceive+0x328>
}
/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
if (hspi->State != HAL_SPI_STATE_BUSY_RX)
8003af8: 68fb ldr r3, [r7, #12]
8003afa: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8003afe: b2db uxtb r3, r3
8003b00: 2b04 cmp r3, #4
8003b02: d003 beq.n 8003b0c <HAL_SPI_TransmitReceive+0x9e>
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
8003b04: 68fb ldr r3, [r7, #12]
8003b06: 2205 movs r2, #5
8003b08: f883 2051 strb.w r2, [r3, #81] ; 0x51
}
/* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8003b0c: 68fb ldr r3, [r7, #12]
8003b0e: 2200 movs r2, #0
8003b10: 655a str r2, [r3, #84] ; 0x54
hspi->pRxBuffPtr = (uint8_t *)pRxData;
8003b12: 68fb ldr r3, [r7, #12]
8003b14: 687a ldr r2, [r7, #4]
8003b16: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount = Size;
8003b18: 68fb ldr r3, [r7, #12]
8003b1a: 887a ldrh r2, [r7, #2]
8003b1c: 87da strh r2, [r3, #62] ; 0x3e
hspi->RxXferSize = Size;
8003b1e: 68fb ldr r3, [r7, #12]
8003b20: 887a ldrh r2, [r7, #2]
8003b22: 879a strh r2, [r3, #60] ; 0x3c
hspi->pTxBuffPtr = (uint8_t *)pTxData;
8003b24: 68fb ldr r3, [r7, #12]
8003b26: 68ba ldr r2, [r7, #8]
8003b28: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount = Size;
8003b2a: 68fb ldr r3, [r7, #12]
8003b2c: 887a ldrh r2, [r7, #2]
8003b2e: 86da strh r2, [r3, #54] ; 0x36
hspi->TxXferSize = Size;
8003b30: 68fb ldr r3, [r7, #12]
8003b32: 887a ldrh r2, [r7, #2]
8003b34: 869a strh r2, [r3, #52] ; 0x34
/*Init field not used in handle to zero */
hspi->RxISR = NULL;
8003b36: 68fb ldr r3, [r7, #12]
8003b38: 2200 movs r2, #0
8003b3a: 641a str r2, [r3, #64] ; 0x40
hspi->TxISR = NULL;
8003b3c: 68fb ldr r3, [r7, #12]
8003b3e: 2200 movs r2, #0
8003b40: 645a str r2, [r3, #68] ; 0x44
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8003b42: 68fb ldr r3, [r7, #12]
8003b44: 681b ldr r3, [r3, #0]
8003b46: 681b ldr r3, [r3, #0]
8003b48: f003 0340 and.w r3, r3, #64 ; 0x40
8003b4c: 2b40 cmp r3, #64 ; 0x40
8003b4e: d007 beq.n 8003b60 <HAL_SPI_TransmitReceive+0xf2>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
8003b50: 68fb ldr r3, [r7, #12]
8003b52: 681b ldr r3, [r3, #0]
8003b54: 681a ldr r2, [r3, #0]
8003b56: 68fb ldr r3, [r7, #12]
8003b58: 681b ldr r3, [r3, #0]
8003b5a: f042 0240 orr.w r2, r2, #64 ; 0x40
8003b5e: 601a str r2, [r3, #0]
}
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
8003b60: 68fb ldr r3, [r7, #12]
8003b62: 68db ldr r3, [r3, #12]
8003b64: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8003b68: d178 bne.n 8003c5c <HAL_SPI_TransmitReceive+0x1ee>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8003b6a: 68fb ldr r3, [r7, #12]
8003b6c: 685b ldr r3, [r3, #4]
8003b6e: 2b00 cmp r3, #0
8003b70: d002 beq.n 8003b78 <HAL_SPI_TransmitReceive+0x10a>
8003b72: 8b7b ldrh r3, [r7, #26]
8003b74: 2b01 cmp r3, #1
8003b76: d166 bne.n 8003c46 <HAL_SPI_TransmitReceive+0x1d8>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8003b78: 68fb ldr r3, [r7, #12]
8003b7a: 6b1b ldr r3, [r3, #48] ; 0x30
8003b7c: 881a ldrh r2, [r3, #0]
8003b7e: 68fb ldr r3, [r7, #12]
8003b80: 681b ldr r3, [r3, #0]
8003b82: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8003b84: 68fb ldr r3, [r7, #12]
8003b86: 6b1b ldr r3, [r3, #48] ; 0x30
8003b88: 1c9a adds r2, r3, #2
8003b8a: 68fb ldr r3, [r7, #12]
8003b8c: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8003b8e: 68fb ldr r3, [r7, #12]
8003b90: 8edb ldrh r3, [r3, #54] ; 0x36
8003b92: b29b uxth r3, r3
8003b94: 3b01 subs r3, #1
8003b96: b29a uxth r2, r3
8003b98: 68fb ldr r3, [r7, #12]
8003b9a: 86da strh r2, [r3, #54] ; 0x36
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8003b9c: e053 b.n 8003c46 <HAL_SPI_TransmitReceive+0x1d8>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
8003b9e: 68fb ldr r3, [r7, #12]
8003ba0: 681b ldr r3, [r3, #0]
8003ba2: 689b ldr r3, [r3, #8]
8003ba4: f003 0302 and.w r3, r3, #2
8003ba8: 2b02 cmp r3, #2
8003baa: d11b bne.n 8003be4 <HAL_SPI_TransmitReceive+0x176>
8003bac: 68fb ldr r3, [r7, #12]
8003bae: 8edb ldrh r3, [r3, #54] ; 0x36
8003bb0: b29b uxth r3, r3
8003bb2: 2b00 cmp r3, #0
8003bb4: d016 beq.n 8003be4 <HAL_SPI_TransmitReceive+0x176>
8003bb6: 6afb ldr r3, [r7, #44] ; 0x2c
8003bb8: 2b01 cmp r3, #1
8003bba: d113 bne.n 8003be4 <HAL_SPI_TransmitReceive+0x176>
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8003bbc: 68fb ldr r3, [r7, #12]
8003bbe: 6b1b ldr r3, [r3, #48] ; 0x30
8003bc0: 881a ldrh r2, [r3, #0]
8003bc2: 68fb ldr r3, [r7, #12]
8003bc4: 681b ldr r3, [r3, #0]
8003bc6: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8003bc8: 68fb ldr r3, [r7, #12]
8003bca: 6b1b ldr r3, [r3, #48] ; 0x30
8003bcc: 1c9a adds r2, r3, #2
8003bce: 68fb ldr r3, [r7, #12]
8003bd0: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8003bd2: 68fb ldr r3, [r7, #12]
8003bd4: 8edb ldrh r3, [r3, #54] ; 0x36
8003bd6: b29b uxth r3, r3
8003bd8: 3b01 subs r3, #1
8003bda: b29a uxth r2, r3
8003bdc: 68fb ldr r3, [r7, #12]
8003bde: 86da strh r2, [r3, #54] ; 0x36
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
8003be0: 2300 movs r3, #0
8003be2: 62fb str r3, [r7, #44] ; 0x2c
}
#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
8003be4: 68fb ldr r3, [r7, #12]
8003be6: 681b ldr r3, [r3, #0]
8003be8: 689b ldr r3, [r3, #8]
8003bea: f003 0301 and.w r3, r3, #1
8003bee: 2b01 cmp r3, #1
8003bf0: d119 bne.n 8003c26 <HAL_SPI_TransmitReceive+0x1b8>
8003bf2: 68fb ldr r3, [r7, #12]
8003bf4: 8fdb ldrh r3, [r3, #62] ; 0x3e
8003bf6: b29b uxth r3, r3
8003bf8: 2b00 cmp r3, #0
8003bfa: d014 beq.n 8003c26 <HAL_SPI_TransmitReceive+0x1b8>
{
*((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
8003bfc: 68fb ldr r3, [r7, #12]
8003bfe: 681b ldr r3, [r3, #0]
8003c00: 68da ldr r2, [r3, #12]
8003c02: 68fb ldr r3, [r7, #12]
8003c04: 6b9b ldr r3, [r3, #56] ; 0x38
8003c06: b292 uxth r2, r2
8003c08: 801a strh r2, [r3, #0]
hspi->pRxBuffPtr += sizeof(uint16_t);
8003c0a: 68fb ldr r3, [r7, #12]
8003c0c: 6b9b ldr r3, [r3, #56] ; 0x38
8003c0e: 1c9a adds r2, r3, #2
8003c10: 68fb ldr r3, [r7, #12]
8003c12: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8003c14: 68fb ldr r3, [r7, #12]
8003c16: 8fdb ldrh r3, [r3, #62] ; 0x3e
8003c18: b29b uxth r3, r3
8003c1a: 3b01 subs r3, #1
8003c1c: b29a uxth r2, r3
8003c1e: 68fb ldr r3, [r7, #12]
8003c20: 87da strh r2, [r3, #62] ; 0x3e
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
8003c22: 2301 movs r3, #1
8003c24: 62fb str r3, [r7, #44] ; 0x2c
}
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
8003c26: f7fd fc99 bl 800155c <HAL_GetTick>
8003c2a: 4602 mov r2, r0
8003c2c: 6a7b ldr r3, [r7, #36] ; 0x24
8003c2e: 1ad3 subs r3, r2, r3
8003c30: 6bba ldr r2, [r7, #56] ; 0x38
8003c32: 429a cmp r2, r3
8003c34: d807 bhi.n 8003c46 <HAL_SPI_TransmitReceive+0x1d8>
8003c36: 6bbb ldr r3, [r7, #56] ; 0x38
8003c38: f1b3 3fff cmp.w r3, #4294967295
8003c3c: d003 beq.n 8003c46 <HAL_SPI_TransmitReceive+0x1d8>
{
errorcode = HAL_TIMEOUT;
8003c3e: 2303 movs r3, #3
8003c40: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8003c44: e0a7 b.n 8003d96 <HAL_SPI_TransmitReceive+0x328>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8003c46: 68fb ldr r3, [r7, #12]
8003c48: 8edb ldrh r3, [r3, #54] ; 0x36
8003c4a: b29b uxth r3, r3
8003c4c: 2b00 cmp r3, #0
8003c4e: d1a6 bne.n 8003b9e <HAL_SPI_TransmitReceive+0x130>
8003c50: 68fb ldr r3, [r7, #12]
8003c52: 8fdb ldrh r3, [r3, #62] ; 0x3e
8003c54: b29b uxth r3, r3
8003c56: 2b00 cmp r3, #0
8003c58: d1a1 bne.n 8003b9e <HAL_SPI_TransmitReceive+0x130>
8003c5a: e07c b.n 8003d56 <HAL_SPI_TransmitReceive+0x2e8>
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8003c5c: 68fb ldr r3, [r7, #12]
8003c5e: 685b ldr r3, [r3, #4]
8003c60: 2b00 cmp r3, #0
8003c62: d002 beq.n 8003c6a <HAL_SPI_TransmitReceive+0x1fc>
8003c64: 8b7b ldrh r3, [r7, #26]
8003c66: 2b01 cmp r3, #1
8003c68: d16b bne.n 8003d42 <HAL_SPI_TransmitReceive+0x2d4>
{
*((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
8003c6a: 68fb ldr r3, [r7, #12]
8003c6c: 6b1a ldr r2, [r3, #48] ; 0x30
8003c6e: 68fb ldr r3, [r7, #12]
8003c70: 681b ldr r3, [r3, #0]
8003c72: 330c adds r3, #12
8003c74: 7812 ldrb r2, [r2, #0]
8003c76: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
8003c78: 68fb ldr r3, [r7, #12]
8003c7a: 6b1b ldr r3, [r3, #48] ; 0x30
8003c7c: 1c5a adds r2, r3, #1
8003c7e: 68fb ldr r3, [r7, #12]
8003c80: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8003c82: 68fb ldr r3, [r7, #12]
8003c84: 8edb ldrh r3, [r3, #54] ; 0x36
8003c86: b29b uxth r3, r3
8003c88: 3b01 subs r3, #1
8003c8a: b29a uxth r2, r3
8003c8c: 68fb ldr r3, [r7, #12]
8003c8e: 86da strh r2, [r3, #54] ; 0x36
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8003c90: e057 b.n 8003d42 <HAL_SPI_TransmitReceive+0x2d4>
{
/* Check TXE flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
8003c92: 68fb ldr r3, [r7, #12]
8003c94: 681b ldr r3, [r3, #0]
8003c96: 689b ldr r3, [r3, #8]
8003c98: f003 0302 and.w r3, r3, #2
8003c9c: 2b02 cmp r3, #2
8003c9e: d11c bne.n 8003cda <HAL_SPI_TransmitReceive+0x26c>
8003ca0: 68fb ldr r3, [r7, #12]
8003ca2: 8edb ldrh r3, [r3, #54] ; 0x36
8003ca4: b29b uxth r3, r3
8003ca6: 2b00 cmp r3, #0
8003ca8: d017 beq.n 8003cda <HAL_SPI_TransmitReceive+0x26c>
8003caa: 6afb ldr r3, [r7, #44] ; 0x2c
8003cac: 2b01 cmp r3, #1
8003cae: d114 bne.n 8003cda <HAL_SPI_TransmitReceive+0x26c>
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
8003cb0: 68fb ldr r3, [r7, #12]
8003cb2: 6b1a ldr r2, [r3, #48] ; 0x30
8003cb4: 68fb ldr r3, [r7, #12]
8003cb6: 681b ldr r3, [r3, #0]
8003cb8: 330c adds r3, #12
8003cba: 7812 ldrb r2, [r2, #0]
8003cbc: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
8003cbe: 68fb ldr r3, [r7, #12]
8003cc0: 6b1b ldr r3, [r3, #48] ; 0x30
8003cc2: 1c5a adds r2, r3, #1
8003cc4: 68fb ldr r3, [r7, #12]
8003cc6: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8003cc8: 68fb ldr r3, [r7, #12]
8003cca: 8edb ldrh r3, [r3, #54] ; 0x36
8003ccc: b29b uxth r3, r3
8003cce: 3b01 subs r3, #1
8003cd0: b29a uxth r2, r3
8003cd2: 68fb ldr r3, [r7, #12]
8003cd4: 86da strh r2, [r3, #54] ; 0x36
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
8003cd6: 2300 movs r3, #0
8003cd8: 62fb str r3, [r7, #44] ; 0x2c
}
#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
8003cda: 68fb ldr r3, [r7, #12]
8003cdc: 681b ldr r3, [r3, #0]
8003cde: 689b ldr r3, [r3, #8]
8003ce0: f003 0301 and.w r3, r3, #1
8003ce4: 2b01 cmp r3, #1
8003ce6: d119 bne.n 8003d1c <HAL_SPI_TransmitReceive+0x2ae>
8003ce8: 68fb ldr r3, [r7, #12]
8003cea: 8fdb ldrh r3, [r3, #62] ; 0x3e
8003cec: b29b uxth r3, r3
8003cee: 2b00 cmp r3, #0
8003cf0: d014 beq.n 8003d1c <HAL_SPI_TransmitReceive+0x2ae>
{
(*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
8003cf2: 68fb ldr r3, [r7, #12]
8003cf4: 681b ldr r3, [r3, #0]
8003cf6: 68da ldr r2, [r3, #12]
8003cf8: 68fb ldr r3, [r7, #12]
8003cfa: 6b9b ldr r3, [r3, #56] ; 0x38
8003cfc: b2d2 uxtb r2, r2
8003cfe: 701a strb r2, [r3, #0]
hspi->pRxBuffPtr++;
8003d00: 68fb ldr r3, [r7, #12]
8003d02: 6b9b ldr r3, [r3, #56] ; 0x38
8003d04: 1c5a adds r2, r3, #1
8003d06: 68fb ldr r3, [r7, #12]
8003d08: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferCount--;
8003d0a: 68fb ldr r3, [r7, #12]
8003d0c: 8fdb ldrh r3, [r3, #62] ; 0x3e
8003d0e: b29b uxth r3, r3
8003d10: 3b01 subs r3, #1
8003d12: b29a uxth r2, r3
8003d14: 68fb ldr r3, [r7, #12]
8003d16: 87da strh r2, [r3, #62] ; 0x3e
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
8003d18: 2301 movs r3, #1
8003d1a: 62fb str r3, [r7, #44] ; 0x2c
}
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
8003d1c: f7fd fc1e bl 800155c <HAL_GetTick>
8003d20: 4602 mov r2, r0
8003d22: 6a7b ldr r3, [r7, #36] ; 0x24
8003d24: 1ad3 subs r3, r2, r3
8003d26: 6bba ldr r2, [r7, #56] ; 0x38
8003d28: 429a cmp r2, r3
8003d2a: d803 bhi.n 8003d34 <HAL_SPI_TransmitReceive+0x2c6>
8003d2c: 6bbb ldr r3, [r7, #56] ; 0x38
8003d2e: f1b3 3fff cmp.w r3, #4294967295
8003d32: d102 bne.n 8003d3a <HAL_SPI_TransmitReceive+0x2cc>
8003d34: 6bbb ldr r3, [r7, #56] ; 0x38
8003d36: 2b00 cmp r3, #0
8003d38: d103 bne.n 8003d42 <HAL_SPI_TransmitReceive+0x2d4>
{
errorcode = HAL_TIMEOUT;
8003d3a: 2303 movs r3, #3
8003d3c: f887 302b strb.w r3, [r7, #43] ; 0x2b
goto error;
8003d40: e029 b.n 8003d96 <HAL_SPI_TransmitReceive+0x328>
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
8003d42: 68fb ldr r3, [r7, #12]
8003d44: 8edb ldrh r3, [r3, #54] ; 0x36
8003d46: b29b uxth r3, r3
8003d48: 2b00 cmp r3, #0
8003d4a: d1a2 bne.n 8003c92 <HAL_SPI_TransmitReceive+0x224>
8003d4c: 68fb ldr r3, [r7, #12]
8003d4e: 8fdb ldrh r3, [r3, #62] ; 0x3e
8003d50: b29b uxth r3, r3
8003d52: 2b00 cmp r3, #0
8003d54: d19d bne.n 8003c92 <HAL_SPI_TransmitReceive+0x224>
}
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
8003d56: 6a7a ldr r2, [r7, #36] ; 0x24
8003d58: 6bb9 ldr r1, [r7, #56] ; 0x38
8003d5a: 68f8 ldr r0, [r7, #12]
8003d5c: f000 f893 bl 8003e86 <SPI_EndRxTxTransaction>
8003d60: 4603 mov r3, r0
8003d62: 2b00 cmp r3, #0
8003d64: d006 beq.n 8003d74 <HAL_SPI_TransmitReceive+0x306>
{
errorcode = HAL_ERROR;
8003d66: 2301 movs r3, #1
8003d68: f887 302b strb.w r3, [r7, #43] ; 0x2b
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
8003d6c: 68fb ldr r3, [r7, #12]
8003d6e: 2220 movs r2, #32
8003d70: 655a str r2, [r3, #84] ; 0x54
goto error;
8003d72: e010 b.n 8003d96 <HAL_SPI_TransmitReceive+0x328>
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
8003d74: 68fb ldr r3, [r7, #12]
8003d76: 689b ldr r3, [r3, #8]
8003d78: 2b00 cmp r3, #0
8003d7a: d10b bne.n 8003d94 <HAL_SPI_TransmitReceive+0x326>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
8003d7c: 2300 movs r3, #0
8003d7e: 617b str r3, [r7, #20]
8003d80: 68fb ldr r3, [r7, #12]
8003d82: 681b ldr r3, [r3, #0]
8003d84: 68db ldr r3, [r3, #12]
8003d86: 617b str r3, [r7, #20]
8003d88: 68fb ldr r3, [r7, #12]
8003d8a: 681b ldr r3, [r3, #0]
8003d8c: 689b ldr r3, [r3, #8]
8003d8e: 617b str r3, [r7, #20]
8003d90: 697b ldr r3, [r7, #20]
8003d92: e000 b.n 8003d96 <HAL_SPI_TransmitReceive+0x328>
}
error :
8003d94: bf00 nop
hspi->State = HAL_SPI_STATE_READY;
8003d96: 68fb ldr r3, [r7, #12]
8003d98: 2201 movs r2, #1
8003d9a: f883 2051 strb.w r2, [r3, #81] ; 0x51
__HAL_UNLOCK(hspi);
8003d9e: 68fb ldr r3, [r7, #12]
8003da0: 2200 movs r2, #0
8003da2: f883 2050 strb.w r2, [r3, #80] ; 0x50
return errorcode;
8003da6: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
}
8003daa: 4618 mov r0, r3
8003dac: 3730 adds r7, #48 ; 0x30
8003dae: 46bd mov sp, r7
8003db0: bd80 pop {r7, pc}
08003db2 <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
8003db2: b580 push {r7, lr}
8003db4: b084 sub sp, #16
8003db6: af00 add r7, sp, #0
8003db8: 60f8 str r0, [r7, #12]
8003dba: 60b9 str r1, [r7, #8]
8003dbc: 603b str r3, [r7, #0]
8003dbe: 4613 mov r3, r2
8003dc0: 71fb strb r3, [r7, #7]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8003dc2: e04c b.n 8003e5e <SPI_WaitFlagStateUntilTimeout+0xac>
{
if (Timeout != HAL_MAX_DELAY)
8003dc4: 683b ldr r3, [r7, #0]
8003dc6: f1b3 3fff cmp.w r3, #4294967295
8003dca: d048 beq.n 8003e5e <SPI_WaitFlagStateUntilTimeout+0xac>
{
if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
8003dcc: f7fd fbc6 bl 800155c <HAL_GetTick>
8003dd0: 4602 mov r2, r0
8003dd2: 69bb ldr r3, [r7, #24]
8003dd4: 1ad3 subs r3, r2, r3
8003dd6: 683a ldr r2, [r7, #0]
8003dd8: 429a cmp r2, r3
8003dda: d902 bls.n 8003de2 <SPI_WaitFlagStateUntilTimeout+0x30>
8003ddc: 683b ldr r3, [r7, #0]
8003dde: 2b00 cmp r3, #0
8003de0: d13d bne.n 8003e5e <SPI_WaitFlagStateUntilTimeout+0xac>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8003de2: 68fb ldr r3, [r7, #12]
8003de4: 681b ldr r3, [r3, #0]
8003de6: 685a ldr r2, [r3, #4]
8003de8: 68fb ldr r3, [r7, #12]
8003dea: 681b ldr r3, [r3, #0]
8003dec: f022 02e0 bic.w r2, r2, #224 ; 0xe0
8003df0: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8003df2: 68fb ldr r3, [r7, #12]
8003df4: 685b ldr r3, [r3, #4]
8003df6: f5b3 7f82 cmp.w r3, #260 ; 0x104
8003dfa: d111 bne.n 8003e20 <SPI_WaitFlagStateUntilTimeout+0x6e>
8003dfc: 68fb ldr r3, [r7, #12]
8003dfe: 689b ldr r3, [r3, #8]
8003e00: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8003e04: d004 beq.n 8003e10 <SPI_WaitFlagStateUntilTimeout+0x5e>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
8003e06: 68fb ldr r3, [r7, #12]
8003e08: 689b ldr r3, [r3, #8]
8003e0a: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8003e0e: d107 bne.n 8003e20 <SPI_WaitFlagStateUntilTimeout+0x6e>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8003e10: 68fb ldr r3, [r7, #12]
8003e12: 681b ldr r3, [r3, #0]
8003e14: 681a ldr r2, [r3, #0]
8003e16: 68fb ldr r3, [r7, #12]
8003e18: 681b ldr r3, [r3, #0]
8003e1a: f022 0240 bic.w r2, r2, #64 ; 0x40
8003e1e: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8003e20: 68fb ldr r3, [r7, #12]
8003e22: 6a9b ldr r3, [r3, #40] ; 0x28
8003e24: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8003e28: d10f bne.n 8003e4a <SPI_WaitFlagStateUntilTimeout+0x98>
{
SPI_RESET_CRC(hspi);
8003e2a: 68fb ldr r3, [r7, #12]
8003e2c: 681b ldr r3, [r3, #0]
8003e2e: 681a ldr r2, [r3, #0]
8003e30: 68fb ldr r3, [r7, #12]
8003e32: 681b ldr r3, [r3, #0]
8003e34: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8003e38: 601a str r2, [r3, #0]
8003e3a: 68fb ldr r3, [r7, #12]
8003e3c: 681b ldr r3, [r3, #0]
8003e3e: 681a ldr r2, [r3, #0]
8003e40: 68fb ldr r3, [r7, #12]
8003e42: 681b ldr r3, [r3, #0]
8003e44: f442 5200 orr.w r2, r2, #8192 ; 0x2000
8003e48: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
8003e4a: 68fb ldr r3, [r7, #12]
8003e4c: 2201 movs r2, #1
8003e4e: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8003e52: 68fb ldr r3, [r7, #12]
8003e54: 2200 movs r2, #0
8003e56: f883 2050 strb.w r2, [r3, #80] ; 0x50
return HAL_TIMEOUT;
8003e5a: 2303 movs r3, #3
8003e5c: e00f b.n 8003e7e <SPI_WaitFlagStateUntilTimeout+0xcc>
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8003e5e: 68fb ldr r3, [r7, #12]
8003e60: 681b ldr r3, [r3, #0]
8003e62: 689a ldr r2, [r3, #8]
8003e64: 68bb ldr r3, [r7, #8]
8003e66: 4013 ands r3, r2
8003e68: 68ba ldr r2, [r7, #8]
8003e6a: 429a cmp r2, r3
8003e6c: bf0c ite eq
8003e6e: 2301 moveq r3, #1
8003e70: 2300 movne r3, #0
8003e72: b2db uxtb r3, r3
8003e74: 461a mov r2, r3
8003e76: 79fb ldrb r3, [r7, #7]
8003e78: 429a cmp r2, r3
8003e7a: d1a3 bne.n 8003dc4 <SPI_WaitFlagStateUntilTimeout+0x12>
}
}
}
return HAL_OK;
8003e7c: 2300 movs r3, #0
}
8003e7e: 4618 mov r0, r3
8003e80: 3710 adds r7, #16
8003e82: 46bd mov sp, r7
8003e84: bd80 pop {r7, pc}
08003e86 <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
8003e86: b580 push {r7, lr}
8003e88: b086 sub sp, #24
8003e8a: af02 add r7, sp, #8
8003e8c: 60f8 str r0, [r7, #12]
8003e8e: 60b9 str r1, [r7, #8]
8003e90: 607a str r2, [r7, #4]
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8003e92: 687b ldr r3, [r7, #4]
8003e94: 9300 str r3, [sp, #0]
8003e96: 68bb ldr r3, [r7, #8]
8003e98: 2200 movs r2, #0
8003e9a: 2180 movs r1, #128 ; 0x80
8003e9c: 68f8 ldr r0, [r7, #12]
8003e9e: f7ff ff88 bl 8003db2 <SPI_WaitFlagStateUntilTimeout>
8003ea2: 4603 mov r3, r0
8003ea4: 2b00 cmp r3, #0
8003ea6: d007 beq.n 8003eb8 <SPI_EndRxTxTransaction+0x32>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8003ea8: 68fb ldr r3, [r7, #12]
8003eaa: 6d5b ldr r3, [r3, #84] ; 0x54
8003eac: f043 0220 orr.w r2, r3, #32
8003eb0: 68fb ldr r3, [r7, #12]
8003eb2: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
8003eb4: 2303 movs r3, #3
8003eb6: e000 b.n 8003eba <SPI_EndRxTxTransaction+0x34>
}
return HAL_OK;
8003eb8: 2300 movs r3, #0
}
8003eba: 4618 mov r0, r3
8003ebc: 3710 adds r7, #16
8003ebe: 46bd mov sp, r7
8003ec0: bd80 pop {r7, pc}
08003ec2 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8003ec2: b580 push {r7, lr}
8003ec4: b082 sub sp, #8
8003ec6: af00 add r7, sp, #0
8003ec8: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 2b00 cmp r3, #0
8003ece: d101 bne.n 8003ed4 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8003ed0: 2301 movs r3, #1
8003ed2: e01d b.n 8003f10 <HAL_TIM_Base_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8003ed4: 687b ldr r3, [r7, #4]
8003ed6: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8003eda: b2db uxtb r3, r3
8003edc: 2b00 cmp r3, #0
8003ede: d106 bne.n 8003eee <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8003ee0: 687b ldr r3, [r7, #4]
8003ee2: 2200 movs r2, #0
8003ee4: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8003ee8: 6878 ldr r0, [r7, #4]
8003eea: f000 f815 bl 8003f18 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003eee: 687b ldr r3, [r7, #4]
8003ef0: 2202 movs r2, #2
8003ef2: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003ef6: 687b ldr r3, [r7, #4]
8003ef8: 681a ldr r2, [r3, #0]
8003efa: 687b ldr r3, [r7, #4]
8003efc: 3304 adds r3, #4
8003efe: 4619 mov r1, r3
8003f00: 4610 mov r0, r2
8003f02: f000 f961 bl 80041c8 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003f06: 687b ldr r3, [r7, #4]
8003f08: 2201 movs r2, #1
8003f0a: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8003f0e: 2300 movs r3, #0
}
8003f10: 4618 mov r0, r3
8003f12: 3708 adds r7, #8
8003f14: 46bd mov sp, r7
8003f16: bd80 pop {r7, pc}
08003f18 <HAL_TIM_Base_MspInit>:
* @brief Initializes the TIM Base MSP.
* @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
8003f18: b480 push {r7}
8003f1a: b083 sub sp, #12
8003f1c: af00 add r7, sp, #0
8003f1e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
8003f20: bf00 nop
8003f22: 370c adds r7, #12
8003f24: 46bd mov sp, r7
8003f26: bc80 pop {r7}
8003f28: 4770 bx lr
08003f2a <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8003f2a: b480 push {r7}
8003f2c: b085 sub sp, #20
8003f2e: af00 add r7, sp, #0
8003f30: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8003f32: 687b ldr r3, [r7, #4]
8003f34: 681b ldr r3, [r3, #0]
8003f36: 68da ldr r2, [r3, #12]
8003f38: 687b ldr r3, [r7, #4]
8003f3a: 681b ldr r3, [r3, #0]
8003f3c: f042 0201 orr.w r2, r2, #1
8003f40: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8003f42: 687b ldr r3, [r7, #4]
8003f44: 681b ldr r3, [r3, #0]
8003f46: 689b ldr r3, [r3, #8]
8003f48: f003 0307 and.w r3, r3, #7
8003f4c: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003f4e: 68fb ldr r3, [r7, #12]
8003f50: 2b06 cmp r3, #6
8003f52: d007 beq.n 8003f64 <HAL_TIM_Base_Start_IT+0x3a>
{
__HAL_TIM_ENABLE(htim);
8003f54: 687b ldr r3, [r7, #4]
8003f56: 681b ldr r3, [r3, #0]
8003f58: 681a ldr r2, [r3, #0]
8003f5a: 687b ldr r3, [r7, #4]
8003f5c: 681b ldr r3, [r3, #0]
8003f5e: f042 0201 orr.w r2, r2, #1
8003f62: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8003f64: 2300 movs r3, #0
}
8003f66: 4618 mov r0, r3
8003f68: 3714 adds r7, #20
8003f6a: 46bd mov sp, r7
8003f6c: bc80 pop {r7}
8003f6e: 4770 bx lr
08003f70 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8003f70: b580 push {r7, lr}
8003f72: b082 sub sp, #8
8003f74: af00 add r7, sp, #0
8003f76: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8003f78: 687b ldr r3, [r7, #4]
8003f7a: 681b ldr r3, [r3, #0]
8003f7c: 691b ldr r3, [r3, #16]
8003f7e: f003 0302 and.w r3, r3, #2
8003f82: 2b02 cmp r3, #2
8003f84: d122 bne.n 8003fcc <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8003f86: 687b ldr r3, [r7, #4]
8003f88: 681b ldr r3, [r3, #0]
8003f8a: 68db ldr r3, [r3, #12]
8003f8c: f003 0302 and.w r3, r3, #2
8003f90: 2b02 cmp r3, #2
8003f92: d11b bne.n 8003fcc <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8003f94: 687b ldr r3, [r7, #4]
8003f96: 681b ldr r3, [r3, #0]
8003f98: f06f 0202 mvn.w r2, #2
8003f9c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8003f9e: 687b ldr r3, [r7, #4]
8003fa0: 2201 movs r2, #1
8003fa2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8003fa4: 687b ldr r3, [r7, #4]
8003fa6: 681b ldr r3, [r3, #0]
8003fa8: 699b ldr r3, [r3, #24]
8003faa: f003 0303 and.w r3, r3, #3
8003fae: 2b00 cmp r3, #0
8003fb0: d003 beq.n 8003fba <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003fb2: 6878 ldr r0, [r7, #4]
8003fb4: f000 f8ed bl 8004192 <HAL_TIM_IC_CaptureCallback>
8003fb8: e005 b.n 8003fc6 <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003fba: 6878 ldr r0, [r7, #4]
8003fbc: f000 f8e0 bl 8004180 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003fc0: 6878 ldr r0, [r7, #4]
8003fc2: f000 f8ef bl 80041a4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003fc6: 687b ldr r3, [r7, #4]
8003fc8: 2200 movs r2, #0
8003fca: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8003fcc: 687b ldr r3, [r7, #4]
8003fce: 681b ldr r3, [r3, #0]
8003fd0: 691b ldr r3, [r3, #16]
8003fd2: f003 0304 and.w r3, r3, #4
8003fd6: 2b04 cmp r3, #4
8003fd8: d122 bne.n 8004020 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8003fda: 687b ldr r3, [r7, #4]
8003fdc: 681b ldr r3, [r3, #0]
8003fde: 68db ldr r3, [r3, #12]
8003fe0: f003 0304 and.w r3, r3, #4
8003fe4: 2b04 cmp r3, #4
8003fe6: d11b bne.n 8004020 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8003fe8: 687b ldr r3, [r7, #4]
8003fea: 681b ldr r3, [r3, #0]
8003fec: f06f 0204 mvn.w r2, #4
8003ff0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8003ff2: 687b ldr r3, [r7, #4]
8003ff4: 2202 movs r2, #2
8003ff6: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8003ff8: 687b ldr r3, [r7, #4]
8003ffa: 681b ldr r3, [r3, #0]
8003ffc: 699b ldr r3, [r3, #24]
8003ffe: f403 7340 and.w r3, r3, #768 ; 0x300
8004002: 2b00 cmp r3, #0
8004004: d003 beq.n 800400e <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8004006: 6878 ldr r0, [r7, #4]
8004008: f000 f8c3 bl 8004192 <HAL_TIM_IC_CaptureCallback>
800400c: e005 b.n 800401a <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800400e: 6878 ldr r0, [r7, #4]
8004010: f000 f8b6 bl 8004180 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004014: 6878 ldr r0, [r7, #4]
8004016: f000 f8c5 bl 80041a4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800401a: 687b ldr r3, [r7, #4]
800401c: 2200 movs r2, #0
800401e: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8004020: 687b ldr r3, [r7, #4]
8004022: 681b ldr r3, [r3, #0]
8004024: 691b ldr r3, [r3, #16]
8004026: f003 0308 and.w r3, r3, #8
800402a: 2b08 cmp r3, #8
800402c: d122 bne.n 8004074 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
800402e: 687b ldr r3, [r7, #4]
8004030: 681b ldr r3, [r3, #0]
8004032: 68db ldr r3, [r3, #12]
8004034: f003 0308 and.w r3, r3, #8
8004038: 2b08 cmp r3, #8
800403a: d11b bne.n 8004074 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
800403c: 687b ldr r3, [r7, #4]
800403e: 681b ldr r3, [r3, #0]
8004040: f06f 0208 mvn.w r2, #8
8004044: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8004046: 687b ldr r3, [r7, #4]
8004048: 2204 movs r2, #4
800404a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
800404c: 687b ldr r3, [r7, #4]
800404e: 681b ldr r3, [r3, #0]
8004050: 69db ldr r3, [r3, #28]
8004052: f003 0303 and.w r3, r3, #3
8004056: 2b00 cmp r3, #0
8004058: d003 beq.n 8004062 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800405a: 6878 ldr r0, [r7, #4]
800405c: f000 f899 bl 8004192 <HAL_TIM_IC_CaptureCallback>
8004060: e005 b.n 800406e <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8004062: 6878 ldr r0, [r7, #4]
8004064: f000 f88c bl 8004180 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004068: 6878 ldr r0, [r7, #4]
800406a: f000 f89b bl 80041a4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800406e: 687b ldr r3, [r7, #4]
8004070: 2200 movs r2, #0
8004072: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8004074: 687b ldr r3, [r7, #4]
8004076: 681b ldr r3, [r3, #0]
8004078: 691b ldr r3, [r3, #16]
800407a: f003 0310 and.w r3, r3, #16
800407e: 2b10 cmp r3, #16
8004080: d122 bne.n 80040c8 <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8004082: 687b ldr r3, [r7, #4]
8004084: 681b ldr r3, [r3, #0]
8004086: 68db ldr r3, [r3, #12]
8004088: f003 0310 and.w r3, r3, #16
800408c: 2b10 cmp r3, #16
800408e: d11b bne.n 80040c8 <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8004090: 687b ldr r3, [r7, #4]
8004092: 681b ldr r3, [r3, #0]
8004094: f06f 0210 mvn.w r2, #16
8004098: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
800409a: 687b ldr r3, [r7, #4]
800409c: 2208 movs r2, #8
800409e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
80040a0: 687b ldr r3, [r7, #4]
80040a2: 681b ldr r3, [r3, #0]
80040a4: 69db ldr r3, [r3, #28]
80040a6: f403 7340 and.w r3, r3, #768 ; 0x300
80040aa: 2b00 cmp r3, #0
80040ac: d003 beq.n 80040b6 <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80040ae: 6878 ldr r0, [r7, #4]
80040b0: f000 f86f bl 8004192 <HAL_TIM_IC_CaptureCallback>
80040b4: e005 b.n 80040c2 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80040b6: 6878 ldr r0, [r7, #4]
80040b8: f000 f862 bl 8004180 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80040bc: 6878 ldr r0, [r7, #4]
80040be: f000 f871 bl 80041a4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80040c2: 687b ldr r3, [r7, #4]
80040c4: 2200 movs r2, #0
80040c6: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
80040c8: 687b ldr r3, [r7, #4]
80040ca: 681b ldr r3, [r3, #0]
80040cc: 691b ldr r3, [r3, #16]
80040ce: f003 0301 and.w r3, r3, #1
80040d2: 2b01 cmp r3, #1
80040d4: d10e bne.n 80040f4 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
80040d6: 687b ldr r3, [r7, #4]
80040d8: 681b ldr r3, [r3, #0]
80040da: 68db ldr r3, [r3, #12]
80040dc: f003 0301 and.w r3, r3, #1
80040e0: 2b01 cmp r3, #1
80040e2: d107 bne.n 80040f4 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
80040e4: 687b ldr r3, [r7, #4]
80040e6: 681b ldr r3, [r3, #0]
80040e8: f06f 0201 mvn.w r2, #1
80040ec: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
80040ee: 6878 ldr r0, [r7, #4]
80040f0: f7fc ff70 bl 8000fd4 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
80040f4: 687b ldr r3, [r7, #4]
80040f6: 681b ldr r3, [r3, #0]
80040f8: 691b ldr r3, [r3, #16]
80040fa: f003 0380 and.w r3, r3, #128 ; 0x80
80040fe: 2b80 cmp r3, #128 ; 0x80
8004100: d10e bne.n 8004120 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8004102: 687b ldr r3, [r7, #4]
8004104: 681b ldr r3, [r3, #0]
8004106: 68db ldr r3, [r3, #12]
8004108: f003 0380 and.w r3, r3, #128 ; 0x80
800410c: 2b80 cmp r3, #128 ; 0x80
800410e: d107 bne.n 8004120 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8004110: 687b ldr r3, [r7, #4]
8004112: 681b ldr r3, [r3, #0]
8004114: f06f 0280 mvn.w r2, #128 ; 0x80
8004118: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
800411a: 6878 ldr r0, [r7, #4]
800411c: f000 f8bf bl 800429e <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8004120: 687b ldr r3, [r7, #4]
8004122: 681b ldr r3, [r3, #0]
8004124: 691b ldr r3, [r3, #16]
8004126: f003 0340 and.w r3, r3, #64 ; 0x40
800412a: 2b40 cmp r3, #64 ; 0x40
800412c: d10e bne.n 800414c <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
800412e: 687b ldr r3, [r7, #4]
8004130: 681b ldr r3, [r3, #0]
8004132: 68db ldr r3, [r3, #12]
8004134: f003 0340 and.w r3, r3, #64 ; 0x40
8004138: 2b40 cmp r3, #64 ; 0x40
800413a: d107 bne.n 800414c <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
800413c: 687b ldr r3, [r7, #4]
800413e: 681b ldr r3, [r3, #0]
8004140: f06f 0240 mvn.w r2, #64 ; 0x40
8004144: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8004146: 6878 ldr r0, [r7, #4]
8004148: f000 f835 bl 80041b6 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
800414c: 687b ldr r3, [r7, #4]
800414e: 681b ldr r3, [r3, #0]
8004150: 691b ldr r3, [r3, #16]
8004152: f003 0320 and.w r3, r3, #32
8004156: 2b20 cmp r3, #32
8004158: d10e bne.n 8004178 <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
800415a: 687b ldr r3, [r7, #4]
800415c: 681b ldr r3, [r3, #0]
800415e: 68db ldr r3, [r3, #12]
8004160: f003 0320 and.w r3, r3, #32
8004164: 2b20 cmp r3, #32
8004166: d107 bne.n 8004178 <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8004168: 687b ldr r3, [r7, #4]
800416a: 681b ldr r3, [r3, #0]
800416c: f06f 0220 mvn.w r2, #32
8004170: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8004172: 6878 ldr r0, [r7, #4]
8004174: f000 f88a bl 800428c <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8004178: bf00 nop
800417a: 3708 adds r7, #8
800417c: 46bd mov sp, r7
800417e: bd80 pop {r7, pc}
08004180 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8004180: b480 push {r7}
8004182: b083 sub sp, #12
8004184: af00 add r7, sp, #0
8004186: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8004188: bf00 nop
800418a: 370c adds r7, #12
800418c: 46bd mov sp, r7
800418e: bc80 pop {r7}
8004190: 4770 bx lr
08004192 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8004192: b480 push {r7}
8004194: b083 sub sp, #12
8004196: af00 add r7, sp, #0
8004198: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
800419a: bf00 nop
800419c: 370c adds r7, #12
800419e: 46bd mov sp, r7
80041a0: bc80 pop {r7}
80041a2: 4770 bx lr
080041a4 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
80041a4: b480 push {r7}
80041a6: b083 sub sp, #12
80041a8: af00 add r7, sp, #0
80041aa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
80041ac: bf00 nop
80041ae: 370c adds r7, #12
80041b0: 46bd mov sp, r7
80041b2: bc80 pop {r7}
80041b4: 4770 bx lr
080041b6 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
80041b6: b480 push {r7}
80041b8: b083 sub sp, #12
80041ba: af00 add r7, sp, #0
80041bc: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
80041be: bf00 nop
80041c0: 370c adds r7, #12
80041c2: 46bd mov sp, r7
80041c4: bc80 pop {r7}
80041c6: 4770 bx lr
080041c8 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
80041c8: b480 push {r7}
80041ca: b085 sub sp, #20
80041cc: af00 add r7, sp, #0
80041ce: 6078 str r0, [r7, #4]
80041d0: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
80041d2: 687b ldr r3, [r7, #4]
80041d4: 681b ldr r3, [r3, #0]
80041d6: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
80041d8: 687b ldr r3, [r7, #4]
80041da: 4a29 ldr r2, [pc, #164] ; (8004280 <TIM_Base_SetConfig+0xb8>)
80041dc: 4293 cmp r3, r2
80041de: d00b beq.n 80041f8 <TIM_Base_SetConfig+0x30>
80041e0: 687b ldr r3, [r7, #4]
80041e2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80041e6: d007 beq.n 80041f8 <TIM_Base_SetConfig+0x30>
80041e8: 687b ldr r3, [r7, #4]
80041ea: 4a26 ldr r2, [pc, #152] ; (8004284 <TIM_Base_SetConfig+0xbc>)
80041ec: 4293 cmp r3, r2
80041ee: d003 beq.n 80041f8 <TIM_Base_SetConfig+0x30>
80041f0: 687b ldr r3, [r7, #4]
80041f2: 4a25 ldr r2, [pc, #148] ; (8004288 <TIM_Base_SetConfig+0xc0>)
80041f4: 4293 cmp r3, r2
80041f6: d108 bne.n 800420a <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
80041f8: 68fb ldr r3, [r7, #12]
80041fa: f023 0370 bic.w r3, r3, #112 ; 0x70
80041fe: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8004200: 683b ldr r3, [r7, #0]
8004202: 685b ldr r3, [r3, #4]
8004204: 68fa ldr r2, [r7, #12]
8004206: 4313 orrs r3, r2
8004208: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800420a: 687b ldr r3, [r7, #4]
800420c: 4a1c ldr r2, [pc, #112] ; (8004280 <TIM_Base_SetConfig+0xb8>)
800420e: 4293 cmp r3, r2
8004210: d00b beq.n 800422a <TIM_Base_SetConfig+0x62>
8004212: 687b ldr r3, [r7, #4]
8004214: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8004218: d007 beq.n 800422a <TIM_Base_SetConfig+0x62>
800421a: 687b ldr r3, [r7, #4]
800421c: 4a19 ldr r2, [pc, #100] ; (8004284 <TIM_Base_SetConfig+0xbc>)
800421e: 4293 cmp r3, r2
8004220: d003 beq.n 800422a <TIM_Base_SetConfig+0x62>
8004222: 687b ldr r3, [r7, #4]
8004224: 4a18 ldr r2, [pc, #96] ; (8004288 <TIM_Base_SetConfig+0xc0>)
8004226: 4293 cmp r3, r2
8004228: d108 bne.n 800423c <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800422a: 68fb ldr r3, [r7, #12]
800422c: f423 7340 bic.w r3, r3, #768 ; 0x300
8004230: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8004232: 683b ldr r3, [r7, #0]
8004234: 68db ldr r3, [r3, #12]
8004236: 68fa ldr r2, [r7, #12]
8004238: 4313 orrs r3, r2
800423a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800423c: 68fb ldr r3, [r7, #12]
800423e: f023 0280 bic.w r2, r3, #128 ; 0x80
8004242: 683b ldr r3, [r7, #0]
8004244: 695b ldr r3, [r3, #20]
8004246: 4313 orrs r3, r2
8004248: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800424a: 687b ldr r3, [r7, #4]
800424c: 68fa ldr r2, [r7, #12]
800424e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8004250: 683b ldr r3, [r7, #0]
8004252: 689a ldr r2, [r3, #8]
8004254: 687b ldr r3, [r7, #4]
8004256: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8004258: 683b ldr r3, [r7, #0]
800425a: 681a ldr r2, [r3, #0]
800425c: 687b ldr r3, [r7, #4]
800425e: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8004260: 687b ldr r3, [r7, #4]
8004262: 4a07 ldr r2, [pc, #28] ; (8004280 <TIM_Base_SetConfig+0xb8>)
8004264: 4293 cmp r3, r2
8004266: d103 bne.n 8004270 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8004268: 683b ldr r3, [r7, #0]
800426a: 691a ldr r2, [r3, #16]
800426c: 687b ldr r3, [r7, #4]
800426e: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8004270: 687b ldr r3, [r7, #4]
8004272: 2201 movs r2, #1
8004274: 615a str r2, [r3, #20]
}
8004276: bf00 nop
8004278: 3714 adds r7, #20
800427a: 46bd mov sp, r7
800427c: bc80 pop {r7}
800427e: 4770 bx lr
8004280: 40012c00 .word 0x40012c00
8004284: 40000400 .word 0x40000400
8004288: 40000800 .word 0x40000800
0800428c <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
800428c: b480 push {r7}
800428e: b083 sub sp, #12
8004290: af00 add r7, sp, #0
8004292: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8004294: bf00 nop
8004296: 370c adds r7, #12
8004298: 46bd mov sp, r7
800429a: bc80 pop {r7}
800429c: 4770 bx lr
0800429e <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
800429e: b480 push {r7}
80042a0: b083 sub sp, #12
80042a2: af00 add r7, sp, #0
80042a4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
80042a6: bf00 nop
80042a8: 370c adds r7, #12
80042aa: 46bd mov sp, r7
80042ac: bc80 pop {r7}
80042ae: 4770 bx lr
080042b0 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80042b0: b580 push {r7, lr}
80042b2: b082 sub sp, #8
80042b4: af00 add r7, sp, #0
80042b6: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80042b8: 687b ldr r3, [r7, #4]
80042ba: 2b00 cmp r3, #0
80042bc: d101 bne.n 80042c2 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80042be: 2301 movs r3, #1
80042c0: e03f b.n 8004342 <HAL_UART_Init+0x92>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
80042c2: 687b ldr r3, [r7, #4]
80042c4: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
80042c8: b2db uxtb r3, r3
80042ca: 2b00 cmp r3, #0
80042cc: d106 bne.n 80042dc <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80042ce: 687b ldr r3, [r7, #4]
80042d0: 2200 movs r2, #0
80042d2: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80042d6: 6878 ldr r0, [r7, #4]
80042d8: f7fc ff4e bl 8001178 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80042dc: 687b ldr r3, [r7, #4]
80042de: 2224 movs r2, #36 ; 0x24
80042e0: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
80042e4: 687b ldr r3, [r7, #4]
80042e6: 681b ldr r3, [r3, #0]
80042e8: 68da ldr r2, [r3, #12]
80042ea: 687b ldr r3, [r7, #4]
80042ec: 681b ldr r3, [r3, #0]
80042ee: f422 5200 bic.w r2, r2, #8192 ; 0x2000
80042f2: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
80042f4: 6878 ldr r0, [r7, #4]
80042f6: f000 fcb5 bl 8004c64 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80042fa: 687b ldr r3, [r7, #4]
80042fc: 681b ldr r3, [r3, #0]
80042fe: 691a ldr r2, [r3, #16]
8004300: 687b ldr r3, [r7, #4]
8004302: 681b ldr r3, [r3, #0]
8004304: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8004308: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800430a: 687b ldr r3, [r7, #4]
800430c: 681b ldr r3, [r3, #0]
800430e: 695a ldr r2, [r3, #20]
8004310: 687b ldr r3, [r7, #4]
8004312: 681b ldr r3, [r3, #0]
8004314: f022 022a bic.w r2, r2, #42 ; 0x2a
8004318: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
800431a: 687b ldr r3, [r7, #4]
800431c: 681b ldr r3, [r3, #0]
800431e: 68da ldr r2, [r3, #12]
8004320: 687b ldr r3, [r7, #4]
8004322: 681b ldr r3, [r3, #0]
8004324: f442 5200 orr.w r2, r2, #8192 ; 0x2000
8004328: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800432a: 687b ldr r3, [r7, #4]
800432c: 2200 movs r2, #0
800432e: 63da str r2, [r3, #60] ; 0x3c
huart->gState = HAL_UART_STATE_READY;
8004330: 687b ldr r3, [r7, #4]
8004332: 2220 movs r2, #32
8004334: f883 2039 strb.w r2, [r3, #57] ; 0x39
huart->RxState = HAL_UART_STATE_READY;
8004338: 687b ldr r3, [r7, #4]
800433a: 2220 movs r2, #32
800433c: f883 203a strb.w r2, [r3, #58] ; 0x3a
return HAL_OK;
8004340: 2300 movs r3, #0
}
8004342: 4618 mov r0, r3
8004344: 3708 adds r7, #8
8004346: 46bd mov sp, r7
8004348: bd80 pop {r7, pc}
0800434a <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800434a: b580 push {r7, lr}
800434c: b088 sub sp, #32
800434e: af02 add r7, sp, #8
8004350: 60f8 str r0, [r7, #12]
8004352: 60b9 str r1, [r7, #8]
8004354: 603b str r3, [r7, #0]
8004356: 4613 mov r3, r2
8004358: 80fb strh r3, [r7, #6]
uint16_t *tmp;
uint32_t tickstart = 0U;
800435a: 2300 movs r3, #0
800435c: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
800435e: 68fb ldr r3, [r7, #12]
8004360: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8004364: b2db uxtb r3, r3
8004366: 2b20 cmp r3, #32
8004368: f040 8083 bne.w 8004472 <HAL_UART_Transmit+0x128>
{
if ((pData == NULL) || (Size == 0U))
800436c: 68bb ldr r3, [r7, #8]
800436e: 2b00 cmp r3, #0
8004370: d002 beq.n 8004378 <HAL_UART_Transmit+0x2e>
8004372: 88fb ldrh r3, [r7, #6]
8004374: 2b00 cmp r3, #0
8004376: d101 bne.n 800437c <HAL_UART_Transmit+0x32>
{
return HAL_ERROR;
8004378: 2301 movs r3, #1
800437a: e07b b.n 8004474 <HAL_UART_Transmit+0x12a>
}
/* Process Locked */
__HAL_LOCK(huart);
800437c: 68fb ldr r3, [r7, #12]
800437e: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8004382: 2b01 cmp r3, #1
8004384: d101 bne.n 800438a <HAL_UART_Transmit+0x40>
8004386: 2302 movs r3, #2
8004388: e074 b.n 8004474 <HAL_UART_Transmit+0x12a>
800438a: 68fb ldr r3, [r7, #12]
800438c: 2201 movs r2, #1
800438e: f883 2038 strb.w r2, [r3, #56] ; 0x38
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004392: 68fb ldr r3, [r7, #12]
8004394: 2200 movs r2, #0
8004396: 63da str r2, [r3, #60] ; 0x3c
huart->gState = HAL_UART_STATE_BUSY_TX;
8004398: 68fb ldr r3, [r7, #12]
800439a: 2221 movs r2, #33 ; 0x21
800439c: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Init tickstart for timeout managment */
tickstart = HAL_GetTick();
80043a0: f7fd f8dc bl 800155c <HAL_GetTick>
80043a4: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
80043a6: 68fb ldr r3, [r7, #12]
80043a8: 88fa ldrh r2, [r7, #6]
80043aa: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
80043ac: 68fb ldr r3, [r7, #12]
80043ae: 88fa ldrh r2, [r7, #6]
80043b0: 84da strh r2, [r3, #38] ; 0x26
while (huart->TxXferCount > 0U)
80043b2: e042 b.n 800443a <HAL_UART_Transmit+0xf0>
{
huart->TxXferCount--;
80043b4: 68fb ldr r3, [r7, #12]
80043b6: 8cdb ldrh r3, [r3, #38] ; 0x26
80043b8: b29b uxth r3, r3
80043ba: 3b01 subs r3, #1
80043bc: b29a uxth r2, r3
80043be: 68fb ldr r3, [r7, #12]
80043c0: 84da strh r2, [r3, #38] ; 0x26
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
80043c2: 68fb ldr r3, [r7, #12]
80043c4: 689b ldr r3, [r3, #8]
80043c6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80043ca: d122 bne.n 8004412 <HAL_UART_Transmit+0xc8>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
80043cc: 683b ldr r3, [r7, #0]
80043ce: 9300 str r3, [sp, #0]
80043d0: 697b ldr r3, [r7, #20]
80043d2: 2200 movs r2, #0
80043d4: 2180 movs r1, #128 ; 0x80
80043d6: 68f8 ldr r0, [r7, #12]
80043d8: f000 fac6 bl 8004968 <UART_WaitOnFlagUntilTimeout>
80043dc: 4603 mov r3, r0
80043de: 2b00 cmp r3, #0
80043e0: d001 beq.n 80043e6 <HAL_UART_Transmit+0x9c>
{
return HAL_TIMEOUT;
80043e2: 2303 movs r3, #3
80043e4: e046 b.n 8004474 <HAL_UART_Transmit+0x12a>
}
tmp = (uint16_t *) pData;
80043e6: 68bb ldr r3, [r7, #8]
80043e8: 613b str r3, [r7, #16]
huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
80043ea: 693b ldr r3, [r7, #16]
80043ec: 881b ldrh r3, [r3, #0]
80043ee: 461a mov r2, r3
80043f0: 68fb ldr r3, [r7, #12]
80043f2: 681b ldr r3, [r3, #0]
80043f4: f3c2 0208 ubfx r2, r2, #0, #9
80043f8: 605a str r2, [r3, #4]
if (huart->Init.Parity == UART_PARITY_NONE)
80043fa: 68fb ldr r3, [r7, #12]
80043fc: 691b ldr r3, [r3, #16]
80043fe: 2b00 cmp r3, #0
8004400: d103 bne.n 800440a <HAL_UART_Transmit+0xc0>
{
pData += 2U;
8004402: 68bb ldr r3, [r7, #8]
8004404: 3302 adds r3, #2
8004406: 60bb str r3, [r7, #8]
8004408: e017 b.n 800443a <HAL_UART_Transmit+0xf0>
}
else
{
pData += 1U;
800440a: 68bb ldr r3, [r7, #8]
800440c: 3301 adds r3, #1
800440e: 60bb str r3, [r7, #8]
8004410: e013 b.n 800443a <HAL_UART_Transmit+0xf0>
}
}
else
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8004412: 683b ldr r3, [r7, #0]
8004414: 9300 str r3, [sp, #0]
8004416: 697b ldr r3, [r7, #20]
8004418: 2200 movs r2, #0
800441a: 2180 movs r1, #128 ; 0x80
800441c: 68f8 ldr r0, [r7, #12]
800441e: f000 faa3 bl 8004968 <UART_WaitOnFlagUntilTimeout>
8004422: 4603 mov r3, r0
8004424: 2b00 cmp r3, #0
8004426: d001 beq.n 800442c <HAL_UART_Transmit+0xe2>
{
return HAL_TIMEOUT;
8004428: 2303 movs r3, #3
800442a: e023 b.n 8004474 <HAL_UART_Transmit+0x12a>
}
huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
800442c: 68bb ldr r3, [r7, #8]
800442e: 1c5a adds r2, r3, #1
8004430: 60ba str r2, [r7, #8]
8004432: 781a ldrb r2, [r3, #0]
8004434: 68fb ldr r3, [r7, #12]
8004436: 681b ldr r3, [r3, #0]
8004438: 605a str r2, [r3, #4]
while (huart->TxXferCount > 0U)
800443a: 68fb ldr r3, [r7, #12]
800443c: 8cdb ldrh r3, [r3, #38] ; 0x26
800443e: b29b uxth r3, r3
8004440: 2b00 cmp r3, #0
8004442: d1b7 bne.n 80043b4 <HAL_UART_Transmit+0x6a>
}
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8004444: 683b ldr r3, [r7, #0]
8004446: 9300 str r3, [sp, #0]
8004448: 697b ldr r3, [r7, #20]
800444a: 2200 movs r2, #0
800444c: 2140 movs r1, #64 ; 0x40
800444e: 68f8 ldr r0, [r7, #12]
8004450: f000 fa8a bl 8004968 <UART_WaitOnFlagUntilTimeout>
8004454: 4603 mov r3, r0
8004456: 2b00 cmp r3, #0
8004458: d001 beq.n 800445e <HAL_UART_Transmit+0x114>
{
return HAL_TIMEOUT;
800445a: 2303 movs r3, #3
800445c: e00a b.n 8004474 <HAL_UART_Transmit+0x12a>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
800445e: 68fb ldr r3, [r7, #12]
8004460: 2220 movs r2, #32
8004462: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004466: 68fb ldr r3, [r7, #12]
8004468: 2200 movs r2, #0
800446a: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
800446e: 2300 movs r3, #0
8004470: e000 b.n 8004474 <HAL_UART_Transmit+0x12a>
}
else
{
return HAL_BUSY;
8004472: 2302 movs r3, #2
}
}
8004474: 4618 mov r0, r3
8004476: 3718 adds r7, #24
8004478: 46bd mov sp, r7
800447a: bd80 pop {r7, pc}
0800447c <HAL_UART_Receive_DMA>:
* @param Size Amount of data elements (u8 or u16) to be received.
* @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
800447c: b580 push {r7, lr}
800447e: b086 sub sp, #24
8004480: af00 add r7, sp, #0
8004482: 60f8 str r0, [r7, #12]
8004484: 60b9 str r1, [r7, #8]
8004486: 4613 mov r3, r2
8004488: 80fb strh r3, [r7, #6]
uint32_t *tmp;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
800448a: 68fb ldr r3, [r7, #12]
800448c: f893 303a ldrb.w r3, [r3, #58] ; 0x3a
8004490: b2db uxtb r3, r3
8004492: 2b20 cmp r3, #32
8004494: d166 bne.n 8004564 <HAL_UART_Receive_DMA+0xe8>
{
if ((pData == NULL) || (Size == 0U))
8004496: 68bb ldr r3, [r7, #8]
8004498: 2b00 cmp r3, #0
800449a: d002 beq.n 80044a2 <HAL_UART_Receive_DMA+0x26>
800449c: 88fb ldrh r3, [r7, #6]
800449e: 2b00 cmp r3, #0
80044a0: d101 bne.n 80044a6 <HAL_UART_Receive_DMA+0x2a>
{
return HAL_ERROR;
80044a2: 2301 movs r3, #1
80044a4: e05f b.n 8004566 <HAL_UART_Receive_DMA+0xea>
}
/* Process Locked */
__HAL_LOCK(huart);
80044a6: 68fb ldr r3, [r7, #12]
80044a8: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
80044ac: 2b01 cmp r3, #1
80044ae: d101 bne.n 80044b4 <HAL_UART_Receive_DMA+0x38>
80044b0: 2302 movs r3, #2
80044b2: e058 b.n 8004566 <HAL_UART_Receive_DMA+0xea>
80044b4: 68fb ldr r3, [r7, #12]
80044b6: 2201 movs r2, #1
80044b8: f883 2038 strb.w r2, [r3, #56] ; 0x38
huart->pRxBuffPtr = pData;
80044bc: 68ba ldr r2, [r7, #8]
80044be: 68fb ldr r3, [r7, #12]
80044c0: 629a str r2, [r3, #40] ; 0x28
huart->RxXferSize = Size;
80044c2: 68fb ldr r3, [r7, #12]
80044c4: 88fa ldrh r2, [r7, #6]
80044c6: 859a strh r2, [r3, #44] ; 0x2c
huart->ErrorCode = HAL_UART_ERROR_NONE;
80044c8: 68fb ldr r3, [r7, #12]
80044ca: 2200 movs r2, #0
80044cc: 63da str r2, [r3, #60] ; 0x3c
huart->RxState = HAL_UART_STATE_BUSY_RX;
80044ce: 68fb ldr r3, [r7, #12]
80044d0: 2222 movs r2, #34 ; 0x22
80044d2: f883 203a strb.w r2, [r3, #58] ; 0x3a
/* Set the UART DMA transfer complete callback */
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
80044d6: 68fb ldr r3, [r7, #12]
80044d8: 6b5b ldr r3, [r3, #52] ; 0x34
80044da: 4a25 ldr r2, [pc, #148] ; (8004570 <HAL_UART_Receive_DMA+0xf4>)
80044dc: 629a str r2, [r3, #40] ; 0x28
/* Set the UART DMA Half transfer complete callback */
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
80044de: 68fb ldr r3, [r7, #12]
80044e0: 6b5b ldr r3, [r3, #52] ; 0x34
80044e2: 4a24 ldr r2, [pc, #144] ; (8004574 <HAL_UART_Receive_DMA+0xf8>)
80044e4: 62da str r2, [r3, #44] ; 0x2c
/* Set the DMA error callback */
huart->hdmarx->XferErrorCallback = UART_DMAError;
80044e6: 68fb ldr r3, [r7, #12]
80044e8: 6b5b ldr r3, [r3, #52] ; 0x34
80044ea: 4a23 ldr r2, [pc, #140] ; (8004578 <HAL_UART_Receive_DMA+0xfc>)
80044ec: 631a str r2, [r3, #48] ; 0x30
/* Set the DMA abort callback */
huart->hdmarx->XferAbortCallback = NULL;
80044ee: 68fb ldr r3, [r7, #12]
80044f0: 6b5b ldr r3, [r3, #52] ; 0x34
80044f2: 2200 movs r2, #0
80044f4: 635a str r2, [r3, #52] ; 0x34
/* Enable the DMA channel */
tmp = (uint32_t *)&pData;
80044f6: f107 0308 add.w r3, r7, #8
80044fa: 617b str r3, [r7, #20]
HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
80044fc: 68fb ldr r3, [r7, #12]
80044fe: 6b58 ldr r0, [r3, #52] ; 0x34
8004500: 68fb ldr r3, [r7, #12]
8004502: 681b ldr r3, [r3, #0]
8004504: 3304 adds r3, #4
8004506: 4619 mov r1, r3
8004508: 697b ldr r3, [r7, #20]
800450a: 681a ldr r2, [r3, #0]
800450c: 88fb ldrh r3, [r7, #6]
800450e: f7fd f98b bl 8001828 <HAL_DMA_Start_IT>
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_UART_CLEAR_OREFLAG(huart);
8004512: 2300 movs r3, #0
8004514: 613b str r3, [r7, #16]
8004516: 68fb ldr r3, [r7, #12]
8004518: 681b ldr r3, [r3, #0]
800451a: 681b ldr r3, [r3, #0]
800451c: 613b str r3, [r7, #16]
800451e: 68fb ldr r3, [r7, #12]
8004520: 681b ldr r3, [r3, #0]
8004522: 685b ldr r3, [r3, #4]
8004524: 613b str r3, [r7, #16]
8004526: 693b ldr r3, [r7, #16]
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004528: 68fb ldr r3, [r7, #12]
800452a: 2200 movs r2, #0
800452c: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Enable the UART Parity Error Interrupt */
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8004530: 68fb ldr r3, [r7, #12]
8004532: 681b ldr r3, [r3, #0]
8004534: 68da ldr r2, [r3, #12]
8004536: 68fb ldr r3, [r7, #12]
8004538: 681b ldr r3, [r3, #0]
800453a: f442 7280 orr.w r2, r2, #256 ; 0x100
800453e: 60da str r2, [r3, #12]
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004540: 68fb ldr r3, [r7, #12]
8004542: 681b ldr r3, [r3, #0]
8004544: 695a ldr r2, [r3, #20]
8004546: 68fb ldr r3, [r7, #12]
8004548: 681b ldr r3, [r3, #0]
800454a: f042 0201 orr.w r2, r2, #1
800454e: 615a str r2, [r3, #20]
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004550: 68fb ldr r3, [r7, #12]
8004552: 681b ldr r3, [r3, #0]
8004554: 695a ldr r2, [r3, #20]
8004556: 68fb ldr r3, [r7, #12]
8004558: 681b ldr r3, [r3, #0]
800455a: f042 0240 orr.w r2, r2, #64 ; 0x40
800455e: 615a str r2, [r3, #20]
return HAL_OK;
8004560: 2300 movs r3, #0
8004562: e000 b.n 8004566 <HAL_UART_Receive_DMA+0xea>
}
else
{
return HAL_BUSY;
8004564: 2302 movs r3, #2
}
}
8004566: 4618 mov r0, r3
8004568: 3718 adds r7, #24
800456a: 46bd mov sp, r7
800456c: bd80 pop {r7, pc}
800456e: bf00 nop
8004570: 08004851 .word 0x08004851
8004574: 080048b9 .word 0x080048b9
8004578: 080048d5 .word 0x080048d5
0800457c <HAL_UART_DMAStop>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
{
800457c: b580 push {r7, lr}
800457e: b084 sub sp, #16
8004580: af00 add r7, sp, #0
8004582: 6078 str r0, [r7, #4]
uint32_t dmarequest = 0x00U;
8004584: 2300 movs r3, #0
8004586: 60fb str r3, [r7, #12]
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
*/
/* Stop UART DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
8004588: 687b ldr r3, [r7, #4]
800458a: 681b ldr r3, [r3, #0]
800458c: 695b ldr r3, [r3, #20]
800458e: f003 0380 and.w r3, r3, #128 ; 0x80
8004592: 2b00 cmp r3, #0
8004594: bf14 ite ne
8004596: 2301 movne r3, #1
8004598: 2300 moveq r3, #0
800459a: b2db uxtb r3, r3
800459c: 60fb str r3, [r7, #12]
if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
800459e: 687b ldr r3, [r7, #4]
80045a0: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
80045a4: b2db uxtb r3, r3
80045a6: 2b21 cmp r3, #33 ; 0x21
80045a8: d116 bne.n 80045d8 <HAL_UART_DMAStop+0x5c>
80045aa: 68fb ldr r3, [r7, #12]
80045ac: 2b00 cmp r3, #0
80045ae: d013 beq.n 80045d8 <HAL_UART_DMAStop+0x5c>
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
80045b0: 687b ldr r3, [r7, #4]
80045b2: 681b ldr r3, [r3, #0]
80045b4: 695a ldr r2, [r3, #20]
80045b6: 687b ldr r3, [r7, #4]
80045b8: 681b ldr r3, [r3, #0]
80045ba: f022 0280 bic.w r2, r2, #128 ; 0x80
80045be: 615a str r2, [r3, #20]
/* Abort the UART DMA Tx channel */
if (huart->hdmatx != NULL)
80045c0: 687b ldr r3, [r7, #4]
80045c2: 6b1b ldr r3, [r3, #48] ; 0x30
80045c4: 2b00 cmp r3, #0
80045c6: d004 beq.n 80045d2 <HAL_UART_DMAStop+0x56>
{
HAL_DMA_Abort(huart->hdmatx);
80045c8: 687b ldr r3, [r7, #4]
80045ca: 6b1b ldr r3, [r3, #48] ; 0x30
80045cc: 4618 mov r0, r3
80045ce: f7fd f98a bl 80018e6 <HAL_DMA_Abort>
}
UART_EndTxTransfer(huart);
80045d2: 6878 ldr r0, [r7, #4]
80045d4: f000 fa12 bl 80049fc <UART_EndTxTransfer>
}
/* Stop UART DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
80045d8: 687b ldr r3, [r7, #4]
80045da: 681b ldr r3, [r3, #0]
80045dc: 695b ldr r3, [r3, #20]
80045de: f003 0340 and.w r3, r3, #64 ; 0x40
80045e2: 2b00 cmp r3, #0
80045e4: bf14 ite ne
80045e6: 2301 movne r3, #1
80045e8: 2300 moveq r3, #0
80045ea: b2db uxtb r3, r3
80045ec: 60fb str r3, [r7, #12]
if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
80045ee: 687b ldr r3, [r7, #4]
80045f0: f893 303a ldrb.w r3, [r3, #58] ; 0x3a
80045f4: b2db uxtb r3, r3
80045f6: 2b22 cmp r3, #34 ; 0x22
80045f8: d116 bne.n 8004628 <HAL_UART_DMAStop+0xac>
80045fa: 68fb ldr r3, [r7, #12]
80045fc: 2b00 cmp r3, #0
80045fe: d013 beq.n 8004628 <HAL_UART_DMAStop+0xac>
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004600: 687b ldr r3, [r7, #4]
8004602: 681b ldr r3, [r3, #0]
8004604: 695a ldr r2, [r3, #20]
8004606: 687b ldr r3, [r7, #4]
8004608: 681b ldr r3, [r3, #0]
800460a: f022 0240 bic.w r2, r2, #64 ; 0x40
800460e: 615a str r2, [r3, #20]
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
8004610: 687b ldr r3, [r7, #4]
8004612: 6b5b ldr r3, [r3, #52] ; 0x34
8004614: 2b00 cmp r3, #0
8004616: d004 beq.n 8004622 <HAL_UART_DMAStop+0xa6>
{
HAL_DMA_Abort(huart->hdmarx);
8004618: 687b ldr r3, [r7, #4]
800461a: 6b5b ldr r3, [r3, #52] ; 0x34
800461c: 4618 mov r0, r3
800461e: f7fd f962 bl 80018e6 <HAL_DMA_Abort>
}
UART_EndRxTransfer(huart);
8004622: 6878 ldr r0, [r7, #4]
8004624: f000 f9ff bl 8004a26 <UART_EndRxTransfer>
}
return HAL_OK;
8004628: 2300 movs r3, #0
}
800462a: 4618 mov r0, r3
800462c: 3710 adds r7, #16
800462e: 46bd mov sp, r7
8004630: bd80 pop {r7, pc}
...
08004634 <HAL_UART_IRQHandler>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8004634: b580 push {r7, lr}
8004636: b088 sub sp, #32
8004638: af00 add r7, sp, #0
800463a: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->SR);
800463c: 687b ldr r3, [r7, #4]
800463e: 681b ldr r3, [r3, #0]
8004640: 681b ldr r3, [r3, #0]
8004642: 61fb str r3, [r7, #28]
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8004644: 687b ldr r3, [r7, #4]
8004646: 681b ldr r3, [r3, #0]
8004648: 68db ldr r3, [r3, #12]
800464a: 61bb str r3, [r7, #24]
uint32_t cr3its = READ_REG(huart->Instance->CR3);
800464c: 687b ldr r3, [r7, #4]
800464e: 681b ldr r3, [r3, #0]
8004650: 695b ldr r3, [r3, #20]
8004652: 617b str r3, [r7, #20]
uint32_t errorflags = 0x00U;
8004654: 2300 movs r3, #0
8004656: 613b str r3, [r7, #16]
uint32_t dmarequest = 0x00U;
8004658: 2300 movs r3, #0
800465a: 60fb str r3, [r7, #12]
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
800465c: 69fb ldr r3, [r7, #28]
800465e: f003 030f and.w r3, r3, #15
8004662: 613b str r3, [r7, #16]
if (errorflags == RESET)
8004664: 693b ldr r3, [r7, #16]
8004666: 2b00 cmp r3, #0
8004668: d10d bne.n 8004686 <HAL_UART_IRQHandler+0x52>
{
/* UART in mode Receiver -------------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
800466a: 69fb ldr r3, [r7, #28]
800466c: f003 0320 and.w r3, r3, #32
8004670: 2b00 cmp r3, #0
8004672: d008 beq.n 8004686 <HAL_UART_IRQHandler+0x52>
8004674: 69bb ldr r3, [r7, #24]
8004676: f003 0320 and.w r3, r3, #32
800467a: 2b00 cmp r3, #0
800467c: d003 beq.n 8004686 <HAL_UART_IRQHandler+0x52>
{
UART_Receive_IT(huart);
800467e: 6878 ldr r0, [r7, #4]
8004680: f000 fa6f bl 8004b62 <UART_Receive_IT>
return;
8004684: e0cc b.n 8004820 <HAL_UART_IRQHandler+0x1ec>
}
}
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
8004686: 693b ldr r3, [r7, #16]
8004688: 2b00 cmp r3, #0
800468a: f000 80ab beq.w 80047e4 <HAL_UART_IRQHandler+0x1b0>
800468e: 697b ldr r3, [r7, #20]
8004690: f003 0301 and.w r3, r3, #1
8004694: 2b00 cmp r3, #0
8004696: d105 bne.n 80046a4 <HAL_UART_IRQHandler+0x70>
8004698: 69bb ldr r3, [r7, #24]
800469a: f403 7390 and.w r3, r3, #288 ; 0x120
800469e: 2b00 cmp r3, #0
80046a0: f000 80a0 beq.w 80047e4 <HAL_UART_IRQHandler+0x1b0>
{
/* UART parity error interrupt occurred ----------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
80046a4: 69fb ldr r3, [r7, #28]
80046a6: f003 0301 and.w r3, r3, #1
80046aa: 2b00 cmp r3, #0
80046ac: d00a beq.n 80046c4 <HAL_UART_IRQHandler+0x90>
80046ae: 69bb ldr r3, [r7, #24]
80046b0: f403 7380 and.w r3, r3, #256 ; 0x100
80046b4: 2b00 cmp r3, #0
80046b6: d005 beq.n 80046c4 <HAL_UART_IRQHandler+0x90>
{
huart->ErrorCode |= HAL_UART_ERROR_PE;
80046b8: 687b ldr r3, [r7, #4]
80046ba: 6bdb ldr r3, [r3, #60] ; 0x3c
80046bc: f043 0201 orr.w r2, r3, #1
80046c0: 687b ldr r3, [r7, #4]
80046c2: 63da str r2, [r3, #60] ; 0x3c
}
/* UART noise error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
80046c4: 69fb ldr r3, [r7, #28]
80046c6: f003 0304 and.w r3, r3, #4
80046ca: 2b00 cmp r3, #0
80046cc: d00a beq.n 80046e4 <HAL_UART_IRQHandler+0xb0>
80046ce: 697b ldr r3, [r7, #20]
80046d0: f003 0301 and.w r3, r3, #1
80046d4: 2b00 cmp r3, #0
80046d6: d005 beq.n 80046e4 <HAL_UART_IRQHandler+0xb0>
{
huart->ErrorCode |= HAL_UART_ERROR_NE;
80046d8: 687b ldr r3, [r7, #4]
80046da: 6bdb ldr r3, [r3, #60] ; 0x3c
80046dc: f043 0202 orr.w r2, r3, #2
80046e0: 687b ldr r3, [r7, #4]
80046e2: 63da str r2, [r3, #60] ; 0x3c
}
/* UART frame error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
80046e4: 69fb ldr r3, [r7, #28]
80046e6: f003 0302 and.w r3, r3, #2
80046ea: 2b00 cmp r3, #0
80046ec: d00a beq.n 8004704 <HAL_UART_IRQHandler+0xd0>
80046ee: 697b ldr r3, [r7, #20]
80046f0: f003 0301 and.w r3, r3, #1
80046f4: 2b00 cmp r3, #0
80046f6: d005 beq.n 8004704 <HAL_UART_IRQHandler+0xd0>
{
huart->ErrorCode |= HAL_UART_ERROR_FE;
80046f8: 687b ldr r3, [r7, #4]
80046fa: 6bdb ldr r3, [r3, #60] ; 0x3c
80046fc: f043 0204 orr.w r2, r3, #4
8004700: 687b ldr r3, [r7, #4]
8004702: 63da str r2, [r3, #60] ; 0x3c
}
/* UART Over-Run interrupt occurred --------------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8004704: 69fb ldr r3, [r7, #28]
8004706: f003 0308 and.w r3, r3, #8
800470a: 2b00 cmp r3, #0
800470c: d00a beq.n 8004724 <HAL_UART_IRQHandler+0xf0>
800470e: 697b ldr r3, [r7, #20]
8004710: f003 0301 and.w r3, r3, #1
8004714: 2b00 cmp r3, #0
8004716: d005 beq.n 8004724 <HAL_UART_IRQHandler+0xf0>
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8004718: 687b ldr r3, [r7, #4]
800471a: 6bdb ldr r3, [r3, #60] ; 0x3c
800471c: f043 0208 orr.w r2, r3, #8
8004720: 687b ldr r3, [r7, #4]
8004722: 63da str r2, [r3, #60] ; 0x3c
}
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8004724: 687b ldr r3, [r7, #4]
8004726: 6bdb ldr r3, [r3, #60] ; 0x3c
8004728: 2b00 cmp r3, #0
800472a: d078 beq.n 800481e <HAL_UART_IRQHandler+0x1ea>
{
/* UART in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
800472c: 69fb ldr r3, [r7, #28]
800472e: f003 0320 and.w r3, r3, #32
8004732: 2b00 cmp r3, #0
8004734: d007 beq.n 8004746 <HAL_UART_IRQHandler+0x112>
8004736: 69bb ldr r3, [r7, #24]
8004738: f003 0320 and.w r3, r3, #32
800473c: 2b00 cmp r3, #0
800473e: d002 beq.n 8004746 <HAL_UART_IRQHandler+0x112>
{
UART_Receive_IT(huart);
8004740: 6878 ldr r0, [r7, #4]
8004742: f000 fa0e bl 8004b62 <UART_Receive_IT>
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
8004746: 687b ldr r3, [r7, #4]
8004748: 681b ldr r3, [r3, #0]
800474a: 695b ldr r3, [r3, #20]
800474c: f003 0340 and.w r3, r3, #64 ; 0x40
8004750: 2b00 cmp r3, #0
8004752: bf14 ite ne
8004754: 2301 movne r3, #1
8004756: 2300 moveq r3, #0
8004758: b2db uxtb r3, r3
800475a: 60fb str r3, [r7, #12]
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
800475c: 687b ldr r3, [r7, #4]
800475e: 6bdb ldr r3, [r3, #60] ; 0x3c
8004760: f003 0308 and.w r3, r3, #8
8004764: 2b00 cmp r3, #0
8004766: d102 bne.n 800476e <HAL_UART_IRQHandler+0x13a>
8004768: 68fb ldr r3, [r7, #12]
800476a: 2b00 cmp r3, #0
800476c: d031 beq.n 80047d2 <HAL_UART_IRQHandler+0x19e>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
800476e: 6878 ldr r0, [r7, #4]
8004770: f000 f959 bl 8004a26 <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004774: 687b ldr r3, [r7, #4]
8004776: 681b ldr r3, [r3, #0]
8004778: 695b ldr r3, [r3, #20]
800477a: f003 0340 and.w r3, r3, #64 ; 0x40
800477e: 2b00 cmp r3, #0
8004780: d023 beq.n 80047ca <HAL_UART_IRQHandler+0x196>
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004782: 687b ldr r3, [r7, #4]
8004784: 681b ldr r3, [r3, #0]
8004786: 695a ldr r2, [r3, #20]
8004788: 687b ldr r3, [r7, #4]
800478a: 681b ldr r3, [r3, #0]
800478c: f022 0240 bic.w r2, r2, #64 ; 0x40
8004790: 615a str r2, [r3, #20]
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
8004792: 687b ldr r3, [r7, #4]
8004794: 6b5b ldr r3, [r3, #52] ; 0x34
8004796: 2b00 cmp r3, #0
8004798: d013 beq.n 80047c2 <HAL_UART_IRQHandler+0x18e>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
800479a: 687b ldr r3, [r7, #4]
800479c: 6b5b ldr r3, [r3, #52] ; 0x34
800479e: 4a22 ldr r2, [pc, #136] ; (8004828 <HAL_UART_IRQHandler+0x1f4>)
80047a0: 635a str r2, [r3, #52] ; 0x34
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
80047a2: 687b ldr r3, [r7, #4]
80047a4: 6b5b ldr r3, [r3, #52] ; 0x34
80047a6: 4618 mov r0, r3
80047a8: f7fd f8d8 bl 800195c <HAL_DMA_Abort_IT>
80047ac: 4603 mov r3, r0
80047ae: 2b00 cmp r3, #0
80047b0: d016 beq.n 80047e0 <HAL_UART_IRQHandler+0x1ac>
{
/* Call Directly XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
80047b2: 687b ldr r3, [r7, #4]
80047b4: 6b5b ldr r3, [r3, #52] ; 0x34
80047b6: 6b5b ldr r3, [r3, #52] ; 0x34
80047b8: 687a ldr r2, [r7, #4]
80047ba: 6b52 ldr r2, [r2, #52] ; 0x34
80047bc: 4610 mov r0, r2
80047be: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80047c0: e00e b.n 80047e0 <HAL_UART_IRQHandler+0x1ac>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80047c2: 6878 ldr r0, [r7, #4]
80047c4: f000 f83b bl 800483e <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80047c8: e00a b.n 80047e0 <HAL_UART_IRQHandler+0x1ac>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80047ca: 6878 ldr r0, [r7, #4]
80047cc: f000 f837 bl 800483e <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80047d0: e006 b.n 80047e0 <HAL_UART_IRQHandler+0x1ac>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80047d2: 6878 ldr r0, [r7, #4]
80047d4: f000 f833 bl 800483e <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80047d8: 687b ldr r3, [r7, #4]
80047da: 2200 movs r2, #0
80047dc: 63da str r2, [r3, #60] ; 0x3c
}
}
return;
80047de: e01e b.n 800481e <HAL_UART_IRQHandler+0x1ea>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80047e0: bf00 nop
return;
80047e2: e01c b.n 800481e <HAL_UART_IRQHandler+0x1ea>
} /* End if some error occurs */
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
80047e4: 69fb ldr r3, [r7, #28]
80047e6: f003 0380 and.w r3, r3, #128 ; 0x80
80047ea: 2b00 cmp r3, #0
80047ec: d008 beq.n 8004800 <HAL_UART_IRQHandler+0x1cc>
80047ee: 69bb ldr r3, [r7, #24]
80047f0: f003 0380 and.w r3, r3, #128 ; 0x80
80047f4: 2b00 cmp r3, #0
80047f6: d003 beq.n 8004800 <HAL_UART_IRQHandler+0x1cc>
{
UART_Transmit_IT(huart);
80047f8: 6878 ldr r0, [r7, #4]
80047fa: f000 f945 bl 8004a88 <UART_Transmit_IT>
return;
80047fe: e00f b.n 8004820 <HAL_UART_IRQHandler+0x1ec>
}
/* UART in mode Transmitter end --------------------------------------------*/
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
8004800: 69fb ldr r3, [r7, #28]
8004802: f003 0340 and.w r3, r3, #64 ; 0x40
8004806: 2b00 cmp r3, #0
8004808: d00a beq.n 8004820 <HAL_UART_IRQHandler+0x1ec>
800480a: 69bb ldr r3, [r7, #24]
800480c: f003 0340 and.w r3, r3, #64 ; 0x40
8004810: 2b00 cmp r3, #0
8004812: d005 beq.n 8004820 <HAL_UART_IRQHandler+0x1ec>
{
UART_EndTransmit_IT(huart);
8004814: 6878 ldr r0, [r7, #4]
8004816: f000 f98c bl 8004b32 <UART_EndTransmit_IT>
return;
800481a: bf00 nop
800481c: e000 b.n 8004820 <HAL_UART_IRQHandler+0x1ec>
return;
800481e: bf00 nop
}
}
8004820: 3720 adds r7, #32
8004822: 46bd mov sp, r7
8004824: bd80 pop {r7, pc}
8004826: bf00 nop
8004828: 08004a61 .word 0x08004a61
0800482c <HAL_UART_TxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
800482c: b480 push {r7}
800482e: b083 sub sp, #12
8004830: af00 add r7, sp, #0
8004832: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
}
8004834: bf00 nop
8004836: 370c adds r7, #12
8004838: 46bd mov sp, r7
800483a: bc80 pop {r7}
800483c: 4770 bx lr
0800483e <HAL_UART_ErrorCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
800483e: b480 push {r7}
8004840: b083 sub sp, #12
8004842: af00 add r7, sp, #0
8004844: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
8004846: bf00 nop
8004848: 370c adds r7, #12
800484a: 46bd mov sp, r7
800484c: bc80 pop {r7}
800484e: 4770 bx lr
08004850 <UART_DMAReceiveCplt>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
8004850: b580 push {r7, lr}
8004852: b084 sub sp, #16
8004854: af00 add r7, sp, #0
8004856: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8004858: 687b ldr r3, [r7, #4]
800485a: 6a5b ldr r3, [r3, #36] ; 0x24
800485c: 60fb str r3, [r7, #12]
/* DMA Normal mode*/
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
800485e: 687b ldr r3, [r7, #4]
8004860: 681b ldr r3, [r3, #0]
8004862: 681b ldr r3, [r3, #0]
8004864: f003 0320 and.w r3, r3, #32
8004868: 2b00 cmp r3, #0
800486a: d11e bne.n 80048aa <UART_DMAReceiveCplt+0x5a>
{
huart->RxXferCount = 0U;
800486c: 68fb ldr r3, [r7, #12]
800486e: 2200 movs r2, #0
8004870: 85da strh r2, [r3, #46] ; 0x2e
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8004872: 68fb ldr r3, [r7, #12]
8004874: 681b ldr r3, [r3, #0]
8004876: 68da ldr r2, [r3, #12]
8004878: 68fb ldr r3, [r7, #12]
800487a: 681b ldr r3, [r3, #0]
800487c: f422 7280 bic.w r2, r2, #256 ; 0x100
8004880: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004882: 68fb ldr r3, [r7, #12]
8004884: 681b ldr r3, [r3, #0]
8004886: 695a ldr r2, [r3, #20]
8004888: 68fb ldr r3, [r7, #12]
800488a: 681b ldr r3, [r3, #0]
800488c: f022 0201 bic.w r2, r2, #1
8004890: 615a str r2, [r3, #20]
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004892: 68fb ldr r3, [r7, #12]
8004894: 681b ldr r3, [r3, #0]
8004896: 695a ldr r2, [r3, #20]
8004898: 68fb ldr r3, [r7, #12]
800489a: 681b ldr r3, [r3, #0]
800489c: f022 0240 bic.w r2, r2, #64 ; 0x40
80048a0: 615a str r2, [r3, #20]
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80048a2: 68fb ldr r3, [r7, #12]
80048a4: 2220 movs r2, #32
80048a6: f883 203a strb.w r2, [r3, #58] ; 0x3a
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
80048aa: 68f8 ldr r0, [r7, #12]
80048ac: f7fc fa0c bl 8000cc8 <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80048b0: bf00 nop
80048b2: 3710 adds r7, #16
80048b4: 46bd mov sp, r7
80048b6: bd80 pop {r7, pc}
080048b8 <UART_DMARxHalfCplt>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
80048b8: b580 push {r7, lr}
80048ba: b084 sub sp, #16
80048bc: af00 add r7, sp, #0
80048be: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
80048c0: 687b ldr r3, [r7, #4]
80048c2: 6a5b ldr r3, [r3, #36] ; 0x24
80048c4: 60fb str r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Half complete callback*/
huart->RxHalfCpltCallback(huart);
#else
/*Call legacy weak Rx Half complete callback*/
HAL_UART_RxHalfCpltCallback(huart);
80048c6: 68f8 ldr r0, [r7, #12]
80048c8: f7fc fa08 bl 8000cdc <HAL_UART_RxHalfCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80048cc: bf00 nop
80048ce: 3710 adds r7, #16
80048d0: 46bd mov sp, r7
80048d2: bd80 pop {r7, pc}
080048d4 <UART_DMAError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
80048d4: b580 push {r7, lr}
80048d6: b084 sub sp, #16
80048d8: af00 add r7, sp, #0
80048da: 6078 str r0, [r7, #4]
uint32_t dmarequest = 0x00U;
80048dc: 2300 movs r3, #0
80048de: 60fb str r3, [r7, #12]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
80048e0: 687b ldr r3, [r7, #4]
80048e2: 6a5b ldr r3, [r3, #36] ; 0x24
80048e4: 60bb str r3, [r7, #8]
/* Stop UART DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
80048e6: 68bb ldr r3, [r7, #8]
80048e8: 681b ldr r3, [r3, #0]
80048ea: 695b ldr r3, [r3, #20]
80048ec: f003 0380 and.w r3, r3, #128 ; 0x80
80048f0: 2b00 cmp r3, #0
80048f2: bf14 ite ne
80048f4: 2301 movne r3, #1
80048f6: 2300 moveq r3, #0
80048f8: b2db uxtb r3, r3
80048fa: 60fb str r3, [r7, #12]
if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
80048fc: 68bb ldr r3, [r7, #8]
80048fe: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8004902: b2db uxtb r3, r3
8004904: 2b21 cmp r3, #33 ; 0x21
8004906: d108 bne.n 800491a <UART_DMAError+0x46>
8004908: 68fb ldr r3, [r7, #12]
800490a: 2b00 cmp r3, #0
800490c: d005 beq.n 800491a <UART_DMAError+0x46>
{
huart->TxXferCount = 0x00U;
800490e: 68bb ldr r3, [r7, #8]
8004910: 2200 movs r2, #0
8004912: 84da strh r2, [r3, #38] ; 0x26
UART_EndTxTransfer(huart);
8004914: 68b8 ldr r0, [r7, #8]
8004916: f000 f871 bl 80049fc <UART_EndTxTransfer>
}
/* Stop UART DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
800491a: 68bb ldr r3, [r7, #8]
800491c: 681b ldr r3, [r3, #0]
800491e: 695b ldr r3, [r3, #20]
8004920: f003 0340 and.w r3, r3, #64 ; 0x40
8004924: 2b00 cmp r3, #0
8004926: bf14 ite ne
8004928: 2301 movne r3, #1
800492a: 2300 moveq r3, #0
800492c: b2db uxtb r3, r3
800492e: 60fb str r3, [r7, #12]
if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
8004930: 68bb ldr r3, [r7, #8]
8004932: f893 303a ldrb.w r3, [r3, #58] ; 0x3a
8004936: b2db uxtb r3, r3
8004938: 2b22 cmp r3, #34 ; 0x22
800493a: d108 bne.n 800494e <UART_DMAError+0x7a>
800493c: 68fb ldr r3, [r7, #12]
800493e: 2b00 cmp r3, #0
8004940: d005 beq.n 800494e <UART_DMAError+0x7a>
{
huart->RxXferCount = 0x00U;
8004942: 68bb ldr r3, [r7, #8]
8004944: 2200 movs r2, #0
8004946: 85da strh r2, [r3, #46] ; 0x2e
UART_EndRxTransfer(huart);
8004948: 68b8 ldr r0, [r7, #8]
800494a: f000 f86c bl 8004a26 <UART_EndRxTransfer>
}
huart->ErrorCode |= HAL_UART_ERROR_DMA;
800494e: 68bb ldr r3, [r7, #8]
8004950: 6bdb ldr r3, [r3, #60] ; 0x3c
8004952: f043 0210 orr.w r2, r3, #16
8004956: 68bb ldr r3, [r7, #8]
8004958: 63da str r2, [r3, #60] ; 0x3c
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800495a: 68b8 ldr r0, [r7, #8]
800495c: f7ff ff6f bl 800483e <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8004960: bf00 nop
8004962: 3710 adds r7, #16
8004964: 46bd mov sp, r7
8004966: bd80 pop {r7, pc}
08004968 <UART_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
8004968: b580 push {r7, lr}
800496a: b084 sub sp, #16
800496c: af00 add r7, sp, #0
800496e: 60f8 str r0, [r7, #12]
8004970: 60b9 str r1, [r7, #8]
8004972: 603b str r3, [r7, #0]
8004974: 4613 mov r3, r2
8004976: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004978: e02c b.n 80049d4 <UART_WaitOnFlagUntilTimeout+0x6c>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800497a: 69bb ldr r3, [r7, #24]
800497c: f1b3 3fff cmp.w r3, #4294967295
8004980: d028 beq.n 80049d4 <UART_WaitOnFlagUntilTimeout+0x6c>
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
8004982: 69bb ldr r3, [r7, #24]
8004984: 2b00 cmp r3, #0
8004986: d007 beq.n 8004998 <UART_WaitOnFlagUntilTimeout+0x30>
8004988: f7fc fde8 bl 800155c <HAL_GetTick>
800498c: 4602 mov r2, r0
800498e: 683b ldr r3, [r7, #0]
8004990: 1ad3 subs r3, r2, r3
8004992: 69ba ldr r2, [r7, #24]
8004994: 429a cmp r2, r3
8004996: d21d bcs.n 80049d4 <UART_WaitOnFlagUntilTimeout+0x6c>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
8004998: 68fb ldr r3, [r7, #12]
800499a: 681b ldr r3, [r3, #0]
800499c: 68da ldr r2, [r3, #12]
800499e: 68fb ldr r3, [r7, #12]
80049a0: 681b ldr r3, [r3, #0]
80049a2: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
80049a6: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80049a8: 68fb ldr r3, [r7, #12]
80049aa: 681b ldr r3, [r3, #0]
80049ac: 695a ldr r2, [r3, #20]
80049ae: 68fb ldr r3, [r7, #12]
80049b0: 681b ldr r3, [r3, #0]
80049b2: f022 0201 bic.w r2, r2, #1
80049b6: 615a str r2, [r3, #20]
huart->gState = HAL_UART_STATE_READY;
80049b8: 68fb ldr r3, [r7, #12]
80049ba: 2220 movs r2, #32
80049bc: f883 2039 strb.w r2, [r3, #57] ; 0x39
huart->RxState = HAL_UART_STATE_READY;
80049c0: 68fb ldr r3, [r7, #12]
80049c2: 2220 movs r2, #32
80049c4: f883 203a strb.w r2, [r3, #58] ; 0x3a
/* Process Unlocked */
__HAL_UNLOCK(huart);
80049c8: 68fb ldr r3, [r7, #12]
80049ca: 2200 movs r2, #0
80049cc: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
80049d0: 2303 movs r3, #3
80049d2: e00f b.n 80049f4 <UART_WaitOnFlagUntilTimeout+0x8c>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80049d4: 68fb ldr r3, [r7, #12]
80049d6: 681b ldr r3, [r3, #0]
80049d8: 681a ldr r2, [r3, #0]
80049da: 68bb ldr r3, [r7, #8]
80049dc: 4013 ands r3, r2
80049de: 68ba ldr r2, [r7, #8]
80049e0: 429a cmp r2, r3
80049e2: bf0c ite eq
80049e4: 2301 moveq r3, #1
80049e6: 2300 movne r3, #0
80049e8: b2db uxtb r3, r3
80049ea: 461a mov r2, r3
80049ec: 79fb ldrb r3, [r7, #7]
80049ee: 429a cmp r2, r3
80049f0: d0c3 beq.n 800497a <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
80049f2: 2300 movs r3, #0
}
80049f4: 4618 mov r0, r3
80049f6: 3710 adds r7, #16
80049f8: 46bd mov sp, r7
80049fa: bd80 pop {r7, pc}
080049fc <UART_EndTxTransfer>:
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
{
80049fc: b480 push {r7}
80049fe: b083 sub sp, #12
8004a00: af00 add r7, sp, #0
8004a02: 6078 str r0, [r7, #4]
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
8004a04: 687b ldr r3, [r7, #4]
8004a06: 681b ldr r3, [r3, #0]
8004a08: 68da ldr r2, [r3, #12]
8004a0a: 687b ldr r3, [r7, #4]
8004a0c: 681b ldr r3, [r3, #0]
8004a0e: f022 02c0 bic.w r2, r2, #192 ; 0xc0
8004a12: 60da str r2, [r3, #12]
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8004a14: 687b ldr r3, [r7, #4]
8004a16: 2220 movs r2, #32
8004a18: f883 2039 strb.w r2, [r3, #57] ; 0x39
}
8004a1c: bf00 nop
8004a1e: 370c adds r7, #12
8004a20: 46bd mov sp, r7
8004a22: bc80 pop {r7}
8004a24: 4770 bx lr
08004a26 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004a26: b480 push {r7}
8004a28: b083 sub sp, #12
8004a2a: af00 add r7, sp, #0
8004a2c: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004a2e: 687b ldr r3, [r7, #4]
8004a30: 681b ldr r3, [r3, #0]
8004a32: 68da ldr r2, [r3, #12]
8004a34: 687b ldr r3, [r7, #4]
8004a36: 681b ldr r3, [r3, #0]
8004a38: f422 7290 bic.w r2, r2, #288 ; 0x120
8004a3c: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004a3e: 687b ldr r3, [r7, #4]
8004a40: 681b ldr r3, [r3, #0]
8004a42: 695a ldr r2, [r3, #20]
8004a44: 687b ldr r3, [r7, #4]
8004a46: 681b ldr r3, [r3, #0]
8004a48: f022 0201 bic.w r2, r2, #1
8004a4c: 615a str r2, [r3, #20]
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004a4e: 687b ldr r3, [r7, #4]
8004a50: 2220 movs r2, #32
8004a52: f883 203a strb.w r2, [r3, #58] ; 0x3a
}
8004a56: bf00 nop
8004a58: 370c adds r7, #12
8004a5a: 46bd mov sp, r7
8004a5c: bc80 pop {r7}
8004a5e: 4770 bx lr
08004a60 <UART_DMAAbortOnError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
8004a60: b580 push {r7, lr}
8004a62: b084 sub sp, #16
8004a64: af00 add r7, sp, #0
8004a66: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8004a68: 687b ldr r3, [r7, #4]
8004a6a: 6a5b ldr r3, [r3, #36] ; 0x24
8004a6c: 60fb str r3, [r7, #12]
huart->RxXferCount = 0x00U;
8004a6e: 68fb ldr r3, [r7, #12]
8004a70: 2200 movs r2, #0
8004a72: 85da strh r2, [r3, #46] ; 0x2e
huart->TxXferCount = 0x00U;
8004a74: 68fb ldr r3, [r7, #12]
8004a76: 2200 movs r2, #0
8004a78: 84da strh r2, [r3, #38] ; 0x26
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8004a7a: 68f8 ldr r0, [r7, #12]
8004a7c: f7ff fedf bl 800483e <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8004a80: bf00 nop
8004a82: 3710 adds r7, #16
8004a84: 46bd mov sp, r7
8004a86: bd80 pop {r7, pc}
08004a88 <UART_Transmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
8004a88: b480 push {r7}
8004a8a: b085 sub sp, #20
8004a8c: af00 add r7, sp, #0
8004a8e: 6078 str r0, [r7, #4]
uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
8004a90: 687b ldr r3, [r7, #4]
8004a92: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8004a96: b2db uxtb r3, r3
8004a98: 2b21 cmp r3, #33 ; 0x21
8004a9a: d144 bne.n 8004b26 <UART_Transmit_IT+0x9e>
{
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
8004a9c: 687b ldr r3, [r7, #4]
8004a9e: 689b ldr r3, [r3, #8]
8004aa0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004aa4: d11a bne.n 8004adc <UART_Transmit_IT+0x54>
{
tmp = (uint16_t *) huart->pTxBuffPtr;
8004aa6: 687b ldr r3, [r7, #4]
8004aa8: 6a1b ldr r3, [r3, #32]
8004aaa: 60fb str r3, [r7, #12]
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
8004aac: 68fb ldr r3, [r7, #12]
8004aae: 881b ldrh r3, [r3, #0]
8004ab0: 461a mov r2, r3
8004ab2: 687b ldr r3, [r7, #4]
8004ab4: 681b ldr r3, [r3, #0]
8004ab6: f3c2 0208 ubfx r2, r2, #0, #9
8004aba: 605a str r2, [r3, #4]
if (huart->Init.Parity == UART_PARITY_NONE)
8004abc: 687b ldr r3, [r7, #4]
8004abe: 691b ldr r3, [r3, #16]
8004ac0: 2b00 cmp r3, #0
8004ac2: d105 bne.n 8004ad0 <UART_Transmit_IT+0x48>
{
huart->pTxBuffPtr += 2U;
8004ac4: 687b ldr r3, [r7, #4]
8004ac6: 6a1b ldr r3, [r3, #32]
8004ac8: 1c9a adds r2, r3, #2
8004aca: 687b ldr r3, [r7, #4]
8004acc: 621a str r2, [r3, #32]
8004ace: e00e b.n 8004aee <UART_Transmit_IT+0x66>
}
else
{
huart->pTxBuffPtr += 1U;
8004ad0: 687b ldr r3, [r7, #4]
8004ad2: 6a1b ldr r3, [r3, #32]
8004ad4: 1c5a adds r2, r3, #1
8004ad6: 687b ldr r3, [r7, #4]
8004ad8: 621a str r2, [r3, #32]
8004ada: e008 b.n 8004aee <UART_Transmit_IT+0x66>
}
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
8004adc: 687b ldr r3, [r7, #4]
8004ade: 6a1b ldr r3, [r3, #32]
8004ae0: 1c59 adds r1, r3, #1
8004ae2: 687a ldr r2, [r7, #4]
8004ae4: 6211 str r1, [r2, #32]
8004ae6: 781a ldrb r2, [r3, #0]
8004ae8: 687b ldr r3, [r7, #4]
8004aea: 681b ldr r3, [r3, #0]
8004aec: 605a str r2, [r3, #4]
}
if (--huart->TxXferCount == 0U)
8004aee: 687b ldr r3, [r7, #4]
8004af0: 8cdb ldrh r3, [r3, #38] ; 0x26
8004af2: b29b uxth r3, r3
8004af4: 3b01 subs r3, #1
8004af6: b29b uxth r3, r3
8004af8: 687a ldr r2, [r7, #4]
8004afa: 4619 mov r1, r3
8004afc: 84d1 strh r1, [r2, #38] ; 0x26
8004afe: 2b00 cmp r3, #0
8004b00: d10f bne.n 8004b22 <UART_Transmit_IT+0x9a>
{
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
8004b02: 687b ldr r3, [r7, #4]
8004b04: 681b ldr r3, [r3, #0]
8004b06: 68da ldr r2, [r3, #12]
8004b08: 687b ldr r3, [r7, #4]
8004b0a: 681b ldr r3, [r3, #0]
8004b0c: f022 0280 bic.w r2, r2, #128 ; 0x80
8004b10: 60da str r2, [r3, #12]
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
8004b12: 687b ldr r3, [r7, #4]
8004b14: 681b ldr r3, [r3, #0]
8004b16: 68da ldr r2, [r3, #12]
8004b18: 687b ldr r3, [r7, #4]
8004b1a: 681b ldr r3, [r3, #0]
8004b1c: f042 0240 orr.w r2, r2, #64 ; 0x40
8004b20: 60da str r2, [r3, #12]
}
return HAL_OK;
8004b22: 2300 movs r3, #0
8004b24: e000 b.n 8004b28 <UART_Transmit_IT+0xa0>
}
else
{
return HAL_BUSY;
8004b26: 2302 movs r3, #2
}
}
8004b28: 4618 mov r0, r3
8004b2a: 3714 adds r7, #20
8004b2c: 46bd mov sp, r7
8004b2e: bc80 pop {r7}
8004b30: 4770 bx lr
08004b32 <UART_EndTransmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
8004b32: b580 push {r7, lr}
8004b34: b082 sub sp, #8
8004b36: af00 add r7, sp, #0
8004b38: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
8004b3a: 687b ldr r3, [r7, #4]
8004b3c: 681b ldr r3, [r3, #0]
8004b3e: 68da ldr r2, [r3, #12]
8004b40: 687b ldr r3, [r7, #4]
8004b42: 681b ldr r3, [r3, #0]
8004b44: f022 0240 bic.w r2, r2, #64 ; 0x40
8004b48: 60da str r2, [r3, #12]
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8004b4a: 687b ldr r3, [r7, #4]
8004b4c: 2220 movs r2, #32
8004b4e: f883 2039 strb.w r2, [r3, #57] ; 0x39
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8004b52: 6878 ldr r0, [r7, #4]
8004b54: f7ff fe6a bl 800482c <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
8004b58: 2300 movs r3, #0
}
8004b5a: 4618 mov r0, r3
8004b5c: 3708 adds r7, #8
8004b5e: 46bd mov sp, r7
8004b60: bd80 pop {r7, pc}
08004b62 <UART_Receive_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
8004b62: b580 push {r7, lr}
8004b64: b084 sub sp, #16
8004b66: af00 add r7, sp, #0
8004b68: 6078 str r0, [r7, #4]
uint16_t *tmp;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8004b6a: 687b ldr r3, [r7, #4]
8004b6c: f893 303a ldrb.w r3, [r3, #58] ; 0x3a
8004b70: b2db uxtb r3, r3
8004b72: 2b22 cmp r3, #34 ; 0x22
8004b74: d171 bne.n 8004c5a <UART_Receive_IT+0xf8>
{
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
8004b76: 687b ldr r3, [r7, #4]
8004b78: 689b ldr r3, [r3, #8]
8004b7a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004b7e: d123 bne.n 8004bc8 <UART_Receive_IT+0x66>
{
tmp = (uint16_t *) huart->pRxBuffPtr;
8004b80: 687b ldr r3, [r7, #4]
8004b82: 6a9b ldr r3, [r3, #40] ; 0x28
8004b84: 60fb str r3, [r7, #12]
if (huart->Init.Parity == UART_PARITY_NONE)
8004b86: 687b ldr r3, [r7, #4]
8004b88: 691b ldr r3, [r3, #16]
8004b8a: 2b00 cmp r3, #0
8004b8c: d10e bne.n 8004bac <UART_Receive_IT+0x4a>
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
8004b8e: 687b ldr r3, [r7, #4]
8004b90: 681b ldr r3, [r3, #0]
8004b92: 685b ldr r3, [r3, #4]
8004b94: b29b uxth r3, r3
8004b96: f3c3 0308 ubfx r3, r3, #0, #9
8004b9a: b29a uxth r2, r3
8004b9c: 68fb ldr r3, [r7, #12]
8004b9e: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8004ba0: 687b ldr r3, [r7, #4]
8004ba2: 6a9b ldr r3, [r3, #40] ; 0x28
8004ba4: 1c9a adds r2, r3, #2
8004ba6: 687b ldr r3, [r7, #4]
8004ba8: 629a str r2, [r3, #40] ; 0x28
8004baa: e029 b.n 8004c00 <UART_Receive_IT+0x9e>
}
else
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
8004bac: 687b ldr r3, [r7, #4]
8004bae: 681b ldr r3, [r3, #0]
8004bb0: 685b ldr r3, [r3, #4]
8004bb2: b29b uxth r3, r3
8004bb4: b2db uxtb r3, r3
8004bb6: b29a uxth r2, r3
8004bb8: 68fb ldr r3, [r7, #12]
8004bba: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 1U;
8004bbc: 687b ldr r3, [r7, #4]
8004bbe: 6a9b ldr r3, [r3, #40] ; 0x28
8004bc0: 1c5a adds r2, r3, #1
8004bc2: 687b ldr r3, [r7, #4]
8004bc4: 629a str r2, [r3, #40] ; 0x28
8004bc6: e01b b.n 8004c00 <UART_Receive_IT+0x9e>
}
}
else
{
if (huart->Init.Parity == UART_PARITY_NONE)
8004bc8: 687b ldr r3, [r7, #4]
8004bca: 691b ldr r3, [r3, #16]
8004bcc: 2b00 cmp r3, #0
8004bce: d10a bne.n 8004be6 <UART_Receive_IT+0x84>
{
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
8004bd0: 687b ldr r3, [r7, #4]
8004bd2: 681b ldr r3, [r3, #0]
8004bd4: 6858 ldr r0, [r3, #4]
8004bd6: 687b ldr r3, [r7, #4]
8004bd8: 6a9b ldr r3, [r3, #40] ; 0x28
8004bda: 1c59 adds r1, r3, #1
8004bdc: 687a ldr r2, [r7, #4]
8004bde: 6291 str r1, [r2, #40] ; 0x28
8004be0: b2c2 uxtb r2, r0
8004be2: 701a strb r2, [r3, #0]
8004be4: e00c b.n 8004c00 <UART_Receive_IT+0x9e>
}
else
{
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
8004be6: 687b ldr r3, [r7, #4]
8004be8: 681b ldr r3, [r3, #0]
8004bea: 685b ldr r3, [r3, #4]
8004bec: b2da uxtb r2, r3
8004bee: 687b ldr r3, [r7, #4]
8004bf0: 6a9b ldr r3, [r3, #40] ; 0x28
8004bf2: 1c58 adds r0, r3, #1
8004bf4: 6879 ldr r1, [r7, #4]
8004bf6: 6288 str r0, [r1, #40] ; 0x28
8004bf8: f002 027f and.w r2, r2, #127 ; 0x7f
8004bfc: b2d2 uxtb r2, r2
8004bfe: 701a strb r2, [r3, #0]
}
}
if (--huart->RxXferCount == 0U)
8004c00: 687b ldr r3, [r7, #4]
8004c02: 8ddb ldrh r3, [r3, #46] ; 0x2e
8004c04: b29b uxth r3, r3
8004c06: 3b01 subs r3, #1
8004c08: b29b uxth r3, r3
8004c0a: 687a ldr r2, [r7, #4]
8004c0c: 4619 mov r1, r3
8004c0e: 85d1 strh r1, [r2, #46] ; 0x2e
8004c10: 2b00 cmp r3, #0
8004c12: d120 bne.n 8004c56 <UART_Receive_IT+0xf4>
{
/* Disable the UART Data Register not empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
8004c14: 687b ldr r3, [r7, #4]
8004c16: 681b ldr r3, [r3, #0]
8004c18: 68da ldr r2, [r3, #12]
8004c1a: 687b ldr r3, [r7, #4]
8004c1c: 681b ldr r3, [r3, #0]
8004c1e: f022 0220 bic.w r2, r2, #32
8004c22: 60da str r2, [r3, #12]
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
8004c24: 687b ldr r3, [r7, #4]
8004c26: 681b ldr r3, [r3, #0]
8004c28: 68da ldr r2, [r3, #12]
8004c2a: 687b ldr r3, [r7, #4]
8004c2c: 681b ldr r3, [r3, #0]
8004c2e: f422 7280 bic.w r2, r2, #256 ; 0x100
8004c32: 60da str r2, [r3, #12]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
8004c34: 687b ldr r3, [r7, #4]
8004c36: 681b ldr r3, [r3, #0]
8004c38: 695a ldr r2, [r3, #20]
8004c3a: 687b ldr r3, [r7, #4]
8004c3c: 681b ldr r3, [r3, #0]
8004c3e: f022 0201 bic.w r2, r2, #1
8004c42: 615a str r2, [r3, #20]
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004c44: 687b ldr r3, [r7, #4]
8004c46: 2220 movs r2, #32
8004c48: f883 203a strb.w r2, [r3, #58] ; 0x3a
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
8004c4c: 6878 ldr r0, [r7, #4]
8004c4e: f7fc f83b bl 8000cc8 <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
8004c52: 2300 movs r3, #0
8004c54: e002 b.n 8004c5c <UART_Receive_IT+0xfa>
}
return HAL_OK;
8004c56: 2300 movs r3, #0
8004c58: e000 b.n 8004c5c <UART_Receive_IT+0xfa>
}
else
{
return HAL_BUSY;
8004c5a: 2302 movs r3, #2
}
}
8004c5c: 4618 mov r0, r3
8004c5e: 3710 adds r7, #16
8004c60: 46bd mov sp, r7
8004c62: bd80 pop {r7, pc}
08004c64 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8004c64: b580 push {r7, lr}
8004c66: b084 sub sp, #16
8004c68: af00 add r7, sp, #0
8004c6a: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8004c6c: 687b ldr r3, [r7, #4]
8004c6e: 681b ldr r3, [r3, #0]
8004c70: 691b ldr r3, [r3, #16]
8004c72: f423 5140 bic.w r1, r3, #12288 ; 0x3000
8004c76: 687b ldr r3, [r7, #4]
8004c78: 68da ldr r2, [r3, #12]
8004c7a: 687b ldr r3, [r7, #4]
8004c7c: 681b ldr r3, [r3, #0]
8004c7e: 430a orrs r2, r1
8004c80: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
8004c82: 687b ldr r3, [r7, #4]
8004c84: 689a ldr r2, [r3, #8]
8004c86: 687b ldr r3, [r7, #4]
8004c88: 691b ldr r3, [r3, #16]
8004c8a: 431a orrs r2, r3
8004c8c: 687b ldr r3, [r7, #4]
8004c8e: 695b ldr r3, [r3, #20]
8004c90: 4313 orrs r3, r2
8004c92: 60fb str r3, [r7, #12]
MODIFY_REG(huart->Instance->CR1,
8004c94: 687b ldr r3, [r7, #4]
8004c96: 681b ldr r3, [r3, #0]
8004c98: 68db ldr r3, [r3, #12]
8004c9a: f423 53b0 bic.w r3, r3, #5632 ; 0x1600
8004c9e: f023 030c bic.w r3, r3, #12
8004ca2: 687a ldr r2, [r7, #4]
8004ca4: 6812 ldr r2, [r2, #0]
8004ca6: 68f9 ldr r1, [r7, #12]
8004ca8: 430b orrs r3, r1
8004caa: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8004cac: 687b ldr r3, [r7, #4]
8004cae: 681b ldr r3, [r3, #0]
8004cb0: 695b ldr r3, [r3, #20]
8004cb2: f423 7140 bic.w r1, r3, #768 ; 0x300
8004cb6: 687b ldr r3, [r7, #4]
8004cb8: 699a ldr r2, [r3, #24]
8004cba: 687b ldr r3, [r7, #4]
8004cbc: 681b ldr r3, [r3, #0]
8004cbe: 430a orrs r2, r1
8004cc0: 615a str r2, [r3, #20]
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
#else
/*-------------------------- USART BRR Configuration ---------------------*/
if(huart->Instance == USART1)
8004cc2: 687b ldr r3, [r7, #4]
8004cc4: 681b ldr r3, [r3, #0]
8004cc6: 4a52 ldr r2, [pc, #328] ; (8004e10 <UART_SetConfig+0x1ac>)
8004cc8: 4293 cmp r3, r2
8004cca: d14e bne.n 8004d6a <UART_SetConfig+0x106>
{
pclk = HAL_RCC_GetPCLK2Freq();
8004ccc: f7fe fd56 bl 800377c <HAL_RCC_GetPCLK2Freq>
8004cd0: 60b8 str r0, [r7, #8]
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8004cd2: 68ba ldr r2, [r7, #8]
8004cd4: 4613 mov r3, r2
8004cd6: 009b lsls r3, r3, #2
8004cd8: 4413 add r3, r2
8004cda: 009a lsls r2, r3, #2
8004cdc: 441a add r2, r3
8004cde: 687b ldr r3, [r7, #4]
8004ce0: 685b ldr r3, [r3, #4]
8004ce2: 009b lsls r3, r3, #2
8004ce4: fbb2 f3f3 udiv r3, r2, r3
8004ce8: 4a4a ldr r2, [pc, #296] ; (8004e14 <UART_SetConfig+0x1b0>)
8004cea: fba2 2303 umull r2, r3, r2, r3
8004cee: 095b lsrs r3, r3, #5
8004cf0: 0119 lsls r1, r3, #4
8004cf2: 68ba ldr r2, [r7, #8]
8004cf4: 4613 mov r3, r2
8004cf6: 009b lsls r3, r3, #2
8004cf8: 4413 add r3, r2
8004cfa: 009a lsls r2, r3, #2
8004cfc: 441a add r2, r3
8004cfe: 687b ldr r3, [r7, #4]
8004d00: 685b ldr r3, [r3, #4]
8004d02: 009b lsls r3, r3, #2
8004d04: fbb2 f2f3 udiv r2, r2, r3
8004d08: 4b42 ldr r3, [pc, #264] ; (8004e14 <UART_SetConfig+0x1b0>)
8004d0a: fba3 0302 umull r0, r3, r3, r2
8004d0e: 095b lsrs r3, r3, #5
8004d10: 2064 movs r0, #100 ; 0x64
8004d12: fb00 f303 mul.w r3, r0, r3
8004d16: 1ad3 subs r3, r2, r3
8004d18: 011b lsls r3, r3, #4
8004d1a: 3332 adds r3, #50 ; 0x32
8004d1c: 4a3d ldr r2, [pc, #244] ; (8004e14 <UART_SetConfig+0x1b0>)
8004d1e: fba2 2303 umull r2, r3, r2, r3
8004d22: 095b lsrs r3, r3, #5
8004d24: f003 03f0 and.w r3, r3, #240 ; 0xf0
8004d28: 4419 add r1, r3
8004d2a: 68ba ldr r2, [r7, #8]
8004d2c: 4613 mov r3, r2
8004d2e: 009b lsls r3, r3, #2
8004d30: 4413 add r3, r2
8004d32: 009a lsls r2, r3, #2
8004d34: 441a add r2, r3
8004d36: 687b ldr r3, [r7, #4]
8004d38: 685b ldr r3, [r3, #4]
8004d3a: 009b lsls r3, r3, #2
8004d3c: fbb2 f2f3 udiv r2, r2, r3
8004d40: 4b34 ldr r3, [pc, #208] ; (8004e14 <UART_SetConfig+0x1b0>)
8004d42: fba3 0302 umull r0, r3, r3, r2
8004d46: 095b lsrs r3, r3, #5
8004d48: 2064 movs r0, #100 ; 0x64
8004d4a: fb00 f303 mul.w r3, r0, r3
8004d4e: 1ad3 subs r3, r2, r3
8004d50: 011b lsls r3, r3, #4
8004d52: 3332 adds r3, #50 ; 0x32
8004d54: 4a2f ldr r2, [pc, #188] ; (8004e14 <UART_SetConfig+0x1b0>)
8004d56: fba2 2303 umull r2, r3, r2, r3
8004d5a: 095b lsrs r3, r3, #5
8004d5c: f003 020f and.w r2, r3, #15
8004d60: 687b ldr r3, [r7, #4]
8004d62: 681b ldr r3, [r3, #0]
8004d64: 440a add r2, r1
8004d66: 609a str r2, [r3, #8]
{
pclk = HAL_RCC_GetPCLK1Freq();
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#endif /* USART_CR1_OVER8 */
}
8004d68: e04d b.n 8004e06 <UART_SetConfig+0x1a2>
pclk = HAL_RCC_GetPCLK1Freq();
8004d6a: f7fe fcf3 bl 8003754 <HAL_RCC_GetPCLK1Freq>
8004d6e: 60b8 str r0, [r7, #8]
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8004d70: 68ba ldr r2, [r7, #8]
8004d72: 4613 mov r3, r2
8004d74: 009b lsls r3, r3, #2
8004d76: 4413 add r3, r2
8004d78: 009a lsls r2, r3, #2
8004d7a: 441a add r2, r3
8004d7c: 687b ldr r3, [r7, #4]
8004d7e: 685b ldr r3, [r3, #4]
8004d80: 009b lsls r3, r3, #2
8004d82: fbb2 f3f3 udiv r3, r2, r3
8004d86: 4a23 ldr r2, [pc, #140] ; (8004e14 <UART_SetConfig+0x1b0>)
8004d88: fba2 2303 umull r2, r3, r2, r3
8004d8c: 095b lsrs r3, r3, #5
8004d8e: 0119 lsls r1, r3, #4
8004d90: 68ba ldr r2, [r7, #8]
8004d92: 4613 mov r3, r2
8004d94: 009b lsls r3, r3, #2
8004d96: 4413 add r3, r2
8004d98: 009a lsls r2, r3, #2
8004d9a: 441a add r2, r3
8004d9c: 687b ldr r3, [r7, #4]
8004d9e: 685b ldr r3, [r3, #4]
8004da0: 009b lsls r3, r3, #2
8004da2: fbb2 f2f3 udiv r2, r2, r3
8004da6: 4b1b ldr r3, [pc, #108] ; (8004e14 <UART_SetConfig+0x1b0>)
8004da8: fba3 0302 umull r0, r3, r3, r2
8004dac: 095b lsrs r3, r3, #5
8004dae: 2064 movs r0, #100 ; 0x64
8004db0: fb00 f303 mul.w r3, r0, r3
8004db4: 1ad3 subs r3, r2, r3
8004db6: 011b lsls r3, r3, #4
8004db8: 3332 adds r3, #50 ; 0x32
8004dba: 4a16 ldr r2, [pc, #88] ; (8004e14 <UART_SetConfig+0x1b0>)
8004dbc: fba2 2303 umull r2, r3, r2, r3
8004dc0: 095b lsrs r3, r3, #5
8004dc2: f003 03f0 and.w r3, r3, #240 ; 0xf0
8004dc6: 4419 add r1, r3
8004dc8: 68ba ldr r2, [r7, #8]
8004dca: 4613 mov r3, r2
8004dcc: 009b lsls r3, r3, #2
8004dce: 4413 add r3, r2
8004dd0: 009a lsls r2, r3, #2
8004dd2: 441a add r2, r3
8004dd4: 687b ldr r3, [r7, #4]
8004dd6: 685b ldr r3, [r3, #4]
8004dd8: 009b lsls r3, r3, #2
8004dda: fbb2 f2f3 udiv r2, r2, r3
8004dde: 4b0d ldr r3, [pc, #52] ; (8004e14 <UART_SetConfig+0x1b0>)
8004de0: fba3 0302 umull r0, r3, r3, r2
8004de4: 095b lsrs r3, r3, #5
8004de6: 2064 movs r0, #100 ; 0x64
8004de8: fb00 f303 mul.w r3, r0, r3
8004dec: 1ad3 subs r3, r2, r3
8004dee: 011b lsls r3, r3, #4
8004df0: 3332 adds r3, #50 ; 0x32
8004df2: 4a08 ldr r2, [pc, #32] ; (8004e14 <UART_SetConfig+0x1b0>)
8004df4: fba2 2303 umull r2, r3, r2, r3
8004df8: 095b lsrs r3, r3, #5
8004dfa: f003 020f and.w r2, r3, #15
8004dfe: 687b ldr r3, [r7, #4]
8004e00: 681b ldr r3, [r3, #0]
8004e02: 440a add r2, r1
8004e04: 609a str r2, [r3, #8]
}
8004e06: bf00 nop
8004e08: 3710 adds r7, #16
8004e0a: 46bd mov sp, r7
8004e0c: bd80 pop {r7, pc}
8004e0e: bf00 nop
8004e10: 40013800 .word 0x40013800
8004e14: 51eb851f .word 0x51eb851f
08004e18 <USB_CoreInit>:
* @param cfg : pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8004e18: b084 sub sp, #16
8004e1a: b480 push {r7}
8004e1c: b083 sub sp, #12
8004e1e: af00 add r7, sp, #0
8004e20: 6078 str r0, [r7, #4]
8004e22: f107 0014 add.w r0, r7, #20
8004e26: e880 000e stmia.w r0, {r1, r2, r3}
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8004e2a: 2300 movs r3, #0
}
8004e2c: 4618 mov r0, r3
8004e2e: 370c adds r7, #12
8004e30: 46bd mov sp, r7
8004e32: bc80 pop {r7}
8004e34: b004 add sp, #16
8004e36: 4770 bx lr
08004e38 <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
8004e38: b480 push {r7}
8004e3a: b085 sub sp, #20
8004e3c: af00 add r7, sp, #0
8004e3e: 6078 str r0, [r7, #4]
uint16_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8004e40: f44f 433f mov.w r3, #48896 ; 0xbf00
8004e44: 81fb strh r3, [r7, #14]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Set interrupt mask */
USBx->CNTR |= winterruptmask;
8004e46: 687b ldr r3, [r7, #4]
8004e48: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40
8004e4c: b29a uxth r2, r3
8004e4e: 89fb ldrh r3, [r7, #14]
8004e50: 4313 orrs r3, r2
8004e52: b29a uxth r2, r3
8004e54: 687b ldr r3, [r7, #4]
8004e56: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
return HAL_OK;
8004e5a: 2300 movs r3, #0
}
8004e5c: 4618 mov r0, r3
8004e5e: 3714 adds r7, #20
8004e60: 46bd mov sp, r7
8004e62: bc80 pop {r7}
8004e64: 4770 bx lr
08004e66 <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
8004e66: b480 push {r7}
8004e68: b085 sub sp, #20
8004e6a: af00 add r7, sp, #0
8004e6c: 6078 str r0, [r7, #4]
uint16_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
8004e6e: f44f 433f mov.w r3, #48896 ; 0xbf00
8004e72: 81fb strh r3, [r7, #14]
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Clear interrupt mask */
USBx->CNTR &= ~winterruptmask;
8004e74: 687b ldr r3, [r7, #4]
8004e76: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40
8004e7a: b29b uxth r3, r3
8004e7c: b21a sxth r2, r3
8004e7e: f9b7 300e ldrsh.w r3, [r7, #14]
8004e82: 43db mvns r3, r3
8004e84: b21b sxth r3, r3
8004e86: 4013 ands r3, r2
8004e88: b21b sxth r3, r3
8004e8a: b29a uxth r2, r3
8004e8c: 687b ldr r3, [r7, #4]
8004e8e: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
return HAL_OK;
8004e92: 2300 movs r3, #0
}
8004e94: 4618 mov r0, r3
8004e96: 3714 adds r7, #20
8004e98: 46bd mov sp, r7
8004e9a: bc80 pop {r7}
8004e9c: 4770 bx lr
08004e9e <USB_SetCurrentMode>:
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE: Peripheral mode mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
{
8004e9e: b480 push {r7}
8004ea0: b083 sub sp, #12
8004ea2: af00 add r7, sp, #0
8004ea4: 6078 str r0, [r7, #4]
8004ea6: 460b mov r3, r1
8004ea8: 70fb strb r3, [r7, #3]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8004eaa: 2300 movs r3, #0
}
8004eac: 4618 mov r0, r3
8004eae: 370c adds r7, #12
8004eb0: 46bd mov sp, r7
8004eb2: bc80 pop {r7}
8004eb4: 4770 bx lr
08004eb6 <USB_DevInit>:
* @param cfg : pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
8004eb6: b084 sub sp, #16
8004eb8: b580 push {r7, lr}
8004eba: b082 sub sp, #8
8004ebc: af00 add r7, sp, #0
8004ebe: 6078 str r0, [r7, #4]
8004ec0: f107 0014 add.w r0, r7, #20
8004ec4: e880 000e stmia.w r0, {r1, r2, r3}
/* Prevent unused argument(s) compilation warning */
UNUSED(cfg);
/* Init Device */
/*CNTR_FRES = 1*/
USBx->CNTR = USB_CNTR_FRES;
8004ec8: 687b ldr r3, [r7, #4]
8004eca: 2201 movs r2, #1
8004ecc: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/*CNTR_FRES = 0*/
USBx->CNTR = 0;
8004ed0: 687b ldr r3, [r7, #4]
8004ed2: 2200 movs r2, #0
8004ed4: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/*Clear pending interrupts*/
USBx->ISTR = 0;
8004ed8: 687b ldr r3, [r7, #4]
8004eda: 2200 movs r2, #0
8004edc: f8a3 2044 strh.w r2, [r3, #68] ; 0x44
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
8004ee0: 687b ldr r3, [r7, #4]
8004ee2: 2200 movs r2, #0
8004ee4: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
/* Enable USB Device Interrupt mask */
(void)USB_EnableGlobalInt(USBx);
8004ee8: 6878 ldr r0, [r7, #4]
8004eea: f7ff ffa5 bl 8004e38 <USB_EnableGlobalInt>
return HAL_OK;
8004eee: 2300 movs r3, #0
}
8004ef0: 4618 mov r0, r3
8004ef2: 3708 adds r7, #8
8004ef4: 46bd mov sp, r7
8004ef6: e8bd 4080 ldmia.w sp!, {r7, lr}
8004efa: b004 add sp, #16
8004efc: 4770 bx lr
...
08004f00 <USB_ActivateEndpoint>:
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8004f00: b490 push {r4, r7}
8004f02: b084 sub sp, #16
8004f04: af00 add r7, sp, #0
8004f06: 6078 str r0, [r7, #4]
8004f08: 6039 str r1, [r7, #0]
HAL_StatusTypeDef ret = HAL_OK;
8004f0a: 2300 movs r3, #0
8004f0c: 73fb strb r3, [r7, #15]
uint16_t wEpRegVal;
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
8004f0e: 687a ldr r2, [r7, #4]
8004f10: 683b ldr r3, [r7, #0]
8004f12: 781b ldrb r3, [r3, #0]
8004f14: 009b lsls r3, r3, #2
8004f16: 4413 add r3, r2
8004f18: 881b ldrh r3, [r3, #0]
8004f1a: b29b uxth r3, r3
8004f1c: f423 43ec bic.w r3, r3, #30208 ; 0x7600
8004f20: f023 0370 bic.w r3, r3, #112 ; 0x70
8004f24: 81bb strh r3, [r7, #12]
/* initialize Endpoint */
switch (ep->type)
8004f26: 683b ldr r3, [r7, #0]
8004f28: 78db ldrb r3, [r3, #3]
8004f2a: 2b03 cmp r3, #3
8004f2c: d819 bhi.n 8004f62 <USB_ActivateEndpoint+0x62>
8004f2e: a201 add r2, pc, #4 ; (adr r2, 8004f34 <USB_ActivateEndpoint+0x34>)
8004f30: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004f34: 08004f45 .word 0x08004f45
8004f38: 08004f59 .word 0x08004f59
8004f3c: 08004f69 .word 0x08004f69
8004f40: 08004f4f .word 0x08004f4f
{
case EP_TYPE_CTRL:
wEpRegVal |= USB_EP_CONTROL;
8004f44: 89bb ldrh r3, [r7, #12]
8004f46: f443 7300 orr.w r3, r3, #512 ; 0x200
8004f4a: 81bb strh r3, [r7, #12]
break;
8004f4c: e00d b.n 8004f6a <USB_ActivateEndpoint+0x6a>
case EP_TYPE_BULK:
wEpRegVal |= USB_EP_BULK;
break;
case EP_TYPE_INTR:
wEpRegVal |= USB_EP_INTERRUPT;
8004f4e: 89bb ldrh r3, [r7, #12]
8004f50: f443 63c0 orr.w r3, r3, #1536 ; 0x600
8004f54: 81bb strh r3, [r7, #12]
break;
8004f56: e008 b.n 8004f6a <USB_ActivateEndpoint+0x6a>
case EP_TYPE_ISOC:
wEpRegVal |= USB_EP_ISOCHRONOUS;
8004f58: 89bb ldrh r3, [r7, #12]
8004f5a: f443 6380 orr.w r3, r3, #1024 ; 0x400
8004f5e: 81bb strh r3, [r7, #12]
break;
8004f60: e003 b.n 8004f6a <USB_ActivateEndpoint+0x6a>
default:
ret = HAL_ERROR;
8004f62: 2301 movs r3, #1
8004f64: 73fb strb r3, [r7, #15]
break;
8004f66: e000 b.n 8004f6a <USB_ActivateEndpoint+0x6a>
break;
8004f68: bf00 nop
}
PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX);
8004f6a: 687a ldr r2, [r7, #4]
8004f6c: 683b ldr r3, [r7, #0]
8004f6e: 781b ldrb r3, [r3, #0]
8004f70: 009b lsls r3, r3, #2
8004f72: 441a add r2, r3
8004f74: 89bb ldrh r3, [r7, #12]
8004f76: f043 437f orr.w r3, r3, #4278190080 ; 0xff000000
8004f7a: f443 037f orr.w r3, r3, #16711680 ; 0xff0000
8004f7e: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8004f82: f043 0380 orr.w r3, r3, #128 ; 0x80
8004f86: b29b uxth r3, r3
8004f88: 8013 strh r3, [r2, #0]
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
8004f8a: 687a ldr r2, [r7, #4]
8004f8c: 683b ldr r3, [r7, #0]
8004f8e: 781b ldrb r3, [r3, #0]
8004f90: 009b lsls r3, r3, #2
8004f92: 4413 add r3, r2
8004f94: 881b ldrh r3, [r3, #0]
8004f96: b29b uxth r3, r3
8004f98: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8004f9c: f023 0370 bic.w r3, r3, #112 ; 0x70
8004fa0: b29a uxth r2, r3
8004fa2: 683b ldr r3, [r7, #0]
8004fa4: 781b ldrb r3, [r3, #0]
8004fa6: b29b uxth r3, r3
8004fa8: 4313 orrs r3, r2
8004faa: b29c uxth r4, r3
8004fac: 687a ldr r2, [r7, #4]
8004fae: 683b ldr r3, [r7, #0]
8004fb0: 781b ldrb r3, [r3, #0]
8004fb2: 009b lsls r3, r3, #2
8004fb4: 441a add r2, r3
8004fb6: 4b8a ldr r3, [pc, #552] ; (80051e0 <USB_ActivateEndpoint+0x2e0>)
8004fb8: 4323 orrs r3, r4
8004fba: b29b uxth r3, r3
8004fbc: 8013 strh r3, [r2, #0]
if (ep->doublebuffer == 0U)
8004fbe: 683b ldr r3, [r7, #0]
8004fc0: 7b1b ldrb r3, [r3, #12]
8004fc2: 2b00 cmp r3, #0
8004fc4: f040 8112 bne.w 80051ec <USB_ActivateEndpoint+0x2ec>
{
if (ep->is_in != 0U)
8004fc8: 683b ldr r3, [r7, #0]
8004fca: 785b ldrb r3, [r3, #1]
8004fcc: 2b00 cmp r3, #0
8004fce: d067 beq.n 80050a0 <USB_ActivateEndpoint+0x1a0>
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
8004fd0: 687c ldr r4, [r7, #4]
8004fd2: 687b ldr r3, [r7, #4]
8004fd4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8004fd8: b29b uxth r3, r3
8004fda: 441c add r4, r3
8004fdc: 683b ldr r3, [r7, #0]
8004fde: 781b ldrb r3, [r3, #0]
8004fe0: 011b lsls r3, r3, #4
8004fe2: 4423 add r3, r4
8004fe4: f503 6380 add.w r3, r3, #1024 ; 0x400
8004fe8: 461c mov r4, r3
8004fea: 683b ldr r3, [r7, #0]
8004fec: 88db ldrh r3, [r3, #6]
8004fee: 085b lsrs r3, r3, #1
8004ff0: b29b uxth r3, r3
8004ff2: 005b lsls r3, r3, #1
8004ff4: b29b uxth r3, r3
8004ff6: 8023 strh r3, [r4, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8004ff8: 687a ldr r2, [r7, #4]
8004ffa: 683b ldr r3, [r7, #0]
8004ffc: 781b ldrb r3, [r3, #0]
8004ffe: 009b lsls r3, r3, #2
8005000: 4413 add r3, r2
8005002: 881b ldrh r3, [r3, #0]
8005004: b29c uxth r4, r3
8005006: 4623 mov r3, r4
8005008: f003 0340 and.w r3, r3, #64 ; 0x40
800500c: 2b00 cmp r3, #0
800500e: d014 beq.n 800503a <USB_ActivateEndpoint+0x13a>
8005010: 687a ldr r2, [r7, #4]
8005012: 683b ldr r3, [r7, #0]
8005014: 781b ldrb r3, [r3, #0]
8005016: 009b lsls r3, r3, #2
8005018: 4413 add r3, r2
800501a: 881b ldrh r3, [r3, #0]
800501c: b29b uxth r3, r3
800501e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005022: f023 0370 bic.w r3, r3, #112 ; 0x70
8005026: b29c uxth r4, r3
8005028: 687a ldr r2, [r7, #4]
800502a: 683b ldr r3, [r7, #0]
800502c: 781b ldrb r3, [r3, #0]
800502e: 009b lsls r3, r3, #2
8005030: 441a add r2, r3
8005032: 4b6c ldr r3, [pc, #432] ; (80051e4 <USB_ActivateEndpoint+0x2e4>)
8005034: 4323 orrs r3, r4
8005036: b29b uxth r3, r3
8005038: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800503a: 683b ldr r3, [r7, #0]
800503c: 78db ldrb r3, [r3, #3]
800503e: 2b01 cmp r3, #1
8005040: d018 beq.n 8005074 <USB_ActivateEndpoint+0x174>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8005042: 687a ldr r2, [r7, #4]
8005044: 683b ldr r3, [r7, #0]
8005046: 781b ldrb r3, [r3, #0]
8005048: 009b lsls r3, r3, #2
800504a: 4413 add r3, r2
800504c: 881b ldrh r3, [r3, #0]
800504e: b29b uxth r3, r3
8005050: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005054: f023 0340 bic.w r3, r3, #64 ; 0x40
8005058: b29c uxth r4, r3
800505a: f084 0320 eor.w r3, r4, #32
800505e: b29c uxth r4, r3
8005060: 687a ldr r2, [r7, #4]
8005062: 683b ldr r3, [r7, #0]
8005064: 781b ldrb r3, [r3, #0]
8005066: 009b lsls r3, r3, #2
8005068: 441a add r2, r3
800506a: 4b5d ldr r3, [pc, #372] ; (80051e0 <USB_ActivateEndpoint+0x2e0>)
800506c: 4323 orrs r3, r4
800506e: b29b uxth r3, r3
8005070: 8013 strh r3, [r2, #0]
8005072: e22b b.n 80054cc <USB_ActivateEndpoint+0x5cc>
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8005074: 687a ldr r2, [r7, #4]
8005076: 683b ldr r3, [r7, #0]
8005078: 781b ldrb r3, [r3, #0]
800507a: 009b lsls r3, r3, #2
800507c: 4413 add r3, r2
800507e: 881b ldrh r3, [r3, #0]
8005080: b29b uxth r3, r3
8005082: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005086: f023 0340 bic.w r3, r3, #64 ; 0x40
800508a: b29c uxth r4, r3
800508c: 687a ldr r2, [r7, #4]
800508e: 683b ldr r3, [r7, #0]
8005090: 781b ldrb r3, [r3, #0]
8005092: 009b lsls r3, r3, #2
8005094: 441a add r2, r3
8005096: 4b52 ldr r3, [pc, #328] ; (80051e0 <USB_ActivateEndpoint+0x2e0>)
8005098: 4323 orrs r3, r4
800509a: b29b uxth r3, r3
800509c: 8013 strh r3, [r2, #0]
800509e: e215 b.n 80054cc <USB_ActivateEndpoint+0x5cc>
}
}
else
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
80050a0: 687c ldr r4, [r7, #4]
80050a2: 687b ldr r3, [r7, #4]
80050a4: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
80050a8: b29b uxth r3, r3
80050aa: 441c add r4, r3
80050ac: 683b ldr r3, [r7, #0]
80050ae: 781b ldrb r3, [r3, #0]
80050b0: 011b lsls r3, r3, #4
80050b2: 4423 add r3, r4
80050b4: f503 6381 add.w r3, r3, #1032 ; 0x408
80050b8: 461c mov r4, r3
80050ba: 683b ldr r3, [r7, #0]
80050bc: 88db ldrh r3, [r3, #6]
80050be: 085b lsrs r3, r3, #1
80050c0: b29b uxth r3, r3
80050c2: 005b lsls r3, r3, #1
80050c4: b29b uxth r3, r3
80050c6: 8023 strh r3, [r4, #0]
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
80050c8: 687c ldr r4, [r7, #4]
80050ca: 687b ldr r3, [r7, #4]
80050cc: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
80050d0: b29b uxth r3, r3
80050d2: 441c add r4, r3
80050d4: 683b ldr r3, [r7, #0]
80050d6: 781b ldrb r3, [r3, #0]
80050d8: 011b lsls r3, r3, #4
80050da: 4423 add r3, r4
80050dc: f203 430c addw r3, r3, #1036 ; 0x40c
80050e0: 461c mov r4, r3
80050e2: 683b ldr r3, [r7, #0]
80050e4: 691b ldr r3, [r3, #16]
80050e6: 2b00 cmp r3, #0
80050e8: d10e bne.n 8005108 <USB_ActivateEndpoint+0x208>
80050ea: 8823 ldrh r3, [r4, #0]
80050ec: b29b uxth r3, r3
80050ee: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
80050f2: b29b uxth r3, r3
80050f4: 8023 strh r3, [r4, #0]
80050f6: 8823 ldrh r3, [r4, #0]
80050f8: b29b uxth r3, r3
80050fa: ea6f 4343 mvn.w r3, r3, lsl #17
80050fe: ea6f 4353 mvn.w r3, r3, lsr #17
8005102: b29b uxth r3, r3
8005104: 8023 strh r3, [r4, #0]
8005106: e02d b.n 8005164 <USB_ActivateEndpoint+0x264>
8005108: 683b ldr r3, [r7, #0]
800510a: 691b ldr r3, [r3, #16]
800510c: 2b3e cmp r3, #62 ; 0x3e
800510e: d812 bhi.n 8005136 <USB_ActivateEndpoint+0x236>
8005110: 683b ldr r3, [r7, #0]
8005112: 691b ldr r3, [r3, #16]
8005114: 085b lsrs r3, r3, #1
8005116: 60bb str r3, [r7, #8]
8005118: 683b ldr r3, [r7, #0]
800511a: 691b ldr r3, [r3, #16]
800511c: f003 0301 and.w r3, r3, #1
8005120: 2b00 cmp r3, #0
8005122: d002 beq.n 800512a <USB_ActivateEndpoint+0x22a>
8005124: 68bb ldr r3, [r7, #8]
8005126: 3301 adds r3, #1
8005128: 60bb str r3, [r7, #8]
800512a: 68bb ldr r3, [r7, #8]
800512c: b29b uxth r3, r3
800512e: 029b lsls r3, r3, #10
8005130: b29b uxth r3, r3
8005132: 8023 strh r3, [r4, #0]
8005134: e016 b.n 8005164 <USB_ActivateEndpoint+0x264>
8005136: 683b ldr r3, [r7, #0]
8005138: 691b ldr r3, [r3, #16]
800513a: 095b lsrs r3, r3, #5
800513c: 60bb str r3, [r7, #8]
800513e: 683b ldr r3, [r7, #0]
8005140: 691b ldr r3, [r3, #16]
8005142: f003 031f and.w r3, r3, #31
8005146: 2b00 cmp r3, #0
8005148: d102 bne.n 8005150 <USB_ActivateEndpoint+0x250>
800514a: 68bb ldr r3, [r7, #8]
800514c: 3b01 subs r3, #1
800514e: 60bb str r3, [r7, #8]
8005150: 68bb ldr r3, [r7, #8]
8005152: b29b uxth r3, r3
8005154: 029b lsls r3, r3, #10
8005156: b29b uxth r3, r3
8005158: ea6f 4343 mvn.w r3, r3, lsl #17
800515c: ea6f 4353 mvn.w r3, r3, lsr #17
8005160: b29b uxth r3, r3
8005162: 8023 strh r3, [r4, #0]
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8005164: 687a ldr r2, [r7, #4]
8005166: 683b ldr r3, [r7, #0]
8005168: 781b ldrb r3, [r3, #0]
800516a: 009b lsls r3, r3, #2
800516c: 4413 add r3, r2
800516e: 881b ldrh r3, [r3, #0]
8005170: b29c uxth r4, r3
8005172: 4623 mov r3, r4
8005174: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005178: 2b00 cmp r3, #0
800517a: d014 beq.n 80051a6 <USB_ActivateEndpoint+0x2a6>
800517c: 687a ldr r2, [r7, #4]
800517e: 683b ldr r3, [r7, #0]
8005180: 781b ldrb r3, [r3, #0]
8005182: 009b lsls r3, r3, #2
8005184: 4413 add r3, r2
8005186: 881b ldrh r3, [r3, #0]
8005188: b29b uxth r3, r3
800518a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
800518e: f023 0370 bic.w r3, r3, #112 ; 0x70
8005192: b29c uxth r4, r3
8005194: 687a ldr r2, [r7, #4]
8005196: 683b ldr r3, [r7, #0]
8005198: 781b ldrb r3, [r3, #0]
800519a: 009b lsls r3, r3, #2
800519c: 441a add r2, r3
800519e: 4b12 ldr r3, [pc, #72] ; (80051e8 <USB_ActivateEndpoint+0x2e8>)
80051a0: 4323 orrs r3, r4
80051a2: b29b uxth r3, r3
80051a4: 8013 strh r3, [r2, #0]
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
80051a6: 687a ldr r2, [r7, #4]
80051a8: 683b ldr r3, [r7, #0]
80051aa: 781b ldrb r3, [r3, #0]
80051ac: 009b lsls r3, r3, #2
80051ae: 4413 add r3, r2
80051b0: 881b ldrh r3, [r3, #0]
80051b2: b29b uxth r3, r3
80051b4: f423 4380 bic.w r3, r3, #16384 ; 0x4000
80051b8: f023 0370 bic.w r3, r3, #112 ; 0x70
80051bc: b29c uxth r4, r3
80051be: f484 5380 eor.w r3, r4, #4096 ; 0x1000
80051c2: b29c uxth r4, r3
80051c4: f484 5300 eor.w r3, r4, #8192 ; 0x2000
80051c8: b29c uxth r4, r3
80051ca: 687a ldr r2, [r7, #4]
80051cc: 683b ldr r3, [r7, #0]
80051ce: 781b ldrb r3, [r3, #0]
80051d0: 009b lsls r3, r3, #2
80051d2: 441a add r2, r3
80051d4: 4b02 ldr r3, [pc, #8] ; (80051e0 <USB_ActivateEndpoint+0x2e0>)
80051d6: 4323 orrs r3, r4
80051d8: b29b uxth r3, r3
80051da: 8013 strh r3, [r2, #0]
80051dc: e176 b.n 80054cc <USB_ActivateEndpoint+0x5cc>
80051de: bf00 nop
80051e0: ffff8080 .word 0xffff8080
80051e4: ffff80c0 .word 0xffff80c0
80051e8: ffffc080 .word 0xffffc080
}
/*Double Buffer*/
else
{
/* Set the endpoint as double buffered */
PCD_SET_EP_DBUF(USBx, ep->num);
80051ec: 687a ldr r2, [r7, #4]
80051ee: 683b ldr r3, [r7, #0]
80051f0: 781b ldrb r3, [r3, #0]
80051f2: 009b lsls r3, r3, #2
80051f4: 4413 add r3, r2
80051f6: 881b ldrh r3, [r3, #0]
80051f8: b29b uxth r3, r3
80051fa: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80051fe: f023 0370 bic.w r3, r3, #112 ; 0x70
8005202: b29c uxth r4, r3
8005204: 687a ldr r2, [r7, #4]
8005206: 683b ldr r3, [r7, #0]
8005208: 781b ldrb r3, [r3, #0]
800520a: 009b lsls r3, r3, #2
800520c: 441a add r2, r3
800520e: 4b96 ldr r3, [pc, #600] ; (8005468 <USB_ActivateEndpoint+0x568>)
8005210: 4323 orrs r3, r4
8005212: b29b uxth r3, r3
8005214: 8013 strh r3, [r2, #0]
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
8005216: 687c ldr r4, [r7, #4]
8005218: 687b ldr r3, [r7, #4]
800521a: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
800521e: b29b uxth r3, r3
8005220: 441c add r4, r3
8005222: 683b ldr r3, [r7, #0]
8005224: 781b ldrb r3, [r3, #0]
8005226: 011b lsls r3, r3, #4
8005228: 4423 add r3, r4
800522a: f503 6380 add.w r3, r3, #1024 ; 0x400
800522e: 461c mov r4, r3
8005230: 683b ldr r3, [r7, #0]
8005232: 891b ldrh r3, [r3, #8]
8005234: 085b lsrs r3, r3, #1
8005236: b29b uxth r3, r3
8005238: 005b lsls r3, r3, #1
800523a: b29b uxth r3, r3
800523c: 8023 strh r3, [r4, #0]
800523e: 687c ldr r4, [r7, #4]
8005240: 687b ldr r3, [r7, #4]
8005242: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005246: b29b uxth r3, r3
8005248: 441c add r4, r3
800524a: 683b ldr r3, [r7, #0]
800524c: 781b ldrb r3, [r3, #0]
800524e: 011b lsls r3, r3, #4
8005250: 4423 add r3, r4
8005252: f503 6381 add.w r3, r3, #1032 ; 0x408
8005256: 461c mov r4, r3
8005258: 683b ldr r3, [r7, #0]
800525a: 895b ldrh r3, [r3, #10]
800525c: 085b lsrs r3, r3, #1
800525e: b29b uxth r3, r3
8005260: 005b lsls r3, r3, #1
8005262: b29b uxth r3, r3
8005264: 8023 strh r3, [r4, #0]
if (ep->is_in == 0U)
8005266: 683b ldr r3, [r7, #0]
8005268: 785b ldrb r3, [r3, #1]
800526a: 2b00 cmp r3, #0
800526c: f040 8088 bne.w 8005380 <USB_ActivateEndpoint+0x480>
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8005270: 687a ldr r2, [r7, #4]
8005272: 683b ldr r3, [r7, #0]
8005274: 781b ldrb r3, [r3, #0]
8005276: 009b lsls r3, r3, #2
8005278: 4413 add r3, r2
800527a: 881b ldrh r3, [r3, #0]
800527c: b29c uxth r4, r3
800527e: 4623 mov r3, r4
8005280: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005284: 2b00 cmp r3, #0
8005286: d014 beq.n 80052b2 <USB_ActivateEndpoint+0x3b2>
8005288: 687a ldr r2, [r7, #4]
800528a: 683b ldr r3, [r7, #0]
800528c: 781b ldrb r3, [r3, #0]
800528e: 009b lsls r3, r3, #2
8005290: 4413 add r3, r2
8005292: 881b ldrh r3, [r3, #0]
8005294: b29b uxth r3, r3
8005296: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
800529a: f023 0370 bic.w r3, r3, #112 ; 0x70
800529e: b29c uxth r4, r3
80052a0: 687a ldr r2, [r7, #4]
80052a2: 683b ldr r3, [r7, #0]
80052a4: 781b ldrb r3, [r3, #0]
80052a6: 009b lsls r3, r3, #2
80052a8: 441a add r2, r3
80052aa: 4b70 ldr r3, [pc, #448] ; (800546c <USB_ActivateEndpoint+0x56c>)
80052ac: 4323 orrs r3, r4
80052ae: b29b uxth r3, r3
80052b0: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80052b2: 687a ldr r2, [r7, #4]
80052b4: 683b ldr r3, [r7, #0]
80052b6: 781b ldrb r3, [r3, #0]
80052b8: 009b lsls r3, r3, #2
80052ba: 4413 add r3, r2
80052bc: 881b ldrh r3, [r3, #0]
80052be: b29c uxth r4, r3
80052c0: 4623 mov r3, r4
80052c2: f003 0340 and.w r3, r3, #64 ; 0x40
80052c6: 2b00 cmp r3, #0
80052c8: d014 beq.n 80052f4 <USB_ActivateEndpoint+0x3f4>
80052ca: 687a ldr r2, [r7, #4]
80052cc: 683b ldr r3, [r7, #0]
80052ce: 781b ldrb r3, [r3, #0]
80052d0: 009b lsls r3, r3, #2
80052d2: 4413 add r3, r2
80052d4: 881b ldrh r3, [r3, #0]
80052d6: b29b uxth r3, r3
80052d8: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80052dc: f023 0370 bic.w r3, r3, #112 ; 0x70
80052e0: b29c uxth r4, r3
80052e2: 687a ldr r2, [r7, #4]
80052e4: 683b ldr r3, [r7, #0]
80052e6: 781b ldrb r3, [r3, #0]
80052e8: 009b lsls r3, r3, #2
80052ea: 441a add r2, r3
80052ec: 4b60 ldr r3, [pc, #384] ; (8005470 <USB_ActivateEndpoint+0x570>)
80052ee: 4323 orrs r3, r4
80052f0: b29b uxth r3, r3
80052f2: 8013 strh r3, [r2, #0]
/* Reset value of the data toggle bits for the endpoint out */
PCD_TX_DTOG(USBx, ep->num);
80052f4: 687a ldr r2, [r7, #4]
80052f6: 683b ldr r3, [r7, #0]
80052f8: 781b ldrb r3, [r3, #0]
80052fa: 009b lsls r3, r3, #2
80052fc: 4413 add r3, r2
80052fe: 881b ldrh r3, [r3, #0]
8005300: b29b uxth r3, r3
8005302: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005306: f023 0370 bic.w r3, r3, #112 ; 0x70
800530a: b29c uxth r4, r3
800530c: 687a ldr r2, [r7, #4]
800530e: 683b ldr r3, [r7, #0]
8005310: 781b ldrb r3, [r3, #0]
8005312: 009b lsls r3, r3, #2
8005314: 441a add r2, r3
8005316: 4b56 ldr r3, [pc, #344] ; (8005470 <USB_ActivateEndpoint+0x570>)
8005318: 4323 orrs r3, r4
800531a: b29b uxth r3, r3
800531c: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
800531e: 687a ldr r2, [r7, #4]
8005320: 683b ldr r3, [r7, #0]
8005322: 781b ldrb r3, [r3, #0]
8005324: 009b lsls r3, r3, #2
8005326: 4413 add r3, r2
8005328: 881b ldrh r3, [r3, #0]
800532a: b29b uxth r3, r3
800532c: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8005330: f023 0370 bic.w r3, r3, #112 ; 0x70
8005334: b29c uxth r4, r3
8005336: f484 5380 eor.w r3, r4, #4096 ; 0x1000
800533a: b29c uxth r4, r3
800533c: f484 5300 eor.w r3, r4, #8192 ; 0x2000
8005340: b29c uxth r4, r3
8005342: 687a ldr r2, [r7, #4]
8005344: 683b ldr r3, [r7, #0]
8005346: 781b ldrb r3, [r3, #0]
8005348: 009b lsls r3, r3, #2
800534a: 441a add r2, r3
800534c: 4b49 ldr r3, [pc, #292] ; (8005474 <USB_ActivateEndpoint+0x574>)
800534e: 4323 orrs r3, r4
8005350: b29b uxth r3, r3
8005352: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8005354: 687a ldr r2, [r7, #4]
8005356: 683b ldr r3, [r7, #0]
8005358: 781b ldrb r3, [r3, #0]
800535a: 009b lsls r3, r3, #2
800535c: 4413 add r3, r2
800535e: 881b ldrh r3, [r3, #0]
8005360: b29b uxth r3, r3
8005362: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005366: f023 0340 bic.w r3, r3, #64 ; 0x40
800536a: b29c uxth r4, r3
800536c: 687a ldr r2, [r7, #4]
800536e: 683b ldr r3, [r7, #0]
8005370: 781b ldrb r3, [r3, #0]
8005372: 009b lsls r3, r3, #2
8005374: 441a add r2, r3
8005376: 4b3f ldr r3, [pc, #252] ; (8005474 <USB_ActivateEndpoint+0x574>)
8005378: 4323 orrs r3, r4
800537a: b29b uxth r3, r3
800537c: 8013 strh r3, [r2, #0]
800537e: e0a5 b.n 80054cc <USB_ActivateEndpoint+0x5cc>
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8005380: 687a ldr r2, [r7, #4]
8005382: 683b ldr r3, [r7, #0]
8005384: 781b ldrb r3, [r3, #0]
8005386: 009b lsls r3, r3, #2
8005388: 4413 add r3, r2
800538a: 881b ldrh r3, [r3, #0]
800538c: b29c uxth r4, r3
800538e: 4623 mov r3, r4
8005390: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005394: 2b00 cmp r3, #0
8005396: d014 beq.n 80053c2 <USB_ActivateEndpoint+0x4c2>
8005398: 687a ldr r2, [r7, #4]
800539a: 683b ldr r3, [r7, #0]
800539c: 781b ldrb r3, [r3, #0]
800539e: 009b lsls r3, r3, #2
80053a0: 4413 add r3, r2
80053a2: 881b ldrh r3, [r3, #0]
80053a4: b29b uxth r3, r3
80053a6: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80053aa: f023 0370 bic.w r3, r3, #112 ; 0x70
80053ae: b29c uxth r4, r3
80053b0: 687a ldr r2, [r7, #4]
80053b2: 683b ldr r3, [r7, #0]
80053b4: 781b ldrb r3, [r3, #0]
80053b6: 009b lsls r3, r3, #2
80053b8: 441a add r2, r3
80053ba: 4b2c ldr r3, [pc, #176] ; (800546c <USB_ActivateEndpoint+0x56c>)
80053bc: 4323 orrs r3, r4
80053be: b29b uxth r3, r3
80053c0: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80053c2: 687a ldr r2, [r7, #4]
80053c4: 683b ldr r3, [r7, #0]
80053c6: 781b ldrb r3, [r3, #0]
80053c8: 009b lsls r3, r3, #2
80053ca: 4413 add r3, r2
80053cc: 881b ldrh r3, [r3, #0]
80053ce: b29c uxth r4, r3
80053d0: 4623 mov r3, r4
80053d2: f003 0340 and.w r3, r3, #64 ; 0x40
80053d6: 2b00 cmp r3, #0
80053d8: d014 beq.n 8005404 <USB_ActivateEndpoint+0x504>
80053da: 687a ldr r2, [r7, #4]
80053dc: 683b ldr r3, [r7, #0]
80053de: 781b ldrb r3, [r3, #0]
80053e0: 009b lsls r3, r3, #2
80053e2: 4413 add r3, r2
80053e4: 881b ldrh r3, [r3, #0]
80053e6: b29b uxth r3, r3
80053e8: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80053ec: f023 0370 bic.w r3, r3, #112 ; 0x70
80053f0: b29c uxth r4, r3
80053f2: 687a ldr r2, [r7, #4]
80053f4: 683b ldr r3, [r7, #0]
80053f6: 781b ldrb r3, [r3, #0]
80053f8: 009b lsls r3, r3, #2
80053fa: 441a add r2, r3
80053fc: 4b1c ldr r3, [pc, #112] ; (8005470 <USB_ActivateEndpoint+0x570>)
80053fe: 4323 orrs r3, r4
8005400: b29b uxth r3, r3
8005402: 8013 strh r3, [r2, #0]
PCD_RX_DTOG(USBx, ep->num);
8005404: 687a ldr r2, [r7, #4]
8005406: 683b ldr r3, [r7, #0]
8005408: 781b ldrb r3, [r3, #0]
800540a: 009b lsls r3, r3, #2
800540c: 4413 add r3, r2
800540e: 881b ldrh r3, [r3, #0]
8005410: b29b uxth r3, r3
8005412: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005416: f023 0370 bic.w r3, r3, #112 ; 0x70
800541a: b29c uxth r4, r3
800541c: 687a ldr r2, [r7, #4]
800541e: 683b ldr r3, [r7, #0]
8005420: 781b ldrb r3, [r3, #0]
8005422: 009b lsls r3, r3, #2
8005424: 441a add r2, r3
8005426: 4b11 ldr r3, [pc, #68] ; (800546c <USB_ActivateEndpoint+0x56c>)
8005428: 4323 orrs r3, r4
800542a: b29b uxth r3, r3
800542c: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
800542e: 683b ldr r3, [r7, #0]
8005430: 78db ldrb r3, [r3, #3]
8005432: 2b01 cmp r3, #1
8005434: d020 beq.n 8005478 <USB_ActivateEndpoint+0x578>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8005436: 687a ldr r2, [r7, #4]
8005438: 683b ldr r3, [r7, #0]
800543a: 781b ldrb r3, [r3, #0]
800543c: 009b lsls r3, r3, #2
800543e: 4413 add r3, r2
8005440: 881b ldrh r3, [r3, #0]
8005442: b29b uxth r3, r3
8005444: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005448: f023 0340 bic.w r3, r3, #64 ; 0x40
800544c: b29c uxth r4, r3
800544e: f084 0320 eor.w r3, r4, #32
8005452: b29c uxth r4, r3
8005454: 687a ldr r2, [r7, #4]
8005456: 683b ldr r3, [r7, #0]
8005458: 781b ldrb r3, [r3, #0]
800545a: 009b lsls r3, r3, #2
800545c: 441a add r2, r3
800545e: 4b05 ldr r3, [pc, #20] ; (8005474 <USB_ActivateEndpoint+0x574>)
8005460: 4323 orrs r3, r4
8005462: b29b uxth r3, r3
8005464: 8013 strh r3, [r2, #0]
8005466: e01c b.n 80054a2 <USB_ActivateEndpoint+0x5a2>
8005468: ffff8180 .word 0xffff8180
800546c: ffffc080 .word 0xffffc080
8005470: ffff80c0 .word 0xffff80c0
8005474: ffff8080 .word 0xffff8080
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8005478: 687a ldr r2, [r7, #4]
800547a: 683b ldr r3, [r7, #0]
800547c: 781b ldrb r3, [r3, #0]
800547e: 009b lsls r3, r3, #2
8005480: 4413 add r3, r2
8005482: 881b ldrh r3, [r3, #0]
8005484: b29b uxth r3, r3
8005486: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
800548a: f023 0340 bic.w r3, r3, #64 ; 0x40
800548e: b29c uxth r4, r3
8005490: 687a ldr r2, [r7, #4]
8005492: 683b ldr r3, [r7, #0]
8005494: 781b ldrb r3, [r3, #0]
8005496: 009b lsls r3, r3, #2
8005498: 441a add r2, r3
800549a: 4b0f ldr r3, [pc, #60] ; (80054d8 <USB_ActivateEndpoint+0x5d8>)
800549c: 4323 orrs r3, r4
800549e: b29b uxth r3, r3
80054a0: 8013 strh r3, [r2, #0]
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80054a2: 687a ldr r2, [r7, #4]
80054a4: 683b ldr r3, [r7, #0]
80054a6: 781b ldrb r3, [r3, #0]
80054a8: 009b lsls r3, r3, #2
80054aa: 4413 add r3, r2
80054ac: 881b ldrh r3, [r3, #0]
80054ae: b29b uxth r3, r3
80054b0: f423 4380 bic.w r3, r3, #16384 ; 0x4000
80054b4: f023 0370 bic.w r3, r3, #112 ; 0x70
80054b8: b29c uxth r4, r3
80054ba: 687a ldr r2, [r7, #4]
80054bc: 683b ldr r3, [r7, #0]
80054be: 781b ldrb r3, [r3, #0]
80054c0: 009b lsls r3, r3, #2
80054c2: 441a add r2, r3
80054c4: 4b04 ldr r3, [pc, #16] ; (80054d8 <USB_ActivateEndpoint+0x5d8>)
80054c6: 4323 orrs r3, r4
80054c8: b29b uxth r3, r3
80054ca: 8013 strh r3, [r2, #0]
}
}
return ret;
80054cc: 7bfb ldrb r3, [r7, #15]
}
80054ce: 4618 mov r0, r3
80054d0: 3710 adds r7, #16
80054d2: 46bd mov sp, r7
80054d4: bc90 pop {r4, r7}
80054d6: 4770 bx lr
80054d8: ffff8080 .word 0xffff8080
080054dc <USB_DeactivateEndpoint>:
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
80054dc: b490 push {r4, r7}
80054de: b082 sub sp, #8
80054e0: af00 add r7, sp, #0
80054e2: 6078 str r0, [r7, #4]
80054e4: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
80054e6: 683b ldr r3, [r7, #0]
80054e8: 7b1b ldrb r3, [r3, #12]
80054ea: 2b00 cmp r3, #0
80054ec: d171 bne.n 80055d2 <USB_DeactivateEndpoint+0xf6>
{
if (ep->is_in != 0U)
80054ee: 683b ldr r3, [r7, #0]
80054f0: 785b ldrb r3, [r3, #1]
80054f2: 2b00 cmp r3, #0
80054f4: d036 beq.n 8005564 <USB_DeactivateEndpoint+0x88>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
80054f6: 687a ldr r2, [r7, #4]
80054f8: 683b ldr r3, [r7, #0]
80054fa: 781b ldrb r3, [r3, #0]
80054fc: 009b lsls r3, r3, #2
80054fe: 4413 add r3, r2
8005500: 881b ldrh r3, [r3, #0]
8005502: b29c uxth r4, r3
8005504: 4623 mov r3, r4
8005506: f003 0340 and.w r3, r3, #64 ; 0x40
800550a: 2b00 cmp r3, #0
800550c: d014 beq.n 8005538 <USB_DeactivateEndpoint+0x5c>
800550e: 687a ldr r2, [r7, #4]
8005510: 683b ldr r3, [r7, #0]
8005512: 781b ldrb r3, [r3, #0]
8005514: 009b lsls r3, r3, #2
8005516: 4413 add r3, r2
8005518: 881b ldrh r3, [r3, #0]
800551a: b29b uxth r3, r3
800551c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005520: f023 0370 bic.w r3, r3, #112 ; 0x70
8005524: b29c uxth r4, r3
8005526: 687a ldr r2, [r7, #4]
8005528: 683b ldr r3, [r7, #0]
800552a: 781b ldrb r3, [r3, #0]
800552c: 009b lsls r3, r3, #2
800552e: 441a add r2, r3
8005530: 4b6b ldr r3, [pc, #428] ; (80056e0 <USB_DeactivateEndpoint+0x204>)
8005532: 4323 orrs r3, r4
8005534: b29b uxth r3, r3
8005536: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
8005538: 687a ldr r2, [r7, #4]
800553a: 683b ldr r3, [r7, #0]
800553c: 781b ldrb r3, [r3, #0]
800553e: 009b lsls r3, r3, #2
8005540: 4413 add r3, r2
8005542: 881b ldrh r3, [r3, #0]
8005544: b29b uxth r3, r3
8005546: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
800554a: f023 0340 bic.w r3, r3, #64 ; 0x40
800554e: b29c uxth r4, r3
8005550: 687a ldr r2, [r7, #4]
8005552: 683b ldr r3, [r7, #0]
8005554: 781b ldrb r3, [r3, #0]
8005556: 009b lsls r3, r3, #2
8005558: 441a add r2, r3
800555a: 4b62 ldr r3, [pc, #392] ; (80056e4 <USB_DeactivateEndpoint+0x208>)
800555c: 4323 orrs r3, r4
800555e: b29b uxth r3, r3
8005560: 8013 strh r3, [r2, #0]
8005562: e144 b.n 80057ee <USB_DeactivateEndpoint+0x312>
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8005564: 687a ldr r2, [r7, #4]
8005566: 683b ldr r3, [r7, #0]
8005568: 781b ldrb r3, [r3, #0]
800556a: 009b lsls r3, r3, #2
800556c: 4413 add r3, r2
800556e: 881b ldrh r3, [r3, #0]
8005570: b29c uxth r4, r3
8005572: 4623 mov r3, r4
8005574: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005578: 2b00 cmp r3, #0
800557a: d014 beq.n 80055a6 <USB_DeactivateEndpoint+0xca>
800557c: 687a ldr r2, [r7, #4]
800557e: 683b ldr r3, [r7, #0]
8005580: 781b ldrb r3, [r3, #0]
8005582: 009b lsls r3, r3, #2
8005584: 4413 add r3, r2
8005586: 881b ldrh r3, [r3, #0]
8005588: b29b uxth r3, r3
800558a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
800558e: f023 0370 bic.w r3, r3, #112 ; 0x70
8005592: b29c uxth r4, r3
8005594: 687a ldr r2, [r7, #4]
8005596: 683b ldr r3, [r7, #0]
8005598: 781b ldrb r3, [r3, #0]
800559a: 009b lsls r3, r3, #2
800559c: 441a add r2, r3
800559e: 4b52 ldr r3, [pc, #328] ; (80056e8 <USB_DeactivateEndpoint+0x20c>)
80055a0: 4323 orrs r3, r4
80055a2: b29b uxth r3, r3
80055a4: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80055a6: 687a ldr r2, [r7, #4]
80055a8: 683b ldr r3, [r7, #0]
80055aa: 781b ldrb r3, [r3, #0]
80055ac: 009b lsls r3, r3, #2
80055ae: 4413 add r3, r2
80055b0: 881b ldrh r3, [r3, #0]
80055b2: b29b uxth r3, r3
80055b4: f423 4380 bic.w r3, r3, #16384 ; 0x4000
80055b8: f023 0370 bic.w r3, r3, #112 ; 0x70
80055bc: b29c uxth r4, r3
80055be: 687a ldr r2, [r7, #4]
80055c0: 683b ldr r3, [r7, #0]
80055c2: 781b ldrb r3, [r3, #0]
80055c4: 009b lsls r3, r3, #2
80055c6: 441a add r2, r3
80055c8: 4b46 ldr r3, [pc, #280] ; (80056e4 <USB_DeactivateEndpoint+0x208>)
80055ca: 4323 orrs r3, r4
80055cc: b29b uxth r3, r3
80055ce: 8013 strh r3, [r2, #0]
80055d0: e10d b.n 80057ee <USB_DeactivateEndpoint+0x312>
}
}
/*Double Buffer*/
else
{
if (ep->is_in == 0U)
80055d2: 683b ldr r3, [r7, #0]
80055d4: 785b ldrb r3, [r3, #1]
80055d6: 2b00 cmp r3, #0
80055d8: f040 8088 bne.w 80056ec <USB_DeactivateEndpoint+0x210>
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80055dc: 687a ldr r2, [r7, #4]
80055de: 683b ldr r3, [r7, #0]
80055e0: 781b ldrb r3, [r3, #0]
80055e2: 009b lsls r3, r3, #2
80055e4: 4413 add r3, r2
80055e6: 881b ldrh r3, [r3, #0]
80055e8: b29c uxth r4, r3
80055ea: 4623 mov r3, r4
80055ec: f403 4380 and.w r3, r3, #16384 ; 0x4000
80055f0: 2b00 cmp r3, #0
80055f2: d014 beq.n 800561e <USB_DeactivateEndpoint+0x142>
80055f4: 687a ldr r2, [r7, #4]
80055f6: 683b ldr r3, [r7, #0]
80055f8: 781b ldrb r3, [r3, #0]
80055fa: 009b lsls r3, r3, #2
80055fc: 4413 add r3, r2
80055fe: 881b ldrh r3, [r3, #0]
8005600: b29b uxth r3, r3
8005602: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005606: f023 0370 bic.w r3, r3, #112 ; 0x70
800560a: b29c uxth r4, r3
800560c: 687a ldr r2, [r7, #4]
800560e: 683b ldr r3, [r7, #0]
8005610: 781b ldrb r3, [r3, #0]
8005612: 009b lsls r3, r3, #2
8005614: 441a add r2, r3
8005616: 4b34 ldr r3, [pc, #208] ; (80056e8 <USB_DeactivateEndpoint+0x20c>)
8005618: 4323 orrs r3, r4
800561a: b29b uxth r3, r3
800561c: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800561e: 687a ldr r2, [r7, #4]
8005620: 683b ldr r3, [r7, #0]
8005622: 781b ldrb r3, [r3, #0]
8005624: 009b lsls r3, r3, #2
8005626: 4413 add r3, r2
8005628: 881b ldrh r3, [r3, #0]
800562a: b29c uxth r4, r3
800562c: 4623 mov r3, r4
800562e: f003 0340 and.w r3, r3, #64 ; 0x40
8005632: 2b00 cmp r3, #0
8005634: d014 beq.n 8005660 <USB_DeactivateEndpoint+0x184>
8005636: 687a ldr r2, [r7, #4]
8005638: 683b ldr r3, [r7, #0]
800563a: 781b ldrb r3, [r3, #0]
800563c: 009b lsls r3, r3, #2
800563e: 4413 add r3, r2
8005640: 881b ldrh r3, [r3, #0]
8005642: b29b uxth r3, r3
8005644: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005648: f023 0370 bic.w r3, r3, #112 ; 0x70
800564c: b29c uxth r4, r3
800564e: 687a ldr r2, [r7, #4]
8005650: 683b ldr r3, [r7, #0]
8005652: 781b ldrb r3, [r3, #0]
8005654: 009b lsls r3, r3, #2
8005656: 441a add r2, r3
8005658: 4b21 ldr r3, [pc, #132] ; (80056e0 <USB_DeactivateEndpoint+0x204>)
800565a: 4323 orrs r3, r4
800565c: b29b uxth r3, r3
800565e: 8013 strh r3, [r2, #0]
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(USBx, ep->num);
8005660: 687a ldr r2, [r7, #4]
8005662: 683b ldr r3, [r7, #0]
8005664: 781b ldrb r3, [r3, #0]
8005666: 009b lsls r3, r3, #2
8005668: 4413 add r3, r2
800566a: 881b ldrh r3, [r3, #0]
800566c: b29b uxth r3, r3
800566e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005672: f023 0370 bic.w r3, r3, #112 ; 0x70
8005676: b29c uxth r4, r3
8005678: 687a ldr r2, [r7, #4]
800567a: 683b ldr r3, [r7, #0]
800567c: 781b ldrb r3, [r3, #0]
800567e: 009b lsls r3, r3, #2
8005680: 441a add r2, r3
8005682: 4b17 ldr r3, [pc, #92] ; (80056e0 <USB_DeactivateEndpoint+0x204>)
8005684: 4323 orrs r3, r4
8005686: b29b uxth r3, r3
8005688: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
800568a: 687a ldr r2, [r7, #4]
800568c: 683b ldr r3, [r7, #0]
800568e: 781b ldrb r3, [r3, #0]
8005690: 009b lsls r3, r3, #2
8005692: 4413 add r3, r2
8005694: 881b ldrh r3, [r3, #0]
8005696: b29b uxth r3, r3
8005698: f423 4380 bic.w r3, r3, #16384 ; 0x4000
800569c: f023 0370 bic.w r3, r3, #112 ; 0x70
80056a0: b29c uxth r4, r3
80056a2: 687a ldr r2, [r7, #4]
80056a4: 683b ldr r3, [r7, #0]
80056a6: 781b ldrb r3, [r3, #0]
80056a8: 009b lsls r3, r3, #2
80056aa: 441a add r2, r3
80056ac: 4b0d ldr r3, [pc, #52] ; (80056e4 <USB_DeactivateEndpoint+0x208>)
80056ae: 4323 orrs r3, r4
80056b0: b29b uxth r3, r3
80056b2: 8013 strh r3, [r2, #0]
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
80056b4: 687a ldr r2, [r7, #4]
80056b6: 683b ldr r3, [r7, #0]
80056b8: 781b ldrb r3, [r3, #0]
80056ba: 009b lsls r3, r3, #2
80056bc: 4413 add r3, r2
80056be: 881b ldrh r3, [r3, #0]
80056c0: b29b uxth r3, r3
80056c2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80056c6: f023 0340 bic.w r3, r3, #64 ; 0x40
80056ca: b29c uxth r4, r3
80056cc: 687a ldr r2, [r7, #4]
80056ce: 683b ldr r3, [r7, #0]
80056d0: 781b ldrb r3, [r3, #0]
80056d2: 009b lsls r3, r3, #2
80056d4: 441a add r2, r3
80056d6: 4b03 ldr r3, [pc, #12] ; (80056e4 <USB_DeactivateEndpoint+0x208>)
80056d8: 4323 orrs r3, r4
80056da: b29b uxth r3, r3
80056dc: 8013 strh r3, [r2, #0]
80056de: e086 b.n 80057ee <USB_DeactivateEndpoint+0x312>
80056e0: ffff80c0 .word 0xffff80c0
80056e4: ffff8080 .word 0xffff8080
80056e8: ffffc080 .word 0xffffc080
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
80056ec: 687a ldr r2, [r7, #4]
80056ee: 683b ldr r3, [r7, #0]
80056f0: 781b ldrb r3, [r3, #0]
80056f2: 009b lsls r3, r3, #2
80056f4: 4413 add r3, r2
80056f6: 881b ldrh r3, [r3, #0]
80056f8: b29c uxth r4, r3
80056fa: 4623 mov r3, r4
80056fc: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005700: 2b00 cmp r3, #0
8005702: d014 beq.n 800572e <USB_DeactivateEndpoint+0x252>
8005704: 687a ldr r2, [r7, #4]
8005706: 683b ldr r3, [r7, #0]
8005708: 781b ldrb r3, [r3, #0]
800570a: 009b lsls r3, r3, #2
800570c: 4413 add r3, r2
800570e: 881b ldrh r3, [r3, #0]
8005710: b29b uxth r3, r3
8005712: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005716: f023 0370 bic.w r3, r3, #112 ; 0x70
800571a: b29c uxth r4, r3
800571c: 687a ldr r2, [r7, #4]
800571e: 683b ldr r3, [r7, #0]
8005720: 781b ldrb r3, [r3, #0]
8005722: 009b lsls r3, r3, #2
8005724: 441a add r2, r3
8005726: 4b35 ldr r3, [pc, #212] ; (80057fc <USB_DeactivateEndpoint+0x320>)
8005728: 4323 orrs r3, r4
800572a: b29b uxth r3, r3
800572c: 8013 strh r3, [r2, #0]
PCD_CLEAR_TX_DTOG(USBx, ep->num);
800572e: 687a ldr r2, [r7, #4]
8005730: 683b ldr r3, [r7, #0]
8005732: 781b ldrb r3, [r3, #0]
8005734: 009b lsls r3, r3, #2
8005736: 4413 add r3, r2
8005738: 881b ldrh r3, [r3, #0]
800573a: b29c uxth r4, r3
800573c: 4623 mov r3, r4
800573e: f003 0340 and.w r3, r3, #64 ; 0x40
8005742: 2b00 cmp r3, #0
8005744: d014 beq.n 8005770 <USB_DeactivateEndpoint+0x294>
8005746: 687a ldr r2, [r7, #4]
8005748: 683b ldr r3, [r7, #0]
800574a: 781b ldrb r3, [r3, #0]
800574c: 009b lsls r3, r3, #2
800574e: 4413 add r3, r2
8005750: 881b ldrh r3, [r3, #0]
8005752: b29b uxth r3, r3
8005754: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005758: f023 0370 bic.w r3, r3, #112 ; 0x70
800575c: b29c uxth r4, r3
800575e: 687a ldr r2, [r7, #4]
8005760: 683b ldr r3, [r7, #0]
8005762: 781b ldrb r3, [r3, #0]
8005764: 009b lsls r3, r3, #2
8005766: 441a add r2, r3
8005768: 4b25 ldr r3, [pc, #148] ; (8005800 <USB_DeactivateEndpoint+0x324>)
800576a: 4323 orrs r3, r4
800576c: b29b uxth r3, r3
800576e: 8013 strh r3, [r2, #0]
PCD_RX_DTOG(USBx, ep->num);
8005770: 687a ldr r2, [r7, #4]
8005772: 683b ldr r3, [r7, #0]
8005774: 781b ldrb r3, [r3, #0]
8005776: 009b lsls r3, r3, #2
8005778: 4413 add r3, r2
800577a: 881b ldrh r3, [r3, #0]
800577c: b29b uxth r3, r3
800577e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005782: f023 0370 bic.w r3, r3, #112 ; 0x70
8005786: b29c uxth r4, r3
8005788: 687a ldr r2, [r7, #4]
800578a: 683b ldr r3, [r7, #0]
800578c: 781b ldrb r3, [r3, #0]
800578e: 009b lsls r3, r3, #2
8005790: 441a add r2, r3
8005792: 4b1a ldr r3, [pc, #104] ; (80057fc <USB_DeactivateEndpoint+0x320>)
8005794: 4323 orrs r3, r4
8005796: b29b uxth r3, r3
8005798: 8013 strh r3, [r2, #0]
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
800579a: 687a ldr r2, [r7, #4]
800579c: 683b ldr r3, [r7, #0]
800579e: 781b ldrb r3, [r3, #0]
80057a0: 009b lsls r3, r3, #2
80057a2: 4413 add r3, r2
80057a4: 881b ldrh r3, [r3, #0]
80057a6: b29b uxth r3, r3
80057a8: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
80057ac: f023 0340 bic.w r3, r3, #64 ; 0x40
80057b0: b29c uxth r4, r3
80057b2: 687a ldr r2, [r7, #4]
80057b4: 683b ldr r3, [r7, #0]
80057b6: 781b ldrb r3, [r3, #0]
80057b8: 009b lsls r3, r3, #2
80057ba: 441a add r2, r3
80057bc: 4b11 ldr r3, [pc, #68] ; (8005804 <USB_DeactivateEndpoint+0x328>)
80057be: 4323 orrs r3, r4
80057c0: b29b uxth r3, r3
80057c2: 8013 strh r3, [r2, #0]
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
80057c4: 687a ldr r2, [r7, #4]
80057c6: 683b ldr r3, [r7, #0]
80057c8: 781b ldrb r3, [r3, #0]
80057ca: 009b lsls r3, r3, #2
80057cc: 4413 add r3, r2
80057ce: 881b ldrh r3, [r3, #0]
80057d0: b29b uxth r3, r3
80057d2: f423 4380 bic.w r3, r3, #16384 ; 0x4000
80057d6: f023 0370 bic.w r3, r3, #112 ; 0x70
80057da: b29c uxth r4, r3
80057dc: 687a ldr r2, [r7, #4]
80057de: 683b ldr r3, [r7, #0]
80057e0: 781b ldrb r3, [r3, #0]
80057e2: 009b lsls r3, r3, #2
80057e4: 441a add r2, r3
80057e6: 4b07 ldr r3, [pc, #28] ; (8005804 <USB_DeactivateEndpoint+0x328>)
80057e8: 4323 orrs r3, r4
80057ea: b29b uxth r3, r3
80057ec: 8013 strh r3, [r2, #0]
}
}
return HAL_OK;
80057ee: 2300 movs r3, #0
}
80057f0: 4618 mov r0, r3
80057f2: 3708 adds r7, #8
80057f4: 46bd mov sp, r7
80057f6: bc90 pop {r4, r7}
80057f8: 4770 bx lr
80057fa: bf00 nop
80057fc: ffffc080 .word 0xffffc080
8005800: ffff80c0 .word 0xffff80c0
8005804: ffff8080 .word 0xffff8080
08005808 <USB_EPStartXfer>:
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8005808: b590 push {r4, r7, lr}
800580a: b08d sub sp, #52 ; 0x34
800580c: af00 add r7, sp, #0
800580e: 6078 str r0, [r7, #4]
8005810: 6039 str r1, [r7, #0]
uint16_t pmabuffer;
uint32_t len;
/* IN endpoint */
if (ep->is_in == 1U)
8005812: 683b ldr r3, [r7, #0]
8005814: 785b ldrb r3, [r3, #1]
8005816: 2b01 cmp r3, #1
8005818: f040 8160 bne.w 8005adc <USB_EPStartXfer+0x2d4>
{
/*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
800581c: 683b ldr r3, [r7, #0]
800581e: 699a ldr r2, [r3, #24]
8005820: 683b ldr r3, [r7, #0]
8005822: 691b ldr r3, [r3, #16]
8005824: 429a cmp r2, r3
8005826: d909 bls.n 800583c <USB_EPStartXfer+0x34>
{
len = ep->maxpacket;
8005828: 683b ldr r3, [r7, #0]
800582a: 691b ldr r3, [r3, #16]
800582c: 62bb str r3, [r7, #40] ; 0x28
ep->xfer_len -= len;
800582e: 683b ldr r3, [r7, #0]
8005830: 699a ldr r2, [r3, #24]
8005832: 6abb ldr r3, [r7, #40] ; 0x28
8005834: 1ad2 subs r2, r2, r3
8005836: 683b ldr r3, [r7, #0]
8005838: 619a str r2, [r3, #24]
800583a: e005 b.n 8005848 <USB_EPStartXfer+0x40>
}
else
{
len = ep->xfer_len;
800583c: 683b ldr r3, [r7, #0]
800583e: 699b ldr r3, [r3, #24]
8005840: 62bb str r3, [r7, #40] ; 0x28
ep->xfer_len = 0U;
8005842: 683b ldr r3, [r7, #0]
8005844: 2200 movs r2, #0
8005846: 619a str r2, [r3, #24]
}
/* configure and validate Tx endpoint */
if (ep->doublebuffer == 0U)
8005848: 683b ldr r3, [r7, #0]
800584a: 7b1b ldrb r3, [r3, #12]
800584c: 2b00 cmp r3, #0
800584e: d119 bne.n 8005884 <USB_EPStartXfer+0x7c>
{
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
8005850: 683b ldr r3, [r7, #0]
8005852: 6959 ldr r1, [r3, #20]
8005854: 683b ldr r3, [r7, #0]
8005856: 88da ldrh r2, [r3, #6]
8005858: 6abb ldr r3, [r7, #40] ; 0x28
800585a: b29b uxth r3, r3
800585c: 6878 ldr r0, [r7, #4]
800585e: f000 fba2 bl 8005fa6 <USB_WritePMA>
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
8005862: 687c ldr r4, [r7, #4]
8005864: 687b ldr r3, [r7, #4]
8005866: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
800586a: b29b uxth r3, r3
800586c: 441c add r4, r3
800586e: 683b ldr r3, [r7, #0]
8005870: 781b ldrb r3, [r3, #0]
8005872: 011b lsls r3, r3, #4
8005874: 4423 add r3, r4
8005876: f203 4304 addw r3, r3, #1028 ; 0x404
800587a: 461c mov r4, r3
800587c: 6abb ldr r3, [r7, #40] ; 0x28
800587e: b29b uxth r3, r3
8005880: 8023 strh r3, [r4, #0]
8005882: e10f b.n 8005aa4 <USB_EPStartXfer+0x29c>
}
else
{
/* Write the data to the USB endpoint */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
8005884: 687a ldr r2, [r7, #4]
8005886: 683b ldr r3, [r7, #0]
8005888: 781b ldrb r3, [r3, #0]
800588a: 009b lsls r3, r3, #2
800588c: 4413 add r3, r2
800588e: 881b ldrh r3, [r3, #0]
8005890: b29b uxth r3, r3
8005892: f003 0340 and.w r3, r3, #64 ; 0x40
8005896: 2b00 cmp r3, #0
8005898: d065 beq.n 8005966 <USB_EPStartXfer+0x15e>
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
800589a: 687c ldr r4, [r7, #4]
800589c: 683b ldr r3, [r7, #0]
800589e: 785b ldrb r3, [r3, #1]
80058a0: 2b00 cmp r3, #0
80058a2: d148 bne.n 8005936 <USB_EPStartXfer+0x12e>
80058a4: 687c ldr r4, [r7, #4]
80058a6: 687b ldr r3, [r7, #4]
80058a8: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
80058ac: b29b uxth r3, r3
80058ae: 441c add r4, r3
80058b0: 683b ldr r3, [r7, #0]
80058b2: 781b ldrb r3, [r3, #0]
80058b4: 011b lsls r3, r3, #4
80058b6: 4423 add r3, r4
80058b8: f203 430c addw r3, r3, #1036 ; 0x40c
80058bc: 461c mov r4, r3
80058be: 6abb ldr r3, [r7, #40] ; 0x28
80058c0: 2b00 cmp r3, #0
80058c2: d10e bne.n 80058e2 <USB_EPStartXfer+0xda>
80058c4: 8823 ldrh r3, [r4, #0]
80058c6: b29b uxth r3, r3
80058c8: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
80058cc: b29b uxth r3, r3
80058ce: 8023 strh r3, [r4, #0]
80058d0: 8823 ldrh r3, [r4, #0]
80058d2: b29b uxth r3, r3
80058d4: ea6f 4343 mvn.w r3, r3, lsl #17
80058d8: ea6f 4353 mvn.w r3, r3, lsr #17
80058dc: b29b uxth r3, r3
80058de: 8023 strh r3, [r4, #0]
80058e0: e03d b.n 800595e <USB_EPStartXfer+0x156>
80058e2: 6abb ldr r3, [r7, #40] ; 0x28
80058e4: 2b3e cmp r3, #62 ; 0x3e
80058e6: d810 bhi.n 800590a <USB_EPStartXfer+0x102>
80058e8: 6abb ldr r3, [r7, #40] ; 0x28
80058ea: 085b lsrs r3, r3, #1
80058ec: 627b str r3, [r7, #36] ; 0x24
80058ee: 6abb ldr r3, [r7, #40] ; 0x28
80058f0: f003 0301 and.w r3, r3, #1
80058f4: 2b00 cmp r3, #0
80058f6: d002 beq.n 80058fe <USB_EPStartXfer+0xf6>
80058f8: 6a7b ldr r3, [r7, #36] ; 0x24
80058fa: 3301 adds r3, #1
80058fc: 627b str r3, [r7, #36] ; 0x24
80058fe: 6a7b ldr r3, [r7, #36] ; 0x24
8005900: b29b uxth r3, r3
8005902: 029b lsls r3, r3, #10
8005904: b29b uxth r3, r3
8005906: 8023 strh r3, [r4, #0]
8005908: e029 b.n 800595e <USB_EPStartXfer+0x156>
800590a: 6abb ldr r3, [r7, #40] ; 0x28
800590c: 095b lsrs r3, r3, #5
800590e: 627b str r3, [r7, #36] ; 0x24
8005910: 6abb ldr r3, [r7, #40] ; 0x28
8005912: f003 031f and.w r3, r3, #31
8005916: 2b00 cmp r3, #0
8005918: d102 bne.n 8005920 <USB_EPStartXfer+0x118>
800591a: 6a7b ldr r3, [r7, #36] ; 0x24
800591c: 3b01 subs r3, #1
800591e: 627b str r3, [r7, #36] ; 0x24
8005920: 6a7b ldr r3, [r7, #36] ; 0x24
8005922: b29b uxth r3, r3
8005924: 029b lsls r3, r3, #10
8005926: b29b uxth r3, r3
8005928: ea6f 4343 mvn.w r3, r3, lsl #17
800592c: ea6f 4353 mvn.w r3, r3, lsr #17
8005930: b29b uxth r3, r3
8005932: 8023 strh r3, [r4, #0]
8005934: e013 b.n 800595e <USB_EPStartXfer+0x156>
8005936: 683b ldr r3, [r7, #0]
8005938: 785b ldrb r3, [r3, #1]
800593a: 2b01 cmp r3, #1
800593c: d10f bne.n 800595e <USB_EPStartXfer+0x156>
800593e: 687b ldr r3, [r7, #4]
8005940: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005944: b29b uxth r3, r3
8005946: 441c add r4, r3
8005948: 683b ldr r3, [r7, #0]
800594a: 781b ldrb r3, [r3, #0]
800594c: 011b lsls r3, r3, #4
800594e: 4423 add r3, r4
8005950: f203 430c addw r3, r3, #1036 ; 0x40c
8005954: 60fb str r3, [r7, #12]
8005956: 6abb ldr r3, [r7, #40] ; 0x28
8005958: b29a uxth r2, r3
800595a: 68fb ldr r3, [r7, #12]
800595c: 801a strh r2, [r3, #0]
pmabuffer = ep->pmaaddr1;
800595e: 683b ldr r3, [r7, #0]
8005960: 895b ldrh r3, [r3, #10]
8005962: 85fb strh r3, [r7, #46] ; 0x2e
8005964: e063 b.n 8005a2e <USB_EPStartXfer+0x226>
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
8005966: 683b ldr r3, [r7, #0]
8005968: 785b ldrb r3, [r3, #1]
800596a: 2b00 cmp r3, #0
800596c: d148 bne.n 8005a00 <USB_EPStartXfer+0x1f8>
800596e: 687c ldr r4, [r7, #4]
8005970: 687b ldr r3, [r7, #4]
8005972: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005976: b29b uxth r3, r3
8005978: 441c add r4, r3
800597a: 683b ldr r3, [r7, #0]
800597c: 781b ldrb r3, [r3, #0]
800597e: 011b lsls r3, r3, #4
8005980: 4423 add r3, r4
8005982: f203 4304 addw r3, r3, #1028 ; 0x404
8005986: 461c mov r4, r3
8005988: 6abb ldr r3, [r7, #40] ; 0x28
800598a: 2b00 cmp r3, #0
800598c: d10e bne.n 80059ac <USB_EPStartXfer+0x1a4>
800598e: 8823 ldrh r3, [r4, #0]
8005990: b29b uxth r3, r3
8005992: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
8005996: b29b uxth r3, r3
8005998: 8023 strh r3, [r4, #0]
800599a: 8823 ldrh r3, [r4, #0]
800599c: b29b uxth r3, r3
800599e: ea6f 4343 mvn.w r3, r3, lsl #17
80059a2: ea6f 4353 mvn.w r3, r3, lsr #17
80059a6: b29b uxth r3, r3
80059a8: 8023 strh r3, [r4, #0]
80059aa: e03d b.n 8005a28 <USB_EPStartXfer+0x220>
80059ac: 6abb ldr r3, [r7, #40] ; 0x28
80059ae: 2b3e cmp r3, #62 ; 0x3e
80059b0: d810 bhi.n 80059d4 <USB_EPStartXfer+0x1cc>
80059b2: 6abb ldr r3, [r7, #40] ; 0x28
80059b4: 085b lsrs r3, r3, #1
80059b6: 623b str r3, [r7, #32]
80059b8: 6abb ldr r3, [r7, #40] ; 0x28
80059ba: f003 0301 and.w r3, r3, #1
80059be: 2b00 cmp r3, #0
80059c0: d002 beq.n 80059c8 <USB_EPStartXfer+0x1c0>
80059c2: 6a3b ldr r3, [r7, #32]
80059c4: 3301 adds r3, #1
80059c6: 623b str r3, [r7, #32]
80059c8: 6a3b ldr r3, [r7, #32]
80059ca: b29b uxth r3, r3
80059cc: 029b lsls r3, r3, #10
80059ce: b29b uxth r3, r3
80059d0: 8023 strh r3, [r4, #0]
80059d2: e029 b.n 8005a28 <USB_EPStartXfer+0x220>
80059d4: 6abb ldr r3, [r7, #40] ; 0x28
80059d6: 095b lsrs r3, r3, #5
80059d8: 623b str r3, [r7, #32]
80059da: 6abb ldr r3, [r7, #40] ; 0x28
80059dc: f003 031f and.w r3, r3, #31
80059e0: 2b00 cmp r3, #0
80059e2: d102 bne.n 80059ea <USB_EPStartXfer+0x1e2>
80059e4: 6a3b ldr r3, [r7, #32]
80059e6: 3b01 subs r3, #1
80059e8: 623b str r3, [r7, #32]
80059ea: 6a3b ldr r3, [r7, #32]
80059ec: b29b uxth r3, r3
80059ee: 029b lsls r3, r3, #10
80059f0: b29b uxth r3, r3
80059f2: ea6f 4343 mvn.w r3, r3, lsl #17
80059f6: ea6f 4353 mvn.w r3, r3, lsr #17
80059fa: b29b uxth r3, r3
80059fc: 8023 strh r3, [r4, #0]
80059fe: e013 b.n 8005a28 <USB_EPStartXfer+0x220>
8005a00: 683b ldr r3, [r7, #0]
8005a02: 785b ldrb r3, [r3, #1]
8005a04: 2b01 cmp r3, #1
8005a06: d10f bne.n 8005a28 <USB_EPStartXfer+0x220>
8005a08: 687c ldr r4, [r7, #4]
8005a0a: 687b ldr r3, [r7, #4]
8005a0c: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005a10: b29b uxth r3, r3
8005a12: 441c add r4, r3
8005a14: 683b ldr r3, [r7, #0]
8005a16: 781b ldrb r3, [r3, #0]
8005a18: 011b lsls r3, r3, #4
8005a1a: 4423 add r3, r4
8005a1c: f203 4304 addw r3, r3, #1028 ; 0x404
8005a20: 461c mov r4, r3
8005a22: 6abb ldr r3, [r7, #40] ; 0x28
8005a24: b29b uxth r3, r3
8005a26: 8023 strh r3, [r4, #0]
pmabuffer = ep->pmaaddr0;
8005a28: 683b ldr r3, [r7, #0]
8005a2a: 891b ldrh r3, [r3, #8]
8005a2c: 85fb strh r3, [r7, #46] ; 0x2e
}
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
8005a2e: 683b ldr r3, [r7, #0]
8005a30: 6959 ldr r1, [r3, #20]
8005a32: 6abb ldr r3, [r7, #40] ; 0x28
8005a34: b29b uxth r3, r3
8005a36: 8dfa ldrh r2, [r7, #46] ; 0x2e
8005a38: 6878 ldr r0, [r7, #4]
8005a3a: f000 fab4 bl 8005fa6 <USB_WritePMA>
PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
8005a3e: 683b ldr r3, [r7, #0]
8005a40: 785b ldrb r3, [r3, #1]
8005a42: 2b00 cmp r3, #0
8005a44: d115 bne.n 8005a72 <USB_EPStartXfer+0x26a>
8005a46: 687a ldr r2, [r7, #4]
8005a48: 683b ldr r3, [r7, #0]
8005a4a: 781b ldrb r3, [r3, #0]
8005a4c: 009b lsls r3, r3, #2
8005a4e: 4413 add r3, r2
8005a50: 881b ldrh r3, [r3, #0]
8005a52: b29b uxth r3, r3
8005a54: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005a58: f023 0370 bic.w r3, r3, #112 ; 0x70
8005a5c: b29c uxth r4, r3
8005a5e: 687a ldr r2, [r7, #4]
8005a60: 683b ldr r3, [r7, #0]
8005a62: 781b ldrb r3, [r3, #0]
8005a64: 009b lsls r3, r3, #2
8005a66: 441a add r2, r3
8005a68: 4b9a ldr r3, [pc, #616] ; (8005cd4 <USB_EPStartXfer+0x4cc>)
8005a6a: 4323 orrs r3, r4
8005a6c: b29b uxth r3, r3
8005a6e: 8013 strh r3, [r2, #0]
8005a70: e018 b.n 8005aa4 <USB_EPStartXfer+0x29c>
8005a72: 683b ldr r3, [r7, #0]
8005a74: 785b ldrb r3, [r3, #1]
8005a76: 2b01 cmp r3, #1
8005a78: d114 bne.n 8005aa4 <USB_EPStartXfer+0x29c>
8005a7a: 687a ldr r2, [r7, #4]
8005a7c: 683b ldr r3, [r7, #0]
8005a7e: 781b ldrb r3, [r3, #0]
8005a80: 009b lsls r3, r3, #2
8005a82: 4413 add r3, r2
8005a84: 881b ldrh r3, [r3, #0]
8005a86: b29b uxth r3, r3
8005a88: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005a8c: f023 0370 bic.w r3, r3, #112 ; 0x70
8005a90: b29c uxth r4, r3
8005a92: 687a ldr r2, [r7, #4]
8005a94: 683b ldr r3, [r7, #0]
8005a96: 781b ldrb r3, [r3, #0]
8005a98: 009b lsls r3, r3, #2
8005a9a: 441a add r2, r3
8005a9c: 4b8e ldr r3, [pc, #568] ; (8005cd8 <USB_EPStartXfer+0x4d0>)
8005a9e: 4323 orrs r3, r4
8005aa0: b29b uxth r3, r3
8005aa2: 8013 strh r3, [r2, #0]
}
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
8005aa4: 687a ldr r2, [r7, #4]
8005aa6: 683b ldr r3, [r7, #0]
8005aa8: 781b ldrb r3, [r3, #0]
8005aaa: 009b lsls r3, r3, #2
8005aac: 4413 add r3, r2
8005aae: 881b ldrh r3, [r3, #0]
8005ab0: b29b uxth r3, r3
8005ab2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005ab6: f023 0340 bic.w r3, r3, #64 ; 0x40
8005aba: b29c uxth r4, r3
8005abc: f084 0310 eor.w r3, r4, #16
8005ac0: b29c uxth r4, r3
8005ac2: f084 0320 eor.w r3, r4, #32
8005ac6: b29c uxth r4, r3
8005ac8: 687a ldr r2, [r7, #4]
8005aca: 683b ldr r3, [r7, #0]
8005acc: 781b ldrb r3, [r3, #0]
8005ace: 009b lsls r3, r3, #2
8005ad0: 441a add r2, r3
8005ad2: 4b82 ldr r3, [pc, #520] ; (8005cdc <USB_EPStartXfer+0x4d4>)
8005ad4: 4323 orrs r3, r4
8005ad6: b29b uxth r3, r3
8005ad8: 8013 strh r3, [r2, #0]
8005ada: e146 b.n 8005d6a <USB_EPStartXfer+0x562>
}
else /* OUT endpoint */
{
/* Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
8005adc: 683b ldr r3, [r7, #0]
8005ade: 699a ldr r2, [r3, #24]
8005ae0: 683b ldr r3, [r7, #0]
8005ae2: 691b ldr r3, [r3, #16]
8005ae4: 429a cmp r2, r3
8005ae6: d909 bls.n 8005afc <USB_EPStartXfer+0x2f4>
{
len = ep->maxpacket;
8005ae8: 683b ldr r3, [r7, #0]
8005aea: 691b ldr r3, [r3, #16]
8005aec: 62bb str r3, [r7, #40] ; 0x28
ep->xfer_len -= len;
8005aee: 683b ldr r3, [r7, #0]
8005af0: 699a ldr r2, [r3, #24]
8005af2: 6abb ldr r3, [r7, #40] ; 0x28
8005af4: 1ad2 subs r2, r2, r3
8005af6: 683b ldr r3, [r7, #0]
8005af8: 619a str r2, [r3, #24]
8005afa: e005 b.n 8005b08 <USB_EPStartXfer+0x300>
}
else
{
len = ep->xfer_len;
8005afc: 683b ldr r3, [r7, #0]
8005afe: 699b ldr r3, [r3, #24]
8005b00: 62bb str r3, [r7, #40] ; 0x28
ep->xfer_len = 0U;
8005b02: 683b ldr r3, [r7, #0]
8005b04: 2200 movs r2, #0
8005b06: 619a str r2, [r3, #24]
}
/* configure and validate Rx endpoint */
if (ep->doublebuffer == 0U)
8005b08: 683b ldr r3, [r7, #0]
8005b0a: 7b1b ldrb r3, [r3, #12]
8005b0c: 2b00 cmp r3, #0
8005b0e: d148 bne.n 8005ba2 <USB_EPStartXfer+0x39a>
{
/*Set RX buffer count*/
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
8005b10: 687c ldr r4, [r7, #4]
8005b12: 687b ldr r3, [r7, #4]
8005b14: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005b18: b29b uxth r3, r3
8005b1a: 441c add r4, r3
8005b1c: 683b ldr r3, [r7, #0]
8005b1e: 781b ldrb r3, [r3, #0]
8005b20: 011b lsls r3, r3, #4
8005b22: 4423 add r3, r4
8005b24: f203 430c addw r3, r3, #1036 ; 0x40c
8005b28: 461c mov r4, r3
8005b2a: 6abb ldr r3, [r7, #40] ; 0x28
8005b2c: 2b00 cmp r3, #0
8005b2e: d10e bne.n 8005b4e <USB_EPStartXfer+0x346>
8005b30: 8823 ldrh r3, [r4, #0]
8005b32: b29b uxth r3, r3
8005b34: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
8005b38: b29b uxth r3, r3
8005b3a: 8023 strh r3, [r4, #0]
8005b3c: 8823 ldrh r3, [r4, #0]
8005b3e: b29b uxth r3, r3
8005b40: ea6f 4343 mvn.w r3, r3, lsl #17
8005b44: ea6f 4353 mvn.w r3, r3, lsr #17
8005b48: b29b uxth r3, r3
8005b4a: 8023 strh r3, [r4, #0]
8005b4c: e0f2 b.n 8005d34 <USB_EPStartXfer+0x52c>
8005b4e: 6abb ldr r3, [r7, #40] ; 0x28
8005b50: 2b3e cmp r3, #62 ; 0x3e
8005b52: d810 bhi.n 8005b76 <USB_EPStartXfer+0x36e>
8005b54: 6abb ldr r3, [r7, #40] ; 0x28
8005b56: 085b lsrs r3, r3, #1
8005b58: 61fb str r3, [r7, #28]
8005b5a: 6abb ldr r3, [r7, #40] ; 0x28
8005b5c: f003 0301 and.w r3, r3, #1
8005b60: 2b00 cmp r3, #0
8005b62: d002 beq.n 8005b6a <USB_EPStartXfer+0x362>
8005b64: 69fb ldr r3, [r7, #28]
8005b66: 3301 adds r3, #1
8005b68: 61fb str r3, [r7, #28]
8005b6a: 69fb ldr r3, [r7, #28]
8005b6c: b29b uxth r3, r3
8005b6e: 029b lsls r3, r3, #10
8005b70: b29b uxth r3, r3
8005b72: 8023 strh r3, [r4, #0]
8005b74: e0de b.n 8005d34 <USB_EPStartXfer+0x52c>
8005b76: 6abb ldr r3, [r7, #40] ; 0x28
8005b78: 095b lsrs r3, r3, #5
8005b7a: 61fb str r3, [r7, #28]
8005b7c: 6abb ldr r3, [r7, #40] ; 0x28
8005b7e: f003 031f and.w r3, r3, #31
8005b82: 2b00 cmp r3, #0
8005b84: d102 bne.n 8005b8c <USB_EPStartXfer+0x384>
8005b86: 69fb ldr r3, [r7, #28]
8005b88: 3b01 subs r3, #1
8005b8a: 61fb str r3, [r7, #28]
8005b8c: 69fb ldr r3, [r7, #28]
8005b8e: b29b uxth r3, r3
8005b90: 029b lsls r3, r3, #10
8005b92: b29b uxth r3, r3
8005b94: ea6f 4343 mvn.w r3, r3, lsl #17
8005b98: ea6f 4353 mvn.w r3, r3, lsr #17
8005b9c: b29b uxth r3, r3
8005b9e: 8023 strh r3, [r4, #0]
8005ba0: e0c8 b.n 8005d34 <USB_EPStartXfer+0x52c>
}
else
{
/*Set the Double buffer counter*/
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
8005ba2: 683b ldr r3, [r7, #0]
8005ba4: 785b ldrb r3, [r3, #1]
8005ba6: 2b00 cmp r3, #0
8005ba8: d148 bne.n 8005c3c <USB_EPStartXfer+0x434>
8005baa: 687c ldr r4, [r7, #4]
8005bac: 687b ldr r3, [r7, #4]
8005bae: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005bb2: b29b uxth r3, r3
8005bb4: 441c add r4, r3
8005bb6: 683b ldr r3, [r7, #0]
8005bb8: 781b ldrb r3, [r3, #0]
8005bba: 011b lsls r3, r3, #4
8005bbc: 4423 add r3, r4
8005bbe: f203 4304 addw r3, r3, #1028 ; 0x404
8005bc2: 461c mov r4, r3
8005bc4: 6abb ldr r3, [r7, #40] ; 0x28
8005bc6: 2b00 cmp r3, #0
8005bc8: d10e bne.n 8005be8 <USB_EPStartXfer+0x3e0>
8005bca: 8823 ldrh r3, [r4, #0]
8005bcc: b29b uxth r3, r3
8005bce: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
8005bd2: b29b uxth r3, r3
8005bd4: 8023 strh r3, [r4, #0]
8005bd6: 8823 ldrh r3, [r4, #0]
8005bd8: b29b uxth r3, r3
8005bda: ea6f 4343 mvn.w r3, r3, lsl #17
8005bde: ea6f 4353 mvn.w r3, r3, lsr #17
8005be2: b29b uxth r3, r3
8005be4: 8023 strh r3, [r4, #0]
8005be6: e03d b.n 8005c64 <USB_EPStartXfer+0x45c>
8005be8: 6abb ldr r3, [r7, #40] ; 0x28
8005bea: 2b3e cmp r3, #62 ; 0x3e
8005bec: d810 bhi.n 8005c10 <USB_EPStartXfer+0x408>
8005bee: 6abb ldr r3, [r7, #40] ; 0x28
8005bf0: 085b lsrs r3, r3, #1
8005bf2: 61bb str r3, [r7, #24]
8005bf4: 6abb ldr r3, [r7, #40] ; 0x28
8005bf6: f003 0301 and.w r3, r3, #1
8005bfa: 2b00 cmp r3, #0
8005bfc: d002 beq.n 8005c04 <USB_EPStartXfer+0x3fc>
8005bfe: 69bb ldr r3, [r7, #24]
8005c00: 3301 adds r3, #1
8005c02: 61bb str r3, [r7, #24]
8005c04: 69bb ldr r3, [r7, #24]
8005c06: b29b uxth r3, r3
8005c08: 029b lsls r3, r3, #10
8005c0a: b29b uxth r3, r3
8005c0c: 8023 strh r3, [r4, #0]
8005c0e: e029 b.n 8005c64 <USB_EPStartXfer+0x45c>
8005c10: 6abb ldr r3, [r7, #40] ; 0x28
8005c12: 095b lsrs r3, r3, #5
8005c14: 61bb str r3, [r7, #24]
8005c16: 6abb ldr r3, [r7, #40] ; 0x28
8005c18: f003 031f and.w r3, r3, #31
8005c1c: 2b00 cmp r3, #0
8005c1e: d102 bne.n 8005c26 <USB_EPStartXfer+0x41e>
8005c20: 69bb ldr r3, [r7, #24]
8005c22: 3b01 subs r3, #1
8005c24: 61bb str r3, [r7, #24]
8005c26: 69bb ldr r3, [r7, #24]
8005c28: b29b uxth r3, r3
8005c2a: 029b lsls r3, r3, #10
8005c2c: b29b uxth r3, r3
8005c2e: ea6f 4343 mvn.w r3, r3, lsl #17
8005c32: ea6f 4353 mvn.w r3, r3, lsr #17
8005c36: b29b uxth r3, r3
8005c38: 8023 strh r3, [r4, #0]
8005c3a: e013 b.n 8005c64 <USB_EPStartXfer+0x45c>
8005c3c: 683b ldr r3, [r7, #0]
8005c3e: 785b ldrb r3, [r3, #1]
8005c40: 2b01 cmp r3, #1
8005c42: d10f bne.n 8005c64 <USB_EPStartXfer+0x45c>
8005c44: 687c ldr r4, [r7, #4]
8005c46: 687b ldr r3, [r7, #4]
8005c48: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005c4c: b29b uxth r3, r3
8005c4e: 441c add r4, r3
8005c50: 683b ldr r3, [r7, #0]
8005c52: 781b ldrb r3, [r3, #0]
8005c54: 011b lsls r3, r3, #4
8005c56: 4423 add r3, r4
8005c58: f203 4304 addw r3, r3, #1028 ; 0x404
8005c5c: 461c mov r4, r3
8005c5e: 6abb ldr r3, [r7, #40] ; 0x28
8005c60: b29b uxth r3, r3
8005c62: 8023 strh r3, [r4, #0]
8005c64: 687c ldr r4, [r7, #4]
8005c66: 683b ldr r3, [r7, #0]
8005c68: 785b ldrb r3, [r3, #1]
8005c6a: 2b00 cmp r3, #0
8005c6c: d14e bne.n 8005d0c <USB_EPStartXfer+0x504>
8005c6e: 687c ldr r4, [r7, #4]
8005c70: 687b ldr r3, [r7, #4]
8005c72: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005c76: b29b uxth r3, r3
8005c78: 441c add r4, r3
8005c7a: 683b ldr r3, [r7, #0]
8005c7c: 781b ldrb r3, [r3, #0]
8005c7e: 011b lsls r3, r3, #4
8005c80: 4423 add r3, r4
8005c82: f203 430c addw r3, r3, #1036 ; 0x40c
8005c86: 461c mov r4, r3
8005c88: 6abb ldr r3, [r7, #40] ; 0x28
8005c8a: 2b00 cmp r3, #0
8005c8c: d10e bne.n 8005cac <USB_EPStartXfer+0x4a4>
8005c8e: 8823 ldrh r3, [r4, #0]
8005c90: b29b uxth r3, r3
8005c92: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
8005c96: b29b uxth r3, r3
8005c98: 8023 strh r3, [r4, #0]
8005c9a: 8823 ldrh r3, [r4, #0]
8005c9c: b29b uxth r3, r3
8005c9e: ea6f 4343 mvn.w r3, r3, lsl #17
8005ca2: ea6f 4353 mvn.w r3, r3, lsr #17
8005ca6: b29b uxth r3, r3
8005ca8: 8023 strh r3, [r4, #0]
8005caa: e043 b.n 8005d34 <USB_EPStartXfer+0x52c>
8005cac: 6abb ldr r3, [r7, #40] ; 0x28
8005cae: 2b3e cmp r3, #62 ; 0x3e
8005cb0: d816 bhi.n 8005ce0 <USB_EPStartXfer+0x4d8>
8005cb2: 6abb ldr r3, [r7, #40] ; 0x28
8005cb4: 085b lsrs r3, r3, #1
8005cb6: 617b str r3, [r7, #20]
8005cb8: 6abb ldr r3, [r7, #40] ; 0x28
8005cba: f003 0301 and.w r3, r3, #1
8005cbe: 2b00 cmp r3, #0
8005cc0: d002 beq.n 8005cc8 <USB_EPStartXfer+0x4c0>
8005cc2: 697b ldr r3, [r7, #20]
8005cc4: 3301 adds r3, #1
8005cc6: 617b str r3, [r7, #20]
8005cc8: 697b ldr r3, [r7, #20]
8005cca: b29b uxth r3, r3
8005ccc: 029b lsls r3, r3, #10
8005cce: b29b uxth r3, r3
8005cd0: 8023 strh r3, [r4, #0]
8005cd2: e02f b.n 8005d34 <USB_EPStartXfer+0x52c>
8005cd4: ffff80c0 .word 0xffff80c0
8005cd8: ffffc080 .word 0xffffc080
8005cdc: ffff8080 .word 0xffff8080
8005ce0: 6abb ldr r3, [r7, #40] ; 0x28
8005ce2: 095b lsrs r3, r3, #5
8005ce4: 617b str r3, [r7, #20]
8005ce6: 6abb ldr r3, [r7, #40] ; 0x28
8005ce8: f003 031f and.w r3, r3, #31
8005cec: 2b00 cmp r3, #0
8005cee: d102 bne.n 8005cf6 <USB_EPStartXfer+0x4ee>
8005cf0: 697b ldr r3, [r7, #20]
8005cf2: 3b01 subs r3, #1
8005cf4: 617b str r3, [r7, #20]
8005cf6: 697b ldr r3, [r7, #20]
8005cf8: b29b uxth r3, r3
8005cfa: 029b lsls r3, r3, #10
8005cfc: b29b uxth r3, r3
8005cfe: ea6f 4343 mvn.w r3, r3, lsl #17
8005d02: ea6f 4353 mvn.w r3, r3, lsr #17
8005d06: b29b uxth r3, r3
8005d08: 8023 strh r3, [r4, #0]
8005d0a: e013 b.n 8005d34 <USB_EPStartXfer+0x52c>
8005d0c: 683b ldr r3, [r7, #0]
8005d0e: 785b ldrb r3, [r3, #1]
8005d10: 2b01 cmp r3, #1
8005d12: d10f bne.n 8005d34 <USB_EPStartXfer+0x52c>
8005d14: 687b ldr r3, [r7, #4]
8005d16: f8b3 3050 ldrh.w r3, [r3, #80] ; 0x50
8005d1a: b29b uxth r3, r3
8005d1c: 441c add r4, r3
8005d1e: 683b ldr r3, [r7, #0]
8005d20: 781b ldrb r3, [r3, #0]
8005d22: 011b lsls r3, r3, #4
8005d24: 4423 add r3, r4
8005d26: f203 430c addw r3, r3, #1036 ; 0x40c
8005d2a: 613b str r3, [r7, #16]
8005d2c: 6abb ldr r3, [r7, #40] ; 0x28
8005d2e: b29a uxth r2, r3
8005d30: 693b ldr r3, [r7, #16]
8005d32: 801a strh r2, [r3, #0]
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8005d34: 687a ldr r2, [r7, #4]
8005d36: 683b ldr r3, [r7, #0]
8005d38: 781b ldrb r3, [r3, #0]
8005d3a: 009b lsls r3, r3, #2
8005d3c: 4413 add r3, r2
8005d3e: 881b ldrh r3, [r3, #0]
8005d40: b29b uxth r3, r3
8005d42: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8005d46: f023 0370 bic.w r3, r3, #112 ; 0x70
8005d4a: b29c uxth r4, r3
8005d4c: f484 5380 eor.w r3, r4, #4096 ; 0x1000
8005d50: b29c uxth r4, r3
8005d52: f484 5300 eor.w r3, r4, #8192 ; 0x2000
8005d56: b29c uxth r4, r3
8005d58: 687a ldr r2, [r7, #4]
8005d5a: 683b ldr r3, [r7, #0]
8005d5c: 781b ldrb r3, [r3, #0]
8005d5e: 009b lsls r3, r3, #2
8005d60: 441a add r2, r3
8005d62: 4b04 ldr r3, [pc, #16] ; (8005d74 <USB_EPStartXfer+0x56c>)
8005d64: 4323 orrs r3, r4
8005d66: b29b uxth r3, r3
8005d68: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8005d6a: 2300 movs r3, #0
}
8005d6c: 4618 mov r0, r3
8005d6e: 3734 adds r7, #52 ; 0x34
8005d70: 46bd mov sp, r7
8005d72: bd90 pop {r4, r7, pc}
8005d74: ffff8080 .word 0xffff8080
08005d78 <USB_EPSetStall>:
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8005d78: b490 push {r4, r7}
8005d7a: b082 sub sp, #8
8005d7c: af00 add r7, sp, #0
8005d7e: 6078 str r0, [r7, #4]
8005d80: 6039 str r1, [r7, #0]
if (ep->is_in != 0U)
8005d82: 683b ldr r3, [r7, #0]
8005d84: 785b ldrb r3, [r3, #1]
8005d86: 2b00 cmp r3, #0
8005d88: d018 beq.n 8005dbc <USB_EPSetStall+0x44>
{
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
8005d8a: 687a ldr r2, [r7, #4]
8005d8c: 683b ldr r3, [r7, #0]
8005d8e: 781b ldrb r3, [r3, #0]
8005d90: 009b lsls r3, r3, #2
8005d92: 4413 add r3, r2
8005d94: 881b ldrh r3, [r3, #0]
8005d96: b29b uxth r3, r3
8005d98: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005d9c: f023 0340 bic.w r3, r3, #64 ; 0x40
8005da0: b29c uxth r4, r3
8005da2: f084 0310 eor.w r3, r4, #16
8005da6: b29c uxth r4, r3
8005da8: 687a ldr r2, [r7, #4]
8005daa: 683b ldr r3, [r7, #0]
8005dac: 781b ldrb r3, [r3, #0]
8005dae: 009b lsls r3, r3, #2
8005db0: 441a add r2, r3
8005db2: 4b11 ldr r3, [pc, #68] ; (8005df8 <USB_EPSetStall+0x80>)
8005db4: 4323 orrs r3, r4
8005db6: b29b uxth r3, r3
8005db8: 8013 strh r3, [r2, #0]
8005dba: e017 b.n 8005dec <USB_EPSetStall+0x74>
}
else
{
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
8005dbc: 687a ldr r2, [r7, #4]
8005dbe: 683b ldr r3, [r7, #0]
8005dc0: 781b ldrb r3, [r3, #0]
8005dc2: 009b lsls r3, r3, #2
8005dc4: 4413 add r3, r2
8005dc6: 881b ldrh r3, [r3, #0]
8005dc8: b29b uxth r3, r3
8005dca: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8005dce: f023 0370 bic.w r3, r3, #112 ; 0x70
8005dd2: b29c uxth r4, r3
8005dd4: f484 5380 eor.w r3, r4, #4096 ; 0x1000
8005dd8: b29c uxth r4, r3
8005dda: 687a ldr r2, [r7, #4]
8005ddc: 683b ldr r3, [r7, #0]
8005dde: 781b ldrb r3, [r3, #0]
8005de0: 009b lsls r3, r3, #2
8005de2: 441a add r2, r3
8005de4: 4b04 ldr r3, [pc, #16] ; (8005df8 <USB_EPSetStall+0x80>)
8005de6: 4323 orrs r3, r4
8005de8: b29b uxth r3, r3
8005dea: 8013 strh r3, [r2, #0]
}
return HAL_OK;
8005dec: 2300 movs r3, #0
}
8005dee: 4618 mov r0, r3
8005df0: 3708 adds r7, #8
8005df2: 46bd mov sp, r7
8005df4: bc90 pop {r4, r7}
8005df6: 4770 bx lr
8005df8: ffff8080 .word 0xffff8080
08005dfc <USB_EPClearStall>:
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
8005dfc: b490 push {r4, r7}
8005dfe: b082 sub sp, #8
8005e00: af00 add r7, sp, #0
8005e02: 6078 str r0, [r7, #4]
8005e04: 6039 str r1, [r7, #0]
if (ep->doublebuffer == 0U)
8005e06: 683b ldr r3, [r7, #0]
8005e08: 7b1b ldrb r3, [r3, #12]
8005e0a: 2b00 cmp r3, #0
8005e0c: d17d bne.n 8005f0a <USB_EPClearStall+0x10e>
{
if (ep->is_in != 0U)
8005e0e: 683b ldr r3, [r7, #0]
8005e10: 785b ldrb r3, [r3, #1]
8005e12: 2b00 cmp r3, #0
8005e14: d03d beq.n 8005e92 <USB_EPClearStall+0x96>
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
8005e16: 687a ldr r2, [r7, #4]
8005e18: 683b ldr r3, [r7, #0]
8005e1a: 781b ldrb r3, [r3, #0]
8005e1c: 009b lsls r3, r3, #2
8005e1e: 4413 add r3, r2
8005e20: 881b ldrh r3, [r3, #0]
8005e22: b29c uxth r4, r3
8005e24: 4623 mov r3, r4
8005e26: f003 0340 and.w r3, r3, #64 ; 0x40
8005e2a: 2b00 cmp r3, #0
8005e2c: d014 beq.n 8005e58 <USB_EPClearStall+0x5c>
8005e2e: 687a ldr r2, [r7, #4]
8005e30: 683b ldr r3, [r7, #0]
8005e32: 781b ldrb r3, [r3, #0]
8005e34: 009b lsls r3, r3, #2
8005e36: 4413 add r3, r2
8005e38: 881b ldrh r3, [r3, #0]
8005e3a: b29b uxth r3, r3
8005e3c: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005e40: f023 0370 bic.w r3, r3, #112 ; 0x70
8005e44: b29c uxth r4, r3
8005e46: 687a ldr r2, [r7, #4]
8005e48: 683b ldr r3, [r7, #0]
8005e4a: 781b ldrb r3, [r3, #0]
8005e4c: 009b lsls r3, r3, #2
8005e4e: 441a add r2, r3
8005e50: 4b31 ldr r3, [pc, #196] ; (8005f18 <USB_EPClearStall+0x11c>)
8005e52: 4323 orrs r3, r4
8005e54: b29b uxth r3, r3
8005e56: 8013 strh r3, [r2, #0]
if (ep->type != EP_TYPE_ISOC)
8005e58: 683b ldr r3, [r7, #0]
8005e5a: 78db ldrb r3, [r3, #3]
8005e5c: 2b01 cmp r3, #1
8005e5e: d054 beq.n 8005f0a <USB_EPClearStall+0x10e>
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
8005e60: 687a ldr r2, [r7, #4]
8005e62: 683b ldr r3, [r7, #0]
8005e64: 781b ldrb r3, [r3, #0]
8005e66: 009b lsls r3, r3, #2
8005e68: 4413 add r3, r2
8005e6a: 881b ldrh r3, [r3, #0]
8005e6c: b29b uxth r3, r3
8005e6e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005e72: f023 0340 bic.w r3, r3, #64 ; 0x40
8005e76: b29c uxth r4, r3
8005e78: f084 0320 eor.w r3, r4, #32
8005e7c: b29c uxth r4, r3
8005e7e: 687a ldr r2, [r7, #4]
8005e80: 683b ldr r3, [r7, #0]
8005e82: 781b ldrb r3, [r3, #0]
8005e84: 009b lsls r3, r3, #2
8005e86: 441a add r2, r3
8005e88: 4b24 ldr r3, [pc, #144] ; (8005f1c <USB_EPClearStall+0x120>)
8005e8a: 4323 orrs r3, r4
8005e8c: b29b uxth r3, r3
8005e8e: 8013 strh r3, [r2, #0]
8005e90: e03b b.n 8005f0a <USB_EPClearStall+0x10e>
}
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
8005e92: 687a ldr r2, [r7, #4]
8005e94: 683b ldr r3, [r7, #0]
8005e96: 781b ldrb r3, [r3, #0]
8005e98: 009b lsls r3, r3, #2
8005e9a: 4413 add r3, r2
8005e9c: 881b ldrh r3, [r3, #0]
8005e9e: b29c uxth r4, r3
8005ea0: 4623 mov r3, r4
8005ea2: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005ea6: 2b00 cmp r3, #0
8005ea8: d014 beq.n 8005ed4 <USB_EPClearStall+0xd8>
8005eaa: 687a ldr r2, [r7, #4]
8005eac: 683b ldr r3, [r7, #0]
8005eae: 781b ldrb r3, [r3, #0]
8005eb0: 009b lsls r3, r3, #2
8005eb2: 4413 add r3, r2
8005eb4: 881b ldrh r3, [r3, #0]
8005eb6: b29b uxth r3, r3
8005eb8: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8005ebc: f023 0370 bic.w r3, r3, #112 ; 0x70
8005ec0: b29c uxth r4, r3
8005ec2: 687a ldr r2, [r7, #4]
8005ec4: 683b ldr r3, [r7, #0]
8005ec6: 781b ldrb r3, [r3, #0]
8005ec8: 009b lsls r3, r3, #2
8005eca: 441a add r2, r3
8005ecc: 4b14 ldr r3, [pc, #80] ; (8005f20 <USB_EPClearStall+0x124>)
8005ece: 4323 orrs r3, r4
8005ed0: b29b uxth r3, r3
8005ed2: 8013 strh r3, [r2, #0]
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
8005ed4: 687a ldr r2, [r7, #4]
8005ed6: 683b ldr r3, [r7, #0]
8005ed8: 781b ldrb r3, [r3, #0]
8005eda: 009b lsls r3, r3, #2
8005edc: 4413 add r3, r2
8005ede: 881b ldrh r3, [r3, #0]
8005ee0: b29b uxth r3, r3
8005ee2: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8005ee6: f023 0370 bic.w r3, r3, #112 ; 0x70
8005eea: b29c uxth r4, r3
8005eec: f484 5380 eor.w r3, r4, #4096 ; 0x1000
8005ef0: b29c uxth r4, r3
8005ef2: f484 5300 eor.w r3, r4, #8192 ; 0x2000
8005ef6: b29c uxth r4, r3
8005ef8: 687a ldr r2, [r7, #4]
8005efa: 683b ldr r3, [r7, #0]
8005efc: 781b ldrb r3, [r3, #0]
8005efe: 009b lsls r3, r3, #2
8005f00: 441a add r2, r3
8005f02: 4b06 ldr r3, [pc, #24] ; (8005f1c <USB_EPClearStall+0x120>)
8005f04: 4323 orrs r3, r4
8005f06: b29b uxth r3, r3
8005f08: 8013 strh r3, [r2, #0]
}
}
return HAL_OK;
8005f0a: 2300 movs r3, #0
}
8005f0c: 4618 mov r0, r3
8005f0e: 3708 adds r7, #8
8005f10: 46bd mov sp, r7
8005f12: bc90 pop {r4, r7}
8005f14: 4770 bx lr
8005f16: bf00 nop
8005f18: ffff80c0 .word 0xffff80c0
8005f1c: ffff8080 .word 0xffff8080
8005f20: ffffc080 .word 0xffffc080
08005f24 <USB_SetDevAddress>:
* @param address : new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
{
8005f24: b480 push {r7}
8005f26: b083 sub sp, #12
8005f28: af00 add r7, sp, #0
8005f2a: 6078 str r0, [r7, #4]
8005f2c: 460b mov r3, r1
8005f2e: 70fb strb r3, [r7, #3]
if (address == 0U)
8005f30: 78fb ldrb r3, [r7, #3]
8005f32: 2b00 cmp r3, #0
8005f34: d103 bne.n 8005f3e <USB_SetDevAddress+0x1a>
{
/* set device address and enable function */
USBx->DADDR = USB_DADDR_EF;
8005f36: 687b ldr r3, [r7, #4]
8005f38: 2280 movs r2, #128 ; 0x80
8005f3a: f8a3 204c strh.w r2, [r3, #76] ; 0x4c
}
return HAL_OK;
8005f3e: 2300 movs r3, #0
}
8005f40: 4618 mov r0, r3
8005f42: 370c adds r7, #12
8005f44: 46bd mov sp, r7
8005f46: bc80 pop {r7}
8005f48: 4770 bx lr
08005f4a <USB_DevConnect>:
* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
8005f4a: b480 push {r7}
8005f4c: b083 sub sp, #12
8005f4e: af00 add r7, sp, #0
8005f50: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8005f52: 2300 movs r3, #0
}
8005f54: 4618 mov r0, r3
8005f56: 370c adds r7, #12
8005f58: 46bd mov sp, r7
8005f5a: bc80 pop {r7}
8005f5c: 4770 bx lr
08005f5e <USB_DevDisconnect>:
* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
{
8005f5e: b480 push {r7}
8005f60: b083 sub sp, #12
8005f62: af00 add r7, sp, #0
8005f64: 6078 str r0, [r7, #4]
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8005f66: 2300 movs r3, #0
}
8005f68: 4618 mov r0, r3
8005f6a: 370c adds r7, #12
8005f6c: 46bd mov sp, r7
8005f6e: bc80 pop {r7}
8005f70: 4770 bx lr
08005f72 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts: return the global USB interrupt status
* @param USBx : Selected device
* @retval HAL status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
{
8005f72: b480 push {r7}
8005f74: b085 sub sp, #20
8005f76: af00 add r7, sp, #0
8005f78: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->ISTR;
8005f7a: 687b ldr r3, [r7, #4]
8005f7c: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44
8005f80: b29b uxth r3, r3
8005f82: 60fb str r3, [r7, #12]
return tmpreg;
8005f84: 68fb ldr r3, [r7, #12]
}
8005f86: 4618 mov r0, r3
8005f88: 3714 adds r7, #20
8005f8a: 46bd mov sp, r7
8005f8c: bc80 pop {r7}
8005f8e: 4770 bx lr
08005f90 <USB_EP0_OutStart>:
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
{
8005f90: b480 push {r7}
8005f92: b083 sub sp, #12
8005f94: af00 add r7, sp, #0
8005f96: 6078 str r0, [r7, #4]
8005f98: 6039 str r1, [r7, #0]
UNUSED(psetup);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
8005f9a: 2300 movs r3, #0
}
8005f9c: 4618 mov r0, r3
8005f9e: 370c adds r7, #12
8005fa0: 46bd mov sp, r7
8005fa2: bc80 pop {r7}
8005fa4: 4770 bx lr
08005fa6 <USB_WritePMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
8005fa6: b480 push {r7}
8005fa8: b08d sub sp, #52 ; 0x34
8005faa: af00 add r7, sp, #0
8005fac: 60f8 str r0, [r7, #12]
8005fae: 60b9 str r1, [r7, #8]
8005fb0: 4611 mov r1, r2
8005fb2: 461a mov r2, r3
8005fb4: 460b mov r3, r1
8005fb6: 80fb strh r3, [r7, #6]
8005fb8: 4613 mov r3, r2
8005fba: 80bb strh r3, [r7, #4]
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
8005fbc: 88bb ldrh r3, [r7, #4]
8005fbe: 3301 adds r3, #1
8005fc0: 085b lsrs r3, r3, #1
8005fc2: 623b str r3, [r7, #32]
uint32_t BaseAddr = (uint32_t)USBx;
8005fc4: 68fb ldr r3, [r7, #12]
8005fc6: 61fb str r3, [r7, #28]
uint32_t i, temp1, temp2;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
8005fc8: 68bb ldr r3, [r7, #8]
8005fca: 627b str r3, [r7, #36] ; 0x24
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
8005fcc: 88fb ldrh r3, [r7, #6]
8005fce: 005a lsls r2, r3, #1
8005fd0: 69fb ldr r3, [r7, #28]
8005fd2: 4413 add r3, r2
8005fd4: f503 6380 add.w r3, r3, #1024 ; 0x400
8005fd8: 62bb str r3, [r7, #40] ; 0x28
for (i = n; i != 0U; i--)
8005fda: 6a3b ldr r3, [r7, #32]
8005fdc: 62fb str r3, [r7, #44] ; 0x2c
8005fde: e01e b.n 800601e <USB_WritePMA+0x78>
{
temp1 = *pBuf;
8005fe0: 6a7b ldr r3, [r7, #36] ; 0x24
8005fe2: 781b ldrb r3, [r3, #0]
8005fe4: 61bb str r3, [r7, #24]
pBuf++;
8005fe6: 6a7b ldr r3, [r7, #36] ; 0x24
8005fe8: 3301 adds r3, #1
8005fea: 627b str r3, [r7, #36] ; 0x24
temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
8005fec: 6a7b ldr r3, [r7, #36] ; 0x24
8005fee: 781b ldrb r3, [r3, #0]
8005ff0: b29b uxth r3, r3
8005ff2: 021b lsls r3, r3, #8
8005ff4: b29b uxth r3, r3
8005ff6: 461a mov r2, r3
8005ff8: 69bb ldr r3, [r7, #24]
8005ffa: 4313 orrs r3, r2
8005ffc: 617b str r3, [r7, #20]
*pdwVal = (uint16_t)temp2;
8005ffe: 697b ldr r3, [r7, #20]
8006000: b29a uxth r2, r3
8006002: 6abb ldr r3, [r7, #40] ; 0x28
8006004: 801a strh r2, [r3, #0]
pdwVal++;
8006006: 6abb ldr r3, [r7, #40] ; 0x28
8006008: 3302 adds r3, #2
800600a: 62bb str r3, [r7, #40] ; 0x28
#if PMA_ACCESS > 1U
pdwVal++;
800600c: 6abb ldr r3, [r7, #40] ; 0x28
800600e: 3302 adds r3, #2
8006010: 62bb str r3, [r7, #40] ; 0x28
#endif
pBuf++;
8006012: 6a7b ldr r3, [r7, #36] ; 0x24
8006014: 3301 adds r3, #1
8006016: 627b str r3, [r7, #36] ; 0x24
for (i = n; i != 0U; i--)
8006018: 6afb ldr r3, [r7, #44] ; 0x2c
800601a: 3b01 subs r3, #1
800601c: 62fb str r3, [r7, #44] ; 0x2c
800601e: 6afb ldr r3, [r7, #44] ; 0x2c
8006020: 2b00 cmp r3, #0
8006022: d1dd bne.n 8005fe0 <USB_WritePMA+0x3a>
}
}
8006024: bf00 nop
8006026: 3734 adds r7, #52 ; 0x34
8006028: 46bd mov sp, r7
800602a: bc80 pop {r7}
800602c: 4770 bx lr
0800602e <USB_ReadPMA>:
* @param wPMABufAddr address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
800602e: b480 push {r7}
8006030: b08b sub sp, #44 ; 0x2c
8006032: af00 add r7, sp, #0
8006034: 60f8 str r0, [r7, #12]
8006036: 60b9 str r1, [r7, #8]
8006038: 4611 mov r1, r2
800603a: 461a mov r2, r3
800603c: 460b mov r3, r1
800603e: 80fb strh r3, [r7, #6]
8006040: 4613 mov r3, r2
8006042: 80bb strh r3, [r7, #4]
uint32_t n = (uint32_t)wNBytes >> 1;
8006044: 88bb ldrh r3, [r7, #4]
8006046: 085b lsrs r3, r3, #1
8006048: b29b uxth r3, r3
800604a: 61bb str r3, [r7, #24]
uint32_t BaseAddr = (uint32_t)USBx;
800604c: 68fb ldr r3, [r7, #12]
800604e: 617b str r3, [r7, #20]
uint32_t i, temp;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
8006050: 68bb ldr r3, [r7, #8]
8006052: 61fb str r3, [r7, #28]
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
8006054: 88fb ldrh r3, [r7, #6]
8006056: 005a lsls r2, r3, #1
8006058: 697b ldr r3, [r7, #20]
800605a: 4413 add r3, r2
800605c: f503 6380 add.w r3, r3, #1024 ; 0x400
8006060: 623b str r3, [r7, #32]
for (i = n; i != 0U; i--)
8006062: 69bb ldr r3, [r7, #24]
8006064: 627b str r3, [r7, #36] ; 0x24
8006066: e01b b.n 80060a0 <USB_ReadPMA+0x72>
{
temp = *(__IO uint16_t *)pdwVal;
8006068: 6a3b ldr r3, [r7, #32]
800606a: 881b ldrh r3, [r3, #0]
800606c: b29b uxth r3, r3
800606e: 613b str r3, [r7, #16]
pdwVal++;
8006070: 6a3b ldr r3, [r7, #32]
8006072: 3302 adds r3, #2
8006074: 623b str r3, [r7, #32]
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
8006076: 693b ldr r3, [r7, #16]
8006078: b2da uxtb r2, r3
800607a: 69fb ldr r3, [r7, #28]
800607c: 701a strb r2, [r3, #0]
pBuf++;
800607e: 69fb ldr r3, [r7, #28]
8006080: 3301 adds r3, #1
8006082: 61fb str r3, [r7, #28]
*pBuf = (uint8_t)((temp >> 8) & 0xFFU);
8006084: 693b ldr r3, [r7, #16]
8006086: 0a1b lsrs r3, r3, #8
8006088: b2da uxtb r2, r3
800608a: 69fb ldr r3, [r7, #28]
800608c: 701a strb r2, [r3, #0]
pBuf++;
800608e: 69fb ldr r3, [r7, #28]
8006090: 3301 adds r3, #1
8006092: 61fb str r3, [r7, #28]
#if PMA_ACCESS > 1U
pdwVal++;
8006094: 6a3b ldr r3, [r7, #32]
8006096: 3302 adds r3, #2
8006098: 623b str r3, [r7, #32]
for (i = n; i != 0U; i--)
800609a: 6a7b ldr r3, [r7, #36] ; 0x24
800609c: 3b01 subs r3, #1
800609e: 627b str r3, [r7, #36] ; 0x24
80060a0: 6a7b ldr r3, [r7, #36] ; 0x24
80060a2: 2b00 cmp r3, #0
80060a4: d1e0 bne.n 8006068 <USB_ReadPMA+0x3a>
#endif
}
if ((wNBytes % 2U) != 0U)
80060a6: 88bb ldrh r3, [r7, #4]
80060a8: f003 0301 and.w r3, r3, #1
80060ac: b29b uxth r3, r3
80060ae: 2b00 cmp r3, #0
80060b0: d007 beq.n 80060c2 <USB_ReadPMA+0x94>
{
temp = *pdwVal;
80060b2: 6a3b ldr r3, [r7, #32]
80060b4: 881b ldrh r3, [r3, #0]
80060b6: b29b uxth r3, r3
80060b8: 613b str r3, [r7, #16]
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
80060ba: 693b ldr r3, [r7, #16]
80060bc: b2da uxtb r2, r3
80060be: 69fb ldr r3, [r7, #28]
80060c0: 701a strb r2, [r3, #0]
}
}
80060c2: bf00 nop
80060c4: 372c adds r7, #44 ; 0x2c
80060c6: 46bd mov sp, r7
80060c8: bc80 pop {r7}
80060ca: 4770 bx lr
080060cc <USBD_CDC_Init>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
80060cc: b580 push {r7, lr}
80060ce: b084 sub sp, #16
80060d0: af00 add r7, sp, #0
80060d2: 6078 str r0, [r7, #4]
80060d4: 460b mov r3, r1
80060d6: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
80060d8: 2300 movs r3, #0
80060da: 73fb strb r3, [r7, #15]
USBD_CDC_HandleTypeDef *hcdc;
if (pdev->dev_speed == USBD_SPEED_HIGH)
80060dc: 687b ldr r3, [r7, #4]
80060de: 7c1b ldrb r3, [r3, #16]
80060e0: 2b00 cmp r3, #0
80060e2: d115 bne.n 8006110 <USBD_CDC_Init+0x44>
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
80060e4: f44f 7300 mov.w r3, #512 ; 0x200
80060e8: 2202 movs r2, #2
80060ea: 2181 movs r1, #129 ; 0x81
80060ec: 6878 ldr r0, [r7, #4]
80060ee: f001 fe8e bl 8007e0e <USBD_LL_OpenEP>
CDC_DATA_HS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
80060f2: 687b ldr r3, [r7, #4]
80060f4: 2201 movs r2, #1
80060f6: 62da str r2, [r3, #44] ; 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
80060f8: f44f 7300 mov.w r3, #512 ; 0x200
80060fc: 2202 movs r2, #2
80060fe: 2101 movs r1, #1
8006100: 6878 ldr r0, [r7, #4]
8006102: f001 fe84 bl 8007e0e <USBD_LL_OpenEP>
CDC_DATA_HS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
8006106: 687b ldr r3, [r7, #4]
8006108: 2201 movs r2, #1
800610a: f8c3 216c str.w r2, [r3, #364] ; 0x16c
800610e: e012 b.n 8006136 <USBD_CDC_Init+0x6a>
}
else
{
/* Open EP IN */
USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK,
8006110: 2340 movs r3, #64 ; 0x40
8006112: 2202 movs r2, #2
8006114: 2181 movs r1, #129 ; 0x81
8006116: 6878 ldr r0, [r7, #4]
8006118: f001 fe79 bl 8007e0e <USBD_LL_OpenEP>
CDC_DATA_FS_IN_PACKET_SIZE);
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U;
800611c: 687b ldr r3, [r7, #4]
800611e: 2201 movs r2, #1
8006120: 62da str r2, [r3, #44] ; 0x2c
/* Open EP OUT */
USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK,
8006122: 2340 movs r3, #64 ; 0x40
8006124: 2202 movs r2, #2
8006126: 2101 movs r1, #1
8006128: 6878 ldr r0, [r7, #4]
800612a: f001 fe70 bl 8007e0e <USBD_LL_OpenEP>
CDC_DATA_FS_OUT_PACKET_SIZE);
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U;
800612e: 687b ldr r3, [r7, #4]
8006130: 2201 movs r2, #1
8006132: f8c3 216c str.w r2, [r3, #364] ; 0x16c
}
/* Open Command IN EP */
USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE);
8006136: 2308 movs r3, #8
8006138: 2203 movs r2, #3
800613a: 2182 movs r1, #130 ; 0x82
800613c: 6878 ldr r0, [r7, #4]
800613e: f001 fe66 bl 8007e0e <USBD_LL_OpenEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U;
8006142: 687b ldr r3, [r7, #4]
8006144: 2201 movs r2, #1
8006146: 641a str r2, [r3, #64] ; 0x40
pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef));
8006148: f44f 7007 mov.w r0, #540 ; 0x21c
800614c: f001 ff80 bl 8008050 <USBD_static_malloc>
8006150: 4602 mov r2, r0
8006152: 687b ldr r3, [r7, #4]
8006154: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8
if (pdev->pClassData == NULL)
8006158: 687b ldr r3, [r7, #4]
800615a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
800615e: 2b00 cmp r3, #0
8006160: d102 bne.n 8006168 <USBD_CDC_Init+0x9c>
{
ret = 1U;
8006162: 2301 movs r3, #1
8006164: 73fb strb r3, [r7, #15]
8006166: e026 b.n 80061b6 <USBD_CDC_Init+0xea>
}
else
{
hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8006168: 687b ldr r3, [r7, #4]
800616a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
800616e: 60bb str r3, [r7, #8]
/* Init physical Interface components */
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();
8006170: 687b ldr r3, [r7, #4]
8006172: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
8006176: 681b ldr r3, [r3, #0]
8006178: 4798 blx r3
/* Init Xfer states */
hcdc->TxState = 0U;
800617a: 68bb ldr r3, [r7, #8]
800617c: 2200 movs r2, #0
800617e: f8c3 2214 str.w r2, [r3, #532] ; 0x214
hcdc->RxState = 0U;
8006182: 68bb ldr r3, [r7, #8]
8006184: 2200 movs r2, #0
8006186: f8c3 2218 str.w r2, [r3, #536] ; 0x218
if (pdev->dev_speed == USBD_SPEED_HIGH)
800618a: 687b ldr r3, [r7, #4]
800618c: 7c1b ldrb r3, [r3, #16]
800618e: 2b00 cmp r3, #0
8006190: d109 bne.n 80061a6 <USBD_CDC_Init+0xda>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
8006192: 68bb ldr r3, [r7, #8]
8006194: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
8006198: f44f 7300 mov.w r3, #512 ; 0x200
800619c: 2101 movs r1, #1
800619e: 6878 ldr r0, [r7, #4]
80061a0: f001 ff1f bl 8007fe2 <USBD_LL_PrepareReceive>
80061a4: e007 b.n 80061b6 <USBD_CDC_Init+0xea>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer,
80061a6: 68bb ldr r3, [r7, #8]
80061a8: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
80061ac: 2340 movs r3, #64 ; 0x40
80061ae: 2101 movs r1, #1
80061b0: 6878 ldr r0, [r7, #4]
80061b2: f001 ff16 bl 8007fe2 <USBD_LL_PrepareReceive>
CDC_DATA_FS_OUT_PACKET_SIZE);
}
}
return ret;
80061b6: 7bfb ldrb r3, [r7, #15]
}
80061b8: 4618 mov r0, r3
80061ba: 3710 adds r7, #16
80061bc: 46bd mov sp, r7
80061be: bd80 pop {r7, pc}
080061c0 <USBD_CDC_DeInit>:
* @param pdev: device instance
* @param cfgidx: Configuration index
* @retval status
*/
static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
80061c0: b580 push {r7, lr}
80061c2: b084 sub sp, #16
80061c4: af00 add r7, sp, #0
80061c6: 6078 str r0, [r7, #4]
80061c8: 460b mov r3, r1
80061ca: 70fb strb r3, [r7, #3]
uint8_t ret = 0U;
80061cc: 2300 movs r3, #0
80061ce: 73fb strb r3, [r7, #15]
/* Close EP IN */
USBD_LL_CloseEP(pdev, CDC_IN_EP);
80061d0: 2181 movs r1, #129 ; 0x81
80061d2: 6878 ldr r0, [r7, #4]
80061d4: f001 fe41 bl 8007e5a <USBD_LL_CloseEP>
pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U;
80061d8: 687b ldr r3, [r7, #4]
80061da: 2200 movs r2, #0
80061dc: 62da str r2, [r3, #44] ; 0x2c
/* Close EP OUT */
USBD_LL_CloseEP(pdev, CDC_OUT_EP);
80061de: 2101 movs r1, #1
80061e0: 6878 ldr r0, [r7, #4]
80061e2: f001 fe3a bl 8007e5a <USBD_LL_CloseEP>
pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U;
80061e6: 687b ldr r3, [r7, #4]
80061e8: 2200 movs r2, #0
80061ea: f8c3 216c str.w r2, [r3, #364] ; 0x16c
/* Close Command IN EP */
USBD_LL_CloseEP(pdev, CDC_CMD_EP);
80061ee: 2182 movs r1, #130 ; 0x82
80061f0: 6878 ldr r0, [r7, #4]
80061f2: f001 fe32 bl 8007e5a <USBD_LL_CloseEP>
pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U;
80061f6: 687b ldr r3, [r7, #4]
80061f8: 2200 movs r2, #0
80061fa: 641a str r2, [r3, #64] ; 0x40
/* DeInit physical Interface components */
if (pdev->pClassData != NULL)
80061fc: 687b ldr r3, [r7, #4]
80061fe: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006202: 2b00 cmp r3, #0
8006204: d00e beq.n 8006224 <USBD_CDC_DeInit+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();
8006206: 687b ldr r3, [r7, #4]
8006208: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
800620c: 685b ldr r3, [r3, #4]
800620e: 4798 blx r3
USBD_free(pdev->pClassData);
8006210: 687b ldr r3, [r7, #4]
8006212: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006216: 4618 mov r0, r3
8006218: f001 ff26 bl 8008068 <USBD_static_free>
pdev->pClassData = NULL;
800621c: 687b ldr r3, [r7, #4]
800621e: 2200 movs r2, #0
8006220: f8c3 22b8 str.w r2, [r3, #696] ; 0x2b8
}
return ret;
8006224: 7bfb ldrb r3, [r7, #15]
}
8006226: 4618 mov r0, r3
8006228: 3710 adds r7, #16
800622a: 46bd mov sp, r7
800622c: bd80 pop {r7, pc}
0800622e <USBD_CDC_Setup>:
* @param req: usb requests
* @retval status
*/
static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
800622e: b580 push {r7, lr}
8006230: b086 sub sp, #24
8006232: af00 add r7, sp, #0
8006234: 6078 str r0, [r7, #4]
8006236: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
8006238: 687b ldr r3, [r7, #4]
800623a: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
800623e: 613b str r3, [r7, #16]
uint8_t ifalt = 0U;
8006240: 2300 movs r3, #0
8006242: 73fb strb r3, [r7, #15]
uint16_t status_info = 0U;
8006244: 2300 movs r3, #0
8006246: 81bb strh r3, [r7, #12]
uint8_t ret = USBD_OK;
8006248: 2300 movs r3, #0
800624a: 75fb strb r3, [r7, #23]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
800624c: 683b ldr r3, [r7, #0]
800624e: 781b ldrb r3, [r3, #0]
8006250: f003 0360 and.w r3, r3, #96 ; 0x60
8006254: 2b00 cmp r3, #0
8006256: d039 beq.n 80062cc <USBD_CDC_Setup+0x9e>
8006258: 2b20 cmp r3, #32
800625a: d17c bne.n 8006356 <USBD_CDC_Setup+0x128>
{
case USB_REQ_TYPE_CLASS :
if (req->wLength)
800625c: 683b ldr r3, [r7, #0]
800625e: 88db ldrh r3, [r3, #6]
8006260: 2b00 cmp r3, #0
8006262: d029 beq.n 80062b8 <USBD_CDC_Setup+0x8a>
{
if (req->bmRequest & 0x80U)
8006264: 683b ldr r3, [r7, #0]
8006266: 781b ldrb r3, [r3, #0]
8006268: b25b sxtb r3, r3
800626a: 2b00 cmp r3, #0
800626c: da11 bge.n 8006292 <USBD_CDC_Setup+0x64>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
800626e: 687b ldr r3, [r7, #4]
8006270: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
8006274: 689b ldr r3, [r3, #8]
8006276: 683a ldr r2, [r7, #0]
8006278: 7850 ldrb r0, [r2, #1]
(uint8_t *)(void *)hcdc->data,
800627a: 6939 ldr r1, [r7, #16]
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
800627c: 683a ldr r2, [r7, #0]
800627e: 88d2 ldrh r2, [r2, #6]
8006280: 4798 blx r3
req->wLength);
USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
8006282: 6939 ldr r1, [r7, #16]
8006284: 683b ldr r3, [r7, #0]
8006286: 88db ldrh r3, [r3, #6]
8006288: 461a mov r2, r3
800628a: 6878 ldr r0, [r7, #4]
800628c: f001 f9f6 bl 800767c <USBD_CtlSendData>
else
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
(uint8_t *)(void *)req, 0U);
}
break;
8006290: e068 b.n 8006364 <USBD_CDC_Setup+0x136>
hcdc->CmdOpCode = req->bRequest;
8006292: 683b ldr r3, [r7, #0]
8006294: 785a ldrb r2, [r3, #1]
8006296: 693b ldr r3, [r7, #16]
8006298: f883 2200 strb.w r2, [r3, #512] ; 0x200
hcdc->CmdLength = (uint8_t)req->wLength;
800629c: 683b ldr r3, [r7, #0]
800629e: 88db ldrh r3, [r3, #6]
80062a0: b2da uxtb r2, r3
80062a2: 693b ldr r3, [r7, #16]
80062a4: f883 2201 strb.w r2, [r3, #513] ; 0x201
USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength);
80062a8: 6939 ldr r1, [r7, #16]
80062aa: 683b ldr r3, [r7, #0]
80062ac: 88db ldrh r3, [r3, #6]
80062ae: 461a mov r2, r3
80062b0: 6878 ldr r0, [r7, #4]
80062b2: f001 fa11 bl 80076d8 <USBD_CtlPrepareRx>
break;
80062b6: e055 b.n 8006364 <USBD_CDC_Setup+0x136>
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,
80062b8: 687b ldr r3, [r7, #4]
80062ba: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
80062be: 689b ldr r3, [r3, #8]
80062c0: 683a ldr r2, [r7, #0]
80062c2: 7850 ldrb r0, [r2, #1]
80062c4: 2200 movs r2, #0
80062c6: 6839 ldr r1, [r7, #0]
80062c8: 4798 blx r3
break;
80062ca: e04b b.n 8006364 <USBD_CDC_Setup+0x136>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
80062cc: 683b ldr r3, [r7, #0]
80062ce: 785b ldrb r3, [r3, #1]
80062d0: 2b0a cmp r3, #10
80062d2: d017 beq.n 8006304 <USBD_CDC_Setup+0xd6>
80062d4: 2b0b cmp r3, #11
80062d6: d029 beq.n 800632c <USBD_CDC_Setup+0xfe>
80062d8: 2b00 cmp r3, #0
80062da: d133 bne.n 8006344 <USBD_CDC_Setup+0x116>
{
case USB_REQ_GET_STATUS:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
80062dc: 687b ldr r3, [r7, #4]
80062de: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
80062e2: 2b03 cmp r3, #3
80062e4: d107 bne.n 80062f6 <USBD_CDC_Setup+0xc8>
{
USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U);
80062e6: f107 030c add.w r3, r7, #12
80062ea: 2202 movs r2, #2
80062ec: 4619 mov r1, r3
80062ee: 6878 ldr r0, [r7, #4]
80062f0: f001 f9c4 bl 800767c <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
80062f4: e02e b.n 8006354 <USBD_CDC_Setup+0x126>
USBD_CtlError(pdev, req);
80062f6: 6839 ldr r1, [r7, #0]
80062f8: 6878 ldr r0, [r7, #4]
80062fa: f001 f955 bl 80075a8 <USBD_CtlError>
ret = USBD_FAIL;
80062fe: 2302 movs r3, #2
8006300: 75fb strb r3, [r7, #23]
break;
8006302: e027 b.n 8006354 <USBD_CDC_Setup+0x126>
case USB_REQ_GET_INTERFACE:
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8006304: 687b ldr r3, [r7, #4]
8006306: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
800630a: 2b03 cmp r3, #3
800630c: d107 bne.n 800631e <USBD_CDC_Setup+0xf0>
{
USBD_CtlSendData(pdev, &ifalt, 1U);
800630e: f107 030f add.w r3, r7, #15
8006312: 2201 movs r2, #1
8006314: 4619 mov r1, r3
8006316: 6878 ldr r0, [r7, #4]
8006318: f001 f9b0 bl 800767c <USBD_CtlSendData>
else
{
USBD_CtlError(pdev, req);
ret = USBD_FAIL;
}
break;
800631c: e01a b.n 8006354 <USBD_CDC_Setup+0x126>
USBD_CtlError(pdev, req);
800631e: 6839 ldr r1, [r7, #0]
8006320: 6878 ldr r0, [r7, #4]
8006322: f001 f941 bl 80075a8 <USBD_CtlError>
ret = USBD_FAIL;
8006326: 2302 movs r3, #2
8006328: 75fb strb r3, [r7, #23]
break;
800632a: e013 b.n 8006354 <USBD_CDC_Setup+0x126>
case USB_REQ_SET_INTERFACE:
if (pdev->dev_state != USBD_STATE_CONFIGURED)
800632c: 687b ldr r3, [r7, #4]
800632e: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8006332: 2b03 cmp r3, #3
8006334: d00d beq.n 8006352 <USBD_CDC_Setup+0x124>
{
USBD_CtlError(pdev, req);
8006336: 6839 ldr r1, [r7, #0]
8006338: 6878 ldr r0, [r7, #4]
800633a: f001 f935 bl 80075a8 <USBD_CtlError>
ret = USBD_FAIL;
800633e: 2302 movs r3, #2
8006340: 75fb strb r3, [r7, #23]
}
break;
8006342: e006 b.n 8006352 <USBD_CDC_Setup+0x124>
default:
USBD_CtlError(pdev, req);
8006344: 6839 ldr r1, [r7, #0]
8006346: 6878 ldr r0, [r7, #4]
8006348: f001 f92e bl 80075a8 <USBD_CtlError>
ret = USBD_FAIL;
800634c: 2302 movs r3, #2
800634e: 75fb strb r3, [r7, #23]
break;
8006350: e000 b.n 8006354 <USBD_CDC_Setup+0x126>
break;
8006352: bf00 nop
}
break;
8006354: e006 b.n 8006364 <USBD_CDC_Setup+0x136>
default:
USBD_CtlError(pdev, req);
8006356: 6839 ldr r1, [r7, #0]
8006358: 6878 ldr r0, [r7, #4]
800635a: f001 f925 bl 80075a8 <USBD_CtlError>
ret = USBD_FAIL;
800635e: 2302 movs r3, #2
8006360: 75fb strb r3, [r7, #23]
break;
8006362: bf00 nop
}
return ret;
8006364: 7dfb ldrb r3, [r7, #23]
}
8006366: 4618 mov r0, r3
8006368: 3718 adds r7, #24
800636a: 46bd mov sp, r7
800636c: bd80 pop {r7, pc}
0800636e <USBD_CDC_DataIn>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
800636e: b580 push {r7, lr}
8006370: b084 sub sp, #16
8006372: af00 add r7, sp, #0
8006374: 6078 str r0, [r7, #4]
8006376: 460b mov r3, r1
8006378: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData;
800637a: 687b ldr r3, [r7, #4]
800637c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006380: 60fb str r3, [r7, #12]
PCD_HandleTypeDef *hpcd = pdev->pData;
8006382: 687b ldr r3, [r7, #4]
8006384: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
8006388: 60bb str r3, [r7, #8]
if (pdev->pClassData != NULL)
800638a: 687b ldr r3, [r7, #4]
800638c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006390: 2b00 cmp r3, #0
8006392: d037 beq.n 8006404 <USBD_CDC_DataIn+0x96>
{
if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U))
8006394: 78fa ldrb r2, [r7, #3]
8006396: 6879 ldr r1, [r7, #4]
8006398: 4613 mov r3, r2
800639a: 009b lsls r3, r3, #2
800639c: 4413 add r3, r2
800639e: 009b lsls r3, r3, #2
80063a0: 440b add r3, r1
80063a2: 331c adds r3, #28
80063a4: 681b ldr r3, [r3, #0]
80063a6: 2b00 cmp r3, #0
80063a8: d026 beq.n 80063f8 <USBD_CDC_DataIn+0x8a>
80063aa: 78fa ldrb r2, [r7, #3]
80063ac: 6879 ldr r1, [r7, #4]
80063ae: 4613 mov r3, r2
80063b0: 009b lsls r3, r3, #2
80063b2: 4413 add r3, r2
80063b4: 009b lsls r3, r3, #2
80063b6: 440b add r3, r1
80063b8: 331c adds r3, #28
80063ba: 681b ldr r3, [r3, #0]
80063bc: 78fa ldrb r2, [r7, #3]
80063be: 68b9 ldr r1, [r7, #8]
80063c0: 0152 lsls r2, r2, #5
80063c2: 440a add r2, r1
80063c4: 3238 adds r2, #56 ; 0x38
80063c6: 6812 ldr r2, [r2, #0]
80063c8: fbb3 f1f2 udiv r1, r3, r2
80063cc: fb02 f201 mul.w r2, r2, r1
80063d0: 1a9b subs r3, r3, r2
80063d2: 2b00 cmp r3, #0
80063d4: d110 bne.n 80063f8 <USBD_CDC_DataIn+0x8a>
{
/* Update the packet total length */
pdev->ep_in[epnum].total_length = 0U;
80063d6: 78fa ldrb r2, [r7, #3]
80063d8: 6879 ldr r1, [r7, #4]
80063da: 4613 mov r3, r2
80063dc: 009b lsls r3, r3, #2
80063de: 4413 add r3, r2
80063e0: 009b lsls r3, r3, #2
80063e2: 440b add r3, r1
80063e4: 331c adds r3, #28
80063e6: 2200 movs r2, #0
80063e8: 601a str r2, [r3, #0]
/* Send ZLP */
USBD_LL_Transmit(pdev, epnum, NULL, 0U);
80063ea: 78f9 ldrb r1, [r7, #3]
80063ec: 2300 movs r3, #0
80063ee: 2200 movs r2, #0
80063f0: 6878 ldr r0, [r7, #4]
80063f2: f001 fdd3 bl 8007f9c <USBD_LL_Transmit>
80063f6: e003 b.n 8006400 <USBD_CDC_DataIn+0x92>
}
else
{
hcdc->TxState = 0U;
80063f8: 68fb ldr r3, [r7, #12]
80063fa: 2200 movs r2, #0
80063fc: f8c3 2214 str.w r2, [r3, #532] ; 0x214
}
return USBD_OK;
8006400: 2300 movs r3, #0
8006402: e000 b.n 8006406 <USBD_CDC_DataIn+0x98>
}
else
{
return USBD_FAIL;
8006404: 2302 movs r3, #2
}
}
8006406: 4618 mov r0, r3
8006408: 3710 adds r7, #16
800640a: 46bd mov sp, r7
800640c: bd80 pop {r7, pc}
0800640e <USBD_CDC_DataOut>:
* @param pdev: device instance
* @param epnum: endpoint number
* @retval status
*/
static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
{
800640e: b580 push {r7, lr}
8006410: b084 sub sp, #16
8006412: af00 add r7, sp, #0
8006414: 6078 str r0, [r7, #4]
8006416: 460b mov r3, r1
8006418: 70fb strb r3, [r7, #3]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800641a: 687b ldr r3, [r7, #4]
800641c: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006420: 60fb str r3, [r7, #12]
/* Get the received data length */
hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum);
8006422: 78fb ldrb r3, [r7, #3]
8006424: 4619 mov r1, r3
8006426: 6878 ldr r0, [r7, #4]
8006428: f001 fdfe bl 8008028 <USBD_LL_GetRxDataSize>
800642c: 4602 mov r2, r0
800642e: 68fb ldr r3, [r7, #12]
8006430: f8c3 220c str.w r2, [r3, #524] ; 0x20c
/* USB data will be immediately processed, this allow next USB traffic being
NAKed till the end of the application Xfer */
if (pdev->pClassData != NULL)
8006434: 687b ldr r3, [r7, #4]
8006436: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
800643a: 2b00 cmp r3, #0
800643c: d00d beq.n 800645a <USBD_CDC_DataOut+0x4c>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength);
800643e: 687b ldr r3, [r7, #4]
8006440: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
8006444: 68db ldr r3, [r3, #12]
8006446: 68fa ldr r2, [r7, #12]
8006448: f8d2 0204 ldr.w r0, [r2, #516] ; 0x204
800644c: 68fa ldr r2, [r7, #12]
800644e: f502 7203 add.w r2, r2, #524 ; 0x20c
8006452: 4611 mov r1, r2
8006454: 4798 blx r3
return USBD_OK;
8006456: 2300 movs r3, #0
8006458: e000 b.n 800645c <USBD_CDC_DataOut+0x4e>
}
else
{
return USBD_FAIL;
800645a: 2302 movs r3, #2
}
}
800645c: 4618 mov r0, r3
800645e: 3710 adds r7, #16
8006460: 46bd mov sp, r7
8006462: bd80 pop {r7, pc}
08006464 <USBD_CDC_EP0_RxReady>:
* Handle EP0 Rx Ready event
* @param pdev: device instance
* @retval status
*/
static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev)
{
8006464: b580 push {r7, lr}
8006466: b084 sub sp, #16
8006468: af00 add r7, sp, #0
800646a: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800646c: 687b ldr r3, [r7, #4]
800646e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006472: 60fb str r3, [r7, #12]
if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU))
8006474: 687b ldr r3, [r7, #4]
8006476: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
800647a: 2b00 cmp r3, #0
800647c: d015 beq.n 80064aa <USBD_CDC_EP0_RxReady+0x46>
800647e: 68fb ldr r3, [r7, #12]
8006480: f893 3200 ldrb.w r3, [r3, #512] ; 0x200
8006484: 2bff cmp r3, #255 ; 0xff
8006486: d010 beq.n 80064aa <USBD_CDC_EP0_RxReady+0x46>
{
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
8006488: 687b ldr r3, [r7, #4]
800648a: f8d3 32bc ldr.w r3, [r3, #700] ; 0x2bc
800648e: 689b ldr r3, [r3, #8]
8006490: 68fa ldr r2, [r7, #12]
8006492: f892 0200 ldrb.w r0, [r2, #512] ; 0x200
(uint8_t *)(void *)hcdc->data,
8006496: 68f9 ldr r1, [r7, #12]
(uint16_t)hcdc->CmdLength);
8006498: 68fa ldr r2, [r7, #12]
800649a: f892 2201 ldrb.w r2, [r2, #513] ; 0x201
((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,
800649e: b292 uxth r2, r2
80064a0: 4798 blx r3
hcdc->CmdOpCode = 0xFFU;
80064a2: 68fb ldr r3, [r7, #12]
80064a4: 22ff movs r2, #255 ; 0xff
80064a6: f883 2200 strb.w r2, [r3, #512] ; 0x200
}
return USBD_OK;
80064aa: 2300 movs r3, #0
}
80064ac: 4618 mov r0, r3
80064ae: 3710 adds r7, #16
80064b0: 46bd mov sp, r7
80064b2: bd80 pop {r7, pc}
080064b4 <USBD_CDC_GetFSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length)
{
80064b4: b480 push {r7}
80064b6: b083 sub sp, #12
80064b8: af00 add r7, sp, #0
80064ba: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgFSDesc);
80064bc: 687b ldr r3, [r7, #4]
80064be: 2243 movs r2, #67 ; 0x43
80064c0: 801a strh r2, [r3, #0]
return USBD_CDC_CfgFSDesc;
80064c2: 4b03 ldr r3, [pc, #12] ; (80064d0 <USBD_CDC_GetFSCfgDesc+0x1c>)
}
80064c4: 4618 mov r0, r3
80064c6: 370c adds r7, #12
80064c8: 46bd mov sp, r7
80064ca: bc80 pop {r7}
80064cc: 4770 bx lr
80064ce: bf00 nop
80064d0: 200000a0 .word 0x200000a0
080064d4 <USBD_CDC_GetHSCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length)
{
80064d4: b480 push {r7}
80064d6: b083 sub sp, #12
80064d8: af00 add r7, sp, #0
80064da: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_CfgHSDesc);
80064dc: 687b ldr r3, [r7, #4]
80064de: 2243 movs r2, #67 ; 0x43
80064e0: 801a strh r2, [r3, #0]
return USBD_CDC_CfgHSDesc;
80064e2: 4b03 ldr r3, [pc, #12] ; (80064f0 <USBD_CDC_GetHSCfgDesc+0x1c>)
}
80064e4: 4618 mov r0, r3
80064e6: 370c adds r7, #12
80064e8: 46bd mov sp, r7
80064ea: bc80 pop {r7}
80064ec: 4770 bx lr
80064ee: bf00 nop
80064f0: 2000005c .word 0x2000005c
080064f4 <USBD_CDC_GetOtherSpeedCfgDesc>:
* @param speed : current device speed
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length)
{
80064f4: b480 push {r7}
80064f6: b083 sub sp, #12
80064f8: af00 add r7, sp, #0
80064fa: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_OtherSpeedCfgDesc);
80064fc: 687b ldr r3, [r7, #4]
80064fe: 2243 movs r2, #67 ; 0x43
8006500: 801a strh r2, [r3, #0]
return USBD_CDC_OtherSpeedCfgDesc;
8006502: 4b03 ldr r3, [pc, #12] ; (8006510 <USBD_CDC_GetOtherSpeedCfgDesc+0x1c>)
}
8006504: 4618 mov r0, r3
8006506: 370c adds r7, #12
8006508: 46bd mov sp, r7
800650a: bc80 pop {r7}
800650c: 4770 bx lr
800650e: bf00 nop
8006510: 200000e4 .word 0x200000e4
08006514 <USBD_CDC_GetDeviceQualifierDescriptor>:
* return Device Qualifier descriptor
* @param length : pointer data length
* @retval pointer to descriptor buffer
*/
uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length)
{
8006514: b480 push {r7}
8006516: b083 sub sp, #12
8006518: af00 add r7, sp, #0
800651a: 6078 str r0, [r7, #4]
*length = sizeof(USBD_CDC_DeviceQualifierDesc);
800651c: 687b ldr r3, [r7, #4]
800651e: 220a movs r2, #10
8006520: 801a strh r2, [r3, #0]
return USBD_CDC_DeviceQualifierDesc;
8006522: 4b03 ldr r3, [pc, #12] ; (8006530 <USBD_CDC_GetDeviceQualifierDescriptor+0x1c>)
}
8006524: 4618 mov r0, r3
8006526: 370c adds r7, #12
8006528: 46bd mov sp, r7
800652a: bc80 pop {r7}
800652c: 4770 bx lr
800652e: bf00 nop
8006530: 20000018 .word 0x20000018
08006534 <USBD_CDC_RegisterInterface>:
* @param fops: CD Interface callback
* @retval status
*/
uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev,
USBD_CDC_ItfTypeDef *fops)
{
8006534: b480 push {r7}
8006536: b085 sub sp, #20
8006538: af00 add r7, sp, #0
800653a: 6078 str r0, [r7, #4]
800653c: 6039 str r1, [r7, #0]
uint8_t ret = USBD_FAIL;
800653e: 2302 movs r3, #2
8006540: 73fb strb r3, [r7, #15]
if (fops != NULL)
8006542: 683b ldr r3, [r7, #0]
8006544: 2b00 cmp r3, #0
8006546: d005 beq.n 8006554 <USBD_CDC_RegisterInterface+0x20>
{
pdev->pUserData = fops;
8006548: 687b ldr r3, [r7, #4]
800654a: 683a ldr r2, [r7, #0]
800654c: f8c3 22bc str.w r2, [r3, #700] ; 0x2bc
ret = USBD_OK;
8006550: 2300 movs r3, #0
8006552: 73fb strb r3, [r7, #15]
}
return ret;
8006554: 7bfb ldrb r3, [r7, #15]
}
8006556: 4618 mov r0, r3
8006558: 3714 adds r7, #20
800655a: 46bd mov sp, r7
800655c: bc80 pop {r7}
800655e: 4770 bx lr
08006560 <USBD_CDC_SetTxBuffer>:
* @retval status
*/
uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff,
uint16_t length)
{
8006560: b480 push {r7}
8006562: b087 sub sp, #28
8006564: af00 add r7, sp, #0
8006566: 60f8 str r0, [r7, #12]
8006568: 60b9 str r1, [r7, #8]
800656a: 4613 mov r3, r2
800656c: 80fb strh r3, [r7, #6]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800656e: 68fb ldr r3, [r7, #12]
8006570: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006574: 617b str r3, [r7, #20]
hcdc->TxBuffer = pbuff;
8006576: 697b ldr r3, [r7, #20]
8006578: 68ba ldr r2, [r7, #8]
800657a: f8c3 2208 str.w r2, [r3, #520] ; 0x208
hcdc->TxLength = length;
800657e: 88fa ldrh r2, [r7, #6]
8006580: 697b ldr r3, [r7, #20]
8006582: f8c3 2210 str.w r2, [r3, #528] ; 0x210
return USBD_OK;
8006586: 2300 movs r3, #0
}
8006588: 4618 mov r0, r3
800658a: 371c adds r7, #28
800658c: 46bd mov sp, r7
800658e: bc80 pop {r7}
8006590: 4770 bx lr
08006592 <USBD_CDC_SetRxBuffer>:
* @param pbuff: Rx Buffer
* @retval status
*/
uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev,
uint8_t *pbuff)
{
8006592: b480 push {r7}
8006594: b085 sub sp, #20
8006596: af00 add r7, sp, #0
8006598: 6078 str r0, [r7, #4]
800659a: 6039 str r1, [r7, #0]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800659c: 687b ldr r3, [r7, #4]
800659e: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
80065a2: 60fb str r3, [r7, #12]
hcdc->RxBuffer = pbuff;
80065a4: 68fb ldr r3, [r7, #12]
80065a6: 683a ldr r2, [r7, #0]
80065a8: f8c3 2204 str.w r2, [r3, #516] ; 0x204
return USBD_OK;
80065ac: 2300 movs r3, #0
}
80065ae: 4618 mov r0, r3
80065b0: 3714 adds r7, #20
80065b2: 46bd mov sp, r7
80065b4: bc80 pop {r7}
80065b6: 4770 bx lr
080065b8 <USBD_CDC_TransmitPacket>:
* Transmit packet on IN endpoint
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev)
{
80065b8: b580 push {r7, lr}
80065ba: b084 sub sp, #16
80065bc: af00 add r7, sp, #0
80065be: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
80065c0: 687b ldr r3, [r7, #4]
80065c2: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
80065c6: 60fb str r3, [r7, #12]
if (pdev->pClassData != NULL)
80065c8: 687b ldr r3, [r7, #4]
80065ca: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
80065ce: 2b00 cmp r3, #0
80065d0: d01c beq.n 800660c <USBD_CDC_TransmitPacket+0x54>
{
if (hcdc->TxState == 0U)
80065d2: 68fb ldr r3, [r7, #12]
80065d4: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214
80065d8: 2b00 cmp r3, #0
80065da: d115 bne.n 8006608 <USBD_CDC_TransmitPacket+0x50>
{
/* Tx Transfer in progress */
hcdc->TxState = 1U;
80065dc: 68fb ldr r3, [r7, #12]
80065de: 2201 movs r2, #1
80065e0: f8c3 2214 str.w r2, [r3, #532] ; 0x214
/* Update the packet total length */
pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength;
80065e4: 68fb ldr r3, [r7, #12]
80065e6: f8d3 2210 ldr.w r2, [r3, #528] ; 0x210
80065ea: 687b ldr r3, [r7, #4]
80065ec: 631a str r2, [r3, #48] ; 0x30
/* Transmit next packet */
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
80065ee: 68fb ldr r3, [r7, #12]
80065f0: f8d3 2208 ldr.w r2, [r3, #520] ; 0x208
(uint16_t)hcdc->TxLength);
80065f4: 68fb ldr r3, [r7, #12]
80065f6: f8d3 3210 ldr.w r3, [r3, #528] ; 0x210
USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer,
80065fa: b29b uxth r3, r3
80065fc: 2181 movs r1, #129 ; 0x81
80065fe: 6878 ldr r0, [r7, #4]
8006600: f001 fccc bl 8007f9c <USBD_LL_Transmit>
return USBD_OK;
8006604: 2300 movs r3, #0
8006606: e002 b.n 800660e <USBD_CDC_TransmitPacket+0x56>
}
else
{
return USBD_BUSY;
8006608: 2301 movs r3, #1
800660a: e000 b.n 800660e <USBD_CDC_TransmitPacket+0x56>
}
}
else
{
return USBD_FAIL;
800660c: 2302 movs r3, #2
}
}
800660e: 4618 mov r0, r3
8006610: 3710 adds r7, #16
8006612: 46bd mov sp, r7
8006614: bd80 pop {r7, pc}
08006616 <USBD_CDC_ReceivePacket>:
* prepare OUT Endpoint for reception
* @param pdev: device instance
* @retval status
*/
uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev)
{
8006616: b580 push {r7, lr}
8006618: b084 sub sp, #16
800661a: af00 add r7, sp, #0
800661c: 6078 str r0, [r7, #4]
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData;
800661e: 687b ldr r3, [r7, #4]
8006620: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006624: 60fb str r3, [r7, #12]
/* Suspend or Resume USB Out process */
if (pdev->pClassData != NULL)
8006626: 687b ldr r3, [r7, #4]
8006628: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
800662c: 2b00 cmp r3, #0
800662e: d017 beq.n 8006660 <USBD_CDC_ReceivePacket+0x4a>
{
if (pdev->dev_speed == USBD_SPEED_HIGH)
8006630: 687b ldr r3, [r7, #4]
8006632: 7c1b ldrb r3, [r3, #16]
8006634: 2b00 cmp r3, #0
8006636: d109 bne.n 800664c <USBD_CDC_ReceivePacket+0x36>
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
8006638: 68fb ldr r3, [r7, #12]
800663a: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
800663e: f44f 7300 mov.w r3, #512 ; 0x200
8006642: 2101 movs r1, #1
8006644: 6878 ldr r0, [r7, #4]
8006646: f001 fccc bl 8007fe2 <USBD_LL_PrepareReceive>
800664a: e007 b.n 800665c <USBD_CDC_ReceivePacket+0x46>
CDC_DATA_HS_OUT_PACKET_SIZE);
}
else
{
/* Prepare Out endpoint to receive next packet */
USBD_LL_PrepareReceive(pdev,
800664c: 68fb ldr r3, [r7, #12]
800664e: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
8006652: 2340 movs r3, #64 ; 0x40
8006654: 2101 movs r1, #1
8006656: 6878 ldr r0, [r7, #4]
8006658: f001 fcc3 bl 8007fe2 <USBD_LL_PrepareReceive>
CDC_OUT_EP,
hcdc->RxBuffer,
CDC_DATA_FS_OUT_PACKET_SIZE);
}
return USBD_OK;
800665c: 2300 movs r3, #0
800665e: e000 b.n 8006662 <USBD_CDC_ReceivePacket+0x4c>
}
else
{
return USBD_FAIL;
8006660: 2302 movs r3, #2
}
}
8006662: 4618 mov r0, r3
8006664: 3710 adds r7, #16
8006666: 46bd mov sp, r7
8006668: bd80 pop {r7, pc}
0800666a <USBD_Init>:
* @param id: Low level core index
* @retval None
*/
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{
800666a: b580 push {r7, lr}
800666c: b084 sub sp, #16
800666e: af00 add r7, sp, #0
8006670: 60f8 str r0, [r7, #12]
8006672: 60b9 str r1, [r7, #8]
8006674: 4613 mov r3, r2
8006676: 71fb strb r3, [r7, #7]
/* Check whether the USB Host handle is valid */
if (pdev == NULL)
8006678: 68fb ldr r3, [r7, #12]
800667a: 2b00 cmp r3, #0
800667c: d101 bne.n 8006682 <USBD_Init+0x18>
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle");
#endif
return USBD_FAIL;
800667e: 2302 movs r3, #2
8006680: e01a b.n 80066b8 <USBD_Init+0x4e>
}
/* Unlink previous class*/
if (pdev->pClass != NULL)
8006682: 68fb ldr r3, [r7, #12]
8006684: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006688: 2b00 cmp r3, #0
800668a: d003 beq.n 8006694 <USBD_Init+0x2a>
{
pdev->pClass = NULL;
800668c: 68fb ldr r3, [r7, #12]
800668e: 2200 movs r2, #0
8006690: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4
}
/* Assign USBD Descriptors */
if (pdesc != NULL)
8006694: 68bb ldr r3, [r7, #8]
8006696: 2b00 cmp r3, #0
8006698: d003 beq.n 80066a2 <USBD_Init+0x38>
{
pdev->pDesc = pdesc;
800669a: 68fb ldr r3, [r7, #12]
800669c: 68ba ldr r2, [r7, #8]
800669e: f8c3 22b0 str.w r2, [r3, #688] ; 0x2b0
}
/* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT;
80066a2: 68fb ldr r3, [r7, #12]
80066a4: 2201 movs r2, #1
80066a6: f883 229c strb.w r2, [r3, #668] ; 0x29c
pdev->id = id;
80066aa: 68fb ldr r3, [r7, #12]
80066ac: 79fa ldrb r2, [r7, #7]
80066ae: 701a strb r2, [r3, #0]
/* Initialize low level driver */
USBD_LL_Init(pdev);
80066b0: 68f8 ldr r0, [r7, #12]
80066b2: f001 fb37 bl 8007d24 <USBD_LL_Init>
return USBD_OK;
80066b6: 2300 movs r3, #0
}
80066b8: 4618 mov r0, r3
80066ba: 3710 adds r7, #16
80066bc: 46bd mov sp, r7
80066be: bd80 pop {r7, pc}
080066c0 <USBD_RegisterClass>:
* @param pDevice : Device Handle
* @param pclass: Class handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{
80066c0: b480 push {r7}
80066c2: b085 sub sp, #20
80066c4: af00 add r7, sp, #0
80066c6: 6078 str r0, [r7, #4]
80066c8: 6039 str r1, [r7, #0]
USBD_StatusTypeDef status = USBD_OK;
80066ca: 2300 movs r3, #0
80066cc: 73fb strb r3, [r7, #15]
if (pclass != NULL)
80066ce: 683b ldr r3, [r7, #0]
80066d0: 2b00 cmp r3, #0
80066d2: d006 beq.n 80066e2 <USBD_RegisterClass+0x22>
{
/* link the class to the USB Device handle */
pdev->pClass = pclass;
80066d4: 687b ldr r3, [r7, #4]
80066d6: 683a ldr r2, [r7, #0]
80066d8: f8c3 22b4 str.w r2, [r3, #692] ; 0x2b4
status = USBD_OK;
80066dc: 2300 movs r3, #0
80066de: 73fb strb r3, [r7, #15]
80066e0: e001 b.n 80066e6 <USBD_RegisterClass+0x26>
else
{
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle");
#endif
status = USBD_FAIL;
80066e2: 2302 movs r3, #2
80066e4: 73fb strb r3, [r7, #15]
}
return status;
80066e6: 7bfb ldrb r3, [r7, #15]
}
80066e8: 4618 mov r0, r3
80066ea: 3714 adds r7, #20
80066ec: 46bd mov sp, r7
80066ee: bc80 pop {r7}
80066f0: 4770 bx lr
080066f2 <USBD_Start>:
* Start the USB Device Core.
* @param pdev: Device Handle
* @retval USBD Status
*/
USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{
80066f2: b580 push {r7, lr}
80066f4: b082 sub sp, #8
80066f6: af00 add r7, sp, #0
80066f8: 6078 str r0, [r7, #4]
/* Start the low level driver */
USBD_LL_Start(pdev);
80066fa: 6878 ldr r0, [r7, #4]
80066fc: f001 fb6c bl 8007dd8 <USBD_LL_Start>
return USBD_OK;
8006700: 2300 movs r3, #0
}
8006702: 4618 mov r0, r3
8006704: 3708 adds r7, #8
8006706: 46bd mov sp, r7
8006708: bd80 pop {r7, pc}
0800670a <USBD_RunTestMode>:
* Launch test mode process
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{
800670a: b480 push {r7}
800670c: b083 sub sp, #12
800670e: af00 add r7, sp, #0
8006710: 6078 str r0, [r7, #4]
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK;
8006712: 2300 movs r3, #0
}
8006714: 4618 mov r0, r3
8006716: 370c adds r7, #12
8006718: 46bd mov sp, r7
800671a: bc80 pop {r7}
800671c: 4770 bx lr
0800671e <USBD_SetClassConfig>:
* @param cfgidx: configuration index
* @retval status
*/
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800671e: b580 push {r7, lr}
8006720: b084 sub sp, #16
8006722: af00 add r7, sp, #0
8006724: 6078 str r0, [r7, #4]
8006726: 460b mov r3, r1
8006728: 70fb strb r3, [r7, #3]
USBD_StatusTypeDef ret = USBD_FAIL;
800672a: 2302 movs r3, #2
800672c: 73fb strb r3, [r7, #15]
if (pdev->pClass != NULL)
800672e: 687b ldr r3, [r7, #4]
8006730: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006734: 2b00 cmp r3, #0
8006736: d00c beq.n 8006752 <USBD_SetClassConfig+0x34>
{
/* Set configuration and Start the Class*/
if (pdev->pClass->Init(pdev, cfgidx) == 0U)
8006738: 687b ldr r3, [r7, #4]
800673a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
800673e: 681b ldr r3, [r3, #0]
8006740: 78fa ldrb r2, [r7, #3]
8006742: 4611 mov r1, r2
8006744: 6878 ldr r0, [r7, #4]
8006746: 4798 blx r3
8006748: 4603 mov r3, r0
800674a: 2b00 cmp r3, #0
800674c: d101 bne.n 8006752 <USBD_SetClassConfig+0x34>
{
ret = USBD_OK;
800674e: 2300 movs r3, #0
8006750: 73fb strb r3, [r7, #15]
}
}
return ret;
8006752: 7bfb ldrb r3, [r7, #15]
}
8006754: 4618 mov r0, r3
8006756: 3710 adds r7, #16
8006758: 46bd mov sp, r7
800675a: bd80 pop {r7, pc}
0800675c <USBD_ClrClassConfig>:
* @param pdev: device instance
* @param cfgidx: configuration index
* @retval status: USBD_StatusTypeDef
*/
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{
800675c: b580 push {r7, lr}
800675e: b082 sub sp, #8
8006760: af00 add r7, sp, #0
8006762: 6078 str r0, [r7, #4]
8006764: 460b mov r3, r1
8006766: 70fb strb r3, [r7, #3]
/* Clear configuration and De-initialize the Class process*/
pdev->pClass->DeInit(pdev, cfgidx);
8006768: 687b ldr r3, [r7, #4]
800676a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
800676e: 685b ldr r3, [r3, #4]
8006770: 78fa ldrb r2, [r7, #3]
8006772: 4611 mov r1, r2
8006774: 6878 ldr r0, [r7, #4]
8006776: 4798 blx r3
return USBD_OK;
8006778: 2300 movs r3, #0
}
800677a: 4618 mov r0, r3
800677c: 3708 adds r7, #8
800677e: 46bd mov sp, r7
8006780: bd80 pop {r7, pc}
08006782 <USBD_LL_SetupStage>:
* Handle the setup stage
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{
8006782: b580 push {r7, lr}
8006784: b082 sub sp, #8
8006786: af00 add r7, sp, #0
8006788: 6078 str r0, [r7, #4]
800678a: 6039 str r1, [r7, #0]
USBD_ParseSetupRequest(&pdev->request, psetup);
800678c: 687b ldr r3, [r7, #4]
800678e: f503 732a add.w r3, r3, #680 ; 0x2a8
8006792: 6839 ldr r1, [r7, #0]
8006794: 4618 mov r0, r3
8006796: f000 fecb bl 8007530 <USBD_ParseSetupRequest>
pdev->ep0_state = USBD_EP0_SETUP;
800679a: 687b ldr r3, [r7, #4]
800679c: 2201 movs r2, #1
800679e: f8c3 2294 str.w r2, [r3, #660] ; 0x294
pdev->ep0_data_len = pdev->request.wLength;
80067a2: 687b ldr r3, [r7, #4]
80067a4: f8b3 32ae ldrh.w r3, [r3, #686] ; 0x2ae
80067a8: 461a mov r2, r3
80067aa: 687b ldr r3, [r7, #4]
80067ac: f8c3 2298 str.w r2, [r3, #664] ; 0x298
switch (pdev->request.bmRequest & 0x1FU)
80067b0: 687b ldr r3, [r7, #4]
80067b2: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8
80067b6: f003 031f and.w r3, r3, #31
80067ba: 2b01 cmp r3, #1
80067bc: d00c beq.n 80067d8 <USBD_LL_SetupStage+0x56>
80067be: 2b01 cmp r3, #1
80067c0: d302 bcc.n 80067c8 <USBD_LL_SetupStage+0x46>
80067c2: 2b02 cmp r3, #2
80067c4: d010 beq.n 80067e8 <USBD_LL_SetupStage+0x66>
80067c6: e017 b.n 80067f8 <USBD_LL_SetupStage+0x76>
{
case USB_REQ_RECIPIENT_DEVICE:
USBD_StdDevReq(pdev, &pdev->request);
80067c8: 687b ldr r3, [r7, #4]
80067ca: f503 732a add.w r3, r3, #680 ; 0x2a8
80067ce: 4619 mov r1, r3
80067d0: 6878 ldr r0, [r7, #4]
80067d2: f000 f9cb bl 8006b6c <USBD_StdDevReq>
break;
80067d6: e01a b.n 800680e <USBD_LL_SetupStage+0x8c>
case USB_REQ_RECIPIENT_INTERFACE:
USBD_StdItfReq(pdev, &pdev->request);
80067d8: 687b ldr r3, [r7, #4]
80067da: f503 732a add.w r3, r3, #680 ; 0x2a8
80067de: 4619 mov r1, r3
80067e0: 6878 ldr r0, [r7, #4]
80067e2: f000 fa2d bl 8006c40 <USBD_StdItfReq>
break;
80067e6: e012 b.n 800680e <USBD_LL_SetupStage+0x8c>
case USB_REQ_RECIPIENT_ENDPOINT:
USBD_StdEPReq(pdev, &pdev->request);
80067e8: 687b ldr r3, [r7, #4]
80067ea: f503 732a add.w r3, r3, #680 ; 0x2a8
80067ee: 4619 mov r1, r3
80067f0: 6878 ldr r0, [r7, #4]
80067f2: f000 fa6b bl 8006ccc <USBD_StdEPReq>
break;
80067f6: e00a b.n 800680e <USBD_LL_SetupStage+0x8c>
default:
USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
80067f8: 687b ldr r3, [r7, #4]
80067fa: f893 32a8 ldrb.w r3, [r3, #680] ; 0x2a8
80067fe: f023 037f bic.w r3, r3, #127 ; 0x7f
8006802: b2db uxtb r3, r3
8006804: 4619 mov r1, r3
8006806: 6878 ldr r0, [r7, #4]
8006808: f001 fb46 bl 8007e98 <USBD_LL_StallEP>
break;
800680c: bf00 nop
}
return USBD_OK;
800680e: 2300 movs r3, #0
}
8006810: 4618 mov r0, r3
8006812: 3708 adds r7, #8
8006814: 46bd mov sp, r7
8006816: bd80 pop {r7, pc}
08006818 <USBD_LL_DataOutStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
8006818: b580 push {r7, lr}
800681a: b086 sub sp, #24
800681c: af00 add r7, sp, #0
800681e: 60f8 str r0, [r7, #12]
8006820: 460b mov r3, r1
8006822: 607a str r2, [r7, #4]
8006824: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
8006826: 7afb ldrb r3, [r7, #11]
8006828: 2b00 cmp r3, #0
800682a: d14b bne.n 80068c4 <USBD_LL_DataOutStage+0xac>
{
pep = &pdev->ep_out[0];
800682c: 68fb ldr r3, [r7, #12]
800682e: f503 73aa add.w r3, r3, #340 ; 0x154
8006832: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_OUT)
8006834: 68fb ldr r3, [r7, #12]
8006836: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294
800683a: 2b03 cmp r3, #3
800683c: d134 bne.n 80068a8 <USBD_LL_DataOutStage+0x90>
{
if (pep->rem_length > pep->maxpacket)
800683e: 697b ldr r3, [r7, #20]
8006840: 68da ldr r2, [r3, #12]
8006842: 697b ldr r3, [r7, #20]
8006844: 691b ldr r3, [r3, #16]
8006846: 429a cmp r2, r3
8006848: d919 bls.n 800687e <USBD_LL_DataOutStage+0x66>
{
pep->rem_length -= pep->maxpacket;
800684a: 697b ldr r3, [r7, #20]
800684c: 68da ldr r2, [r3, #12]
800684e: 697b ldr r3, [r7, #20]
8006850: 691b ldr r3, [r3, #16]
8006852: 1ad2 subs r2, r2, r3
8006854: 697b ldr r3, [r7, #20]
8006856: 60da str r2, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
8006858: 697b ldr r3, [r7, #20]
800685a: 68da ldr r2, [r3, #12]
800685c: 697b ldr r3, [r7, #20]
800685e: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
8006860: 429a cmp r2, r3
8006862: d203 bcs.n 800686c <USBD_LL_DataOutStage+0x54>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
8006864: 697b ldr r3, [r7, #20]
8006866: 68db ldr r3, [r3, #12]
USBD_CtlContinueRx(pdev, pdata,
8006868: b29b uxth r3, r3
800686a: e002 b.n 8006872 <USBD_LL_DataOutStage+0x5a>
(uint16_t)MIN(pep->rem_length, pep->maxpacket));
800686c: 697b ldr r3, [r7, #20]
800686e: 691b ldr r3, [r3, #16]
USBD_CtlContinueRx(pdev, pdata,
8006870: b29b uxth r3, r3
8006872: 461a mov r2, r3
8006874: 6879 ldr r1, [r7, #4]
8006876: 68f8 ldr r0, [r7, #12]
8006878: f000 ff4c bl 8007714 <USBD_CtlContinueRx>
800687c: e038 b.n 80068f0 <USBD_LL_DataOutStage+0xd8>
}
else
{
if ((pdev->pClass->EP0_RxReady != NULL) &&
800687e: 68fb ldr r3, [r7, #12]
8006880: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006884: 691b ldr r3, [r3, #16]
8006886: 2b00 cmp r3, #0
8006888: d00a beq.n 80068a0 <USBD_LL_DataOutStage+0x88>
(pdev->dev_state == USBD_STATE_CONFIGURED))
800688a: 68fb ldr r3, [r7, #12]
800688c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
if ((pdev->pClass->EP0_RxReady != NULL) &&
8006890: 2b03 cmp r3, #3
8006892: d105 bne.n 80068a0 <USBD_LL_DataOutStage+0x88>
{
pdev->pClass->EP0_RxReady(pdev);
8006894: 68fb ldr r3, [r7, #12]
8006896: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
800689a: 691b ldr r3, [r3, #16]
800689c: 68f8 ldr r0, [r7, #12]
800689e: 4798 blx r3
}
USBD_CtlSendStatus(pdev);
80068a0: 68f8 ldr r0, [r7, #12]
80068a2: f000 ff49 bl 8007738 <USBD_CtlSendStatus>
80068a6: e023 b.n 80068f0 <USBD_LL_DataOutStage+0xd8>
}
}
else
{
if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
80068a8: 68fb ldr r3, [r7, #12]
80068aa: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294
80068ae: 2b05 cmp r3, #5
80068b0: d11e bne.n 80068f0 <USBD_LL_DataOutStage+0xd8>
{
/*
* STATUS PHASE completed, update ep0_state to idle
*/
pdev->ep0_state = USBD_EP0_IDLE;
80068b2: 68fb ldr r3, [r7, #12]
80068b4: 2200 movs r2, #0
80068b6: f8c3 2294 str.w r2, [r3, #660] ; 0x294
USBD_LL_StallEP(pdev, 0U);
80068ba: 2100 movs r1, #0
80068bc: 68f8 ldr r0, [r7, #12]
80068be: f001 faeb bl 8007e98 <USBD_LL_StallEP>
80068c2: e015 b.n 80068f0 <USBD_LL_DataOutStage+0xd8>
}
}
}
else if ((pdev->pClass->DataOut != NULL) &&
80068c4: 68fb ldr r3, [r7, #12]
80068c6: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
80068ca: 699b ldr r3, [r3, #24]
80068cc: 2b00 cmp r3, #0
80068ce: d00d beq.n 80068ec <USBD_LL_DataOutStage+0xd4>
(pdev->dev_state == USBD_STATE_CONFIGURED))
80068d0: 68fb ldr r3, [r7, #12]
80068d2: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
else if ((pdev->pClass->DataOut != NULL) &&
80068d6: 2b03 cmp r3, #3
80068d8: d108 bne.n 80068ec <USBD_LL_DataOutStage+0xd4>
{
pdev->pClass->DataOut(pdev, epnum);
80068da: 68fb ldr r3, [r7, #12]
80068dc: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
80068e0: 699b ldr r3, [r3, #24]
80068e2: 7afa ldrb r2, [r7, #11]
80068e4: 4611 mov r1, r2
80068e6: 68f8 ldr r0, [r7, #12]
80068e8: 4798 blx r3
80068ea: e001 b.n 80068f0 <USBD_LL_DataOutStage+0xd8>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
80068ec: 2302 movs r3, #2
80068ee: e000 b.n 80068f2 <USBD_LL_DataOutStage+0xda>
}
return USBD_OK;
80068f0: 2300 movs r3, #0
}
80068f2: 4618 mov r0, r3
80068f4: 3718 adds r7, #24
80068f6: 46bd mov sp, r7
80068f8: bd80 pop {r7, pc}
080068fa <USBD_LL_DataInStage>:
* @param epnum: endpoint index
* @retval status
*/
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{
80068fa: b580 push {r7, lr}
80068fc: b086 sub sp, #24
80068fe: af00 add r7, sp, #0
8006900: 60f8 str r0, [r7, #12]
8006902: 460b mov r3, r1
8006904: 607a str r2, [r7, #4]
8006906: 72fb strb r3, [r7, #11]
USBD_EndpointTypeDef *pep;
if (epnum == 0U)
8006908: 7afb ldrb r3, [r7, #11]
800690a: 2b00 cmp r3, #0
800690c: d17f bne.n 8006a0e <USBD_LL_DataInStage+0x114>
{
pep = &pdev->ep_in[0];
800690e: 68fb ldr r3, [r7, #12]
8006910: 3314 adds r3, #20
8006912: 617b str r3, [r7, #20]
if (pdev->ep0_state == USBD_EP0_DATA_IN)
8006914: 68fb ldr r3, [r7, #12]
8006916: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294
800691a: 2b02 cmp r3, #2
800691c: d15c bne.n 80069d8 <USBD_LL_DataInStage+0xde>
{
if (pep->rem_length > pep->maxpacket)
800691e: 697b ldr r3, [r7, #20]
8006920: 68da ldr r2, [r3, #12]
8006922: 697b ldr r3, [r7, #20]
8006924: 691b ldr r3, [r3, #16]
8006926: 429a cmp r2, r3
8006928: d915 bls.n 8006956 <USBD_LL_DataInStage+0x5c>
{
pep->rem_length -= pep->maxpacket;
800692a: 697b ldr r3, [r7, #20]
800692c: 68da ldr r2, [r3, #12]
800692e: 697b ldr r3, [r7, #20]
8006930: 691b ldr r3, [r3, #16]
8006932: 1ad2 subs r2, r2, r3
8006934: 697b ldr r3, [r7, #20]
8006936: 60da str r2, [r3, #12]
USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
8006938: 697b ldr r3, [r7, #20]
800693a: 68db ldr r3, [r3, #12]
800693c: b29b uxth r3, r3
800693e: 461a mov r2, r3
8006940: 6879 ldr r1, [r7, #4]
8006942: 68f8 ldr r0, [r7, #12]
8006944: f000 feb6 bl 80076b4 <USBD_CtlContinueSendData>
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8006948: 2300 movs r3, #0
800694a: 2200 movs r2, #0
800694c: 2100 movs r1, #0
800694e: 68f8 ldr r0, [r7, #12]
8006950: f001 fb47 bl 8007fe2 <USBD_LL_PrepareReceive>
8006954: e04e b.n 80069f4 <USBD_LL_DataInStage+0xfa>
}
else
{
/* last packet is MPS multiple, so send ZLP packet */
if ((pep->total_length % pep->maxpacket == 0U) &&
8006956: 697b ldr r3, [r7, #20]
8006958: 689b ldr r3, [r3, #8]
800695a: 697a ldr r2, [r7, #20]
800695c: 6912 ldr r2, [r2, #16]
800695e: fbb3 f1f2 udiv r1, r3, r2
8006962: fb02 f201 mul.w r2, r2, r1
8006966: 1a9b subs r3, r3, r2
8006968: 2b00 cmp r3, #0
800696a: d11c bne.n 80069a6 <USBD_LL_DataInStage+0xac>
(pep->total_length >= pep->maxpacket) &&
800696c: 697b ldr r3, [r7, #20]
800696e: 689a ldr r2, [r3, #8]
8006970: 697b ldr r3, [r7, #20]
8006972: 691b ldr r3, [r3, #16]
if ((pep->total_length % pep->maxpacket == 0U) &&
8006974: 429a cmp r2, r3
8006976: d316 bcc.n 80069a6 <USBD_LL_DataInStage+0xac>
(pep->total_length < pdev->ep0_data_len))
8006978: 697b ldr r3, [r7, #20]
800697a: 689a ldr r2, [r3, #8]
800697c: 68fb ldr r3, [r7, #12]
800697e: f8d3 3298 ldr.w r3, [r3, #664] ; 0x298
(pep->total_length >= pep->maxpacket) &&
8006982: 429a cmp r2, r3
8006984: d20f bcs.n 80069a6 <USBD_LL_DataInStage+0xac>
{
USBD_CtlContinueSendData(pdev, NULL, 0U);
8006986: 2200 movs r2, #0
8006988: 2100 movs r1, #0
800698a: 68f8 ldr r0, [r7, #12]
800698c: f000 fe92 bl 80076b4 <USBD_CtlContinueSendData>
pdev->ep0_data_len = 0U;
8006990: 68fb ldr r3, [r7, #12]
8006992: 2200 movs r2, #0
8006994: f8c3 2298 str.w r2, [r3, #664] ; 0x298
/* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
8006998: 2300 movs r3, #0
800699a: 2200 movs r2, #0
800699c: 2100 movs r1, #0
800699e: 68f8 ldr r0, [r7, #12]
80069a0: f001 fb1f bl 8007fe2 <USBD_LL_PrepareReceive>
80069a4: e026 b.n 80069f4 <USBD_LL_DataInStage+0xfa>
}
else
{
if ((pdev->pClass->EP0_TxSent != NULL) &&
80069a6: 68fb ldr r3, [r7, #12]
80069a8: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
80069ac: 68db ldr r3, [r3, #12]
80069ae: 2b00 cmp r3, #0
80069b0: d00a beq.n 80069c8 <USBD_LL_DataInStage+0xce>
(pdev->dev_state == USBD_STATE_CONFIGURED))
80069b2: 68fb ldr r3, [r7, #12]
80069b4: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
if ((pdev->pClass->EP0_TxSent != NULL) &&
80069b8: 2b03 cmp r3, #3
80069ba: d105 bne.n 80069c8 <USBD_LL_DataInStage+0xce>
{
pdev->pClass->EP0_TxSent(pdev);
80069bc: 68fb ldr r3, [r7, #12]
80069be: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
80069c2: 68db ldr r3, [r3, #12]
80069c4: 68f8 ldr r0, [r7, #12]
80069c6: 4798 blx r3
}
USBD_LL_StallEP(pdev, 0x80U);
80069c8: 2180 movs r1, #128 ; 0x80
80069ca: 68f8 ldr r0, [r7, #12]
80069cc: f001 fa64 bl 8007e98 <USBD_LL_StallEP>
USBD_CtlReceiveStatus(pdev);
80069d0: 68f8 ldr r0, [r7, #12]
80069d2: f000 fec4 bl 800775e <USBD_CtlReceiveStatus>
80069d6: e00d b.n 80069f4 <USBD_LL_DataInStage+0xfa>
}
}
}
else
{
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
80069d8: 68fb ldr r3, [r7, #12]
80069da: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294
80069de: 2b04 cmp r3, #4
80069e0: d004 beq.n 80069ec <USBD_LL_DataInStage+0xf2>
(pdev->ep0_state == USBD_EP0_IDLE))
80069e2: 68fb ldr r3, [r7, #12]
80069e4: f8d3 3294 ldr.w r3, [r3, #660] ; 0x294
if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
80069e8: 2b00 cmp r3, #0
80069ea: d103 bne.n 80069f4 <USBD_LL_DataInStage+0xfa>
{
USBD_LL_StallEP(pdev, 0x80U);
80069ec: 2180 movs r1, #128 ; 0x80
80069ee: 68f8 ldr r0, [r7, #12]
80069f0: f001 fa52 bl 8007e98 <USBD_LL_StallEP>
}
}
if (pdev->dev_test_mode == 1U)
80069f4: 68fb ldr r3, [r7, #12]
80069f6: f893 32a0 ldrb.w r3, [r3, #672] ; 0x2a0
80069fa: 2b01 cmp r3, #1
80069fc: d11d bne.n 8006a3a <USBD_LL_DataInStage+0x140>
{
USBD_RunTestMode(pdev);
80069fe: 68f8 ldr r0, [r7, #12]
8006a00: f7ff fe83 bl 800670a <USBD_RunTestMode>
pdev->dev_test_mode = 0U;
8006a04: 68fb ldr r3, [r7, #12]
8006a06: 2200 movs r2, #0
8006a08: f883 22a0 strb.w r2, [r3, #672] ; 0x2a0
8006a0c: e015 b.n 8006a3a <USBD_LL_DataInStage+0x140>
}
}
else if ((pdev->pClass->DataIn != NULL) &&
8006a0e: 68fb ldr r3, [r7, #12]
8006a10: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006a14: 695b ldr r3, [r3, #20]
8006a16: 2b00 cmp r3, #0
8006a18: d00d beq.n 8006a36 <USBD_LL_DataInStage+0x13c>
(pdev->dev_state == USBD_STATE_CONFIGURED))
8006a1a: 68fb ldr r3, [r7, #12]
8006a1c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
else if ((pdev->pClass->DataIn != NULL) &&
8006a20: 2b03 cmp r3, #3
8006a22: d108 bne.n 8006a36 <USBD_LL_DataInStage+0x13c>
{
pdev->pClass->DataIn(pdev, epnum);
8006a24: 68fb ldr r3, [r7, #12]
8006a26: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006a2a: 695b ldr r3, [r3, #20]
8006a2c: 7afa ldrb r2, [r7, #11]
8006a2e: 4611 mov r1, r2
8006a30: 68f8 ldr r0, [r7, #12]
8006a32: 4798 blx r3
8006a34: e001 b.n 8006a3a <USBD_LL_DataInStage+0x140>
}
else
{
/* should never be in this condition */
return USBD_FAIL;
8006a36: 2302 movs r3, #2
8006a38: e000 b.n 8006a3c <USBD_LL_DataInStage+0x142>
}
return USBD_OK;
8006a3a: 2300 movs r3, #0
}
8006a3c: 4618 mov r0, r3
8006a3e: 3718 adds r7, #24
8006a40: 46bd mov sp, r7
8006a42: bd80 pop {r7, pc}
08006a44 <USBD_LL_Reset>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{
8006a44: b580 push {r7, lr}
8006a46: b082 sub sp, #8
8006a48: af00 add r7, sp, #0
8006a4a: 6078 str r0, [r7, #4]
/* Open EP0 OUT */
USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8006a4c: 2340 movs r3, #64 ; 0x40
8006a4e: 2200 movs r2, #0
8006a50: 2100 movs r1, #0
8006a52: 6878 ldr r0, [r7, #4]
8006a54: f001 f9db bl 8007e0e <USBD_LL_OpenEP>
pdev->ep_out[0x00U & 0xFU].is_used = 1U;
8006a58: 687b ldr r3, [r7, #4]
8006a5a: 2201 movs r2, #1
8006a5c: f8c3 2158 str.w r2, [r3, #344] ; 0x158
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
8006a60: 687b ldr r3, [r7, #4]
8006a62: 2240 movs r2, #64 ; 0x40
8006a64: f8c3 2164 str.w r2, [r3, #356] ; 0x164
/* Open EP0 IN */
USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
8006a68: 2340 movs r3, #64 ; 0x40
8006a6a: 2200 movs r2, #0
8006a6c: 2180 movs r1, #128 ; 0x80
8006a6e: 6878 ldr r0, [r7, #4]
8006a70: f001 f9cd bl 8007e0e <USBD_LL_OpenEP>
pdev->ep_in[0x80U & 0xFU].is_used = 1U;
8006a74: 687b ldr r3, [r7, #4]
8006a76: 2201 movs r2, #1
8006a78: 619a str r2, [r3, #24]
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
8006a7a: 687b ldr r3, [r7, #4]
8006a7c: 2240 movs r2, #64 ; 0x40
8006a7e: 625a str r2, [r3, #36] ; 0x24
/* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT;
8006a80: 687b ldr r3, [r7, #4]
8006a82: 2201 movs r2, #1
8006a84: f883 229c strb.w r2, [r3, #668] ; 0x29c
pdev->ep0_state = USBD_EP0_IDLE;
8006a88: 687b ldr r3, [r7, #4]
8006a8a: 2200 movs r2, #0
8006a8c: f8c3 2294 str.w r2, [r3, #660] ; 0x294
pdev->dev_config = 0U;
8006a90: 687b ldr r3, [r7, #4]
8006a92: 2200 movs r2, #0
8006a94: 605a str r2, [r3, #4]
pdev->dev_remote_wakeup = 0U;
8006a96: 687b ldr r3, [r7, #4]
8006a98: 2200 movs r2, #0
8006a9a: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4
if (pdev->pClassData)
8006a9e: 687b ldr r3, [r7, #4]
8006aa0: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
8006aa4: 2b00 cmp r3, #0
8006aa6: d009 beq.n 8006abc <USBD_LL_Reset+0x78>
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
8006aa8: 687b ldr r3, [r7, #4]
8006aaa: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006aae: 685b ldr r3, [r3, #4]
8006ab0: 687a ldr r2, [r7, #4]
8006ab2: 6852 ldr r2, [r2, #4]
8006ab4: b2d2 uxtb r2, r2
8006ab6: 4611 mov r1, r2
8006ab8: 6878 ldr r0, [r7, #4]
8006aba: 4798 blx r3
}
return USBD_OK;
8006abc: 2300 movs r3, #0
}
8006abe: 4618 mov r0, r3
8006ac0: 3708 adds r7, #8
8006ac2: 46bd mov sp, r7
8006ac4: bd80 pop {r7, pc}
08006ac6 <USBD_LL_SetSpeed>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{
8006ac6: b480 push {r7}
8006ac8: b083 sub sp, #12
8006aca: af00 add r7, sp, #0
8006acc: 6078 str r0, [r7, #4]
8006ace: 460b mov r3, r1
8006ad0: 70fb strb r3, [r7, #3]
pdev->dev_speed = speed;
8006ad2: 687b ldr r3, [r7, #4]
8006ad4: 78fa ldrb r2, [r7, #3]
8006ad6: 741a strb r2, [r3, #16]
return USBD_OK;
8006ad8: 2300 movs r3, #0
}
8006ada: 4618 mov r0, r3
8006adc: 370c adds r7, #12
8006ade: 46bd mov sp, r7
8006ae0: bc80 pop {r7}
8006ae2: 4770 bx lr
08006ae4 <USBD_LL_Suspend>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{
8006ae4: b480 push {r7}
8006ae6: b083 sub sp, #12
8006ae8: af00 add r7, sp, #0
8006aea: 6078 str r0, [r7, #4]
pdev->dev_old_state = pdev->dev_state;
8006aec: 687b ldr r3, [r7, #4]
8006aee: f893 229c ldrb.w r2, [r3, #668] ; 0x29c
8006af2: 687b ldr r3, [r7, #4]
8006af4: f883 229d strb.w r2, [r3, #669] ; 0x29d
pdev->dev_state = USBD_STATE_SUSPENDED;
8006af8: 687b ldr r3, [r7, #4]
8006afa: 2204 movs r2, #4
8006afc: f883 229c strb.w r2, [r3, #668] ; 0x29c
return USBD_OK;
8006b00: 2300 movs r3, #0
}
8006b02: 4618 mov r0, r3
8006b04: 370c adds r7, #12
8006b06: 46bd mov sp, r7
8006b08: bc80 pop {r7}
8006b0a: 4770 bx lr
08006b0c <USBD_LL_Resume>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{
8006b0c: b480 push {r7}
8006b0e: b083 sub sp, #12
8006b10: af00 add r7, sp, #0
8006b12: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_SUSPENDED)
8006b14: 687b ldr r3, [r7, #4]
8006b16: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8006b1a: 2b04 cmp r3, #4
8006b1c: d105 bne.n 8006b2a <USBD_LL_Resume+0x1e>
{
pdev->dev_state = pdev->dev_old_state;
8006b1e: 687b ldr r3, [r7, #4]
8006b20: f893 229d ldrb.w r2, [r3, #669] ; 0x29d
8006b24: 687b ldr r3, [r7, #4]
8006b26: f883 229c strb.w r2, [r3, #668] ; 0x29c
}
return USBD_OK;
8006b2a: 2300 movs r3, #0
}
8006b2c: 4618 mov r0, r3
8006b2e: 370c adds r7, #12
8006b30: 46bd mov sp, r7
8006b32: bc80 pop {r7}
8006b34: 4770 bx lr
08006b36 <USBD_LL_SOF>:
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{
8006b36: b580 push {r7, lr}
8006b38: b082 sub sp, #8
8006b3a: af00 add r7, sp, #0
8006b3c: 6078 str r0, [r7, #4]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8006b3e: 687b ldr r3, [r7, #4]
8006b40: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8006b44: 2b03 cmp r3, #3
8006b46: d10b bne.n 8006b60 <USBD_LL_SOF+0x2a>
{
if (pdev->pClass->SOF != NULL)
8006b48: 687b ldr r3, [r7, #4]
8006b4a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006b4e: 69db ldr r3, [r3, #28]
8006b50: 2b00 cmp r3, #0
8006b52: d005 beq.n 8006b60 <USBD_LL_SOF+0x2a>
{
pdev->pClass->SOF(pdev);
8006b54: 687b ldr r3, [r7, #4]
8006b56: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006b5a: 69db ldr r3, [r3, #28]
8006b5c: 6878 ldr r0, [r7, #4]
8006b5e: 4798 blx r3
}
}
return USBD_OK;
8006b60: 2300 movs r3, #0
}
8006b62: 4618 mov r0, r3
8006b64: 3708 adds r7, #8
8006b66: 46bd mov sp, r7
8006b68: bd80 pop {r7, pc}
...
08006b6c <USBD_StdDevReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8006b6c: b580 push {r7, lr}
8006b6e: b084 sub sp, #16
8006b70: af00 add r7, sp, #0
8006b72: 6078 str r0, [r7, #4]
8006b74: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8006b76: 2300 movs r3, #0
8006b78: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8006b7a: 683b ldr r3, [r7, #0]
8006b7c: 781b ldrb r3, [r3, #0]
8006b7e: f003 0360 and.w r3, r3, #96 ; 0x60
8006b82: 2b20 cmp r3, #32
8006b84: d004 beq.n 8006b90 <USBD_StdDevReq+0x24>
8006b86: 2b40 cmp r3, #64 ; 0x40
8006b88: d002 beq.n 8006b90 <USBD_StdDevReq+0x24>
8006b8a: 2b00 cmp r3, #0
8006b8c: d008 beq.n 8006ba0 <USBD_StdDevReq+0x34>
8006b8e: e04c b.n 8006c2a <USBD_StdDevReq+0xbe>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
8006b90: 687b ldr r3, [r7, #4]
8006b92: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006b96: 689b ldr r3, [r3, #8]
8006b98: 6839 ldr r1, [r7, #0]
8006b9a: 6878 ldr r0, [r7, #4]
8006b9c: 4798 blx r3
break;
8006b9e: e049 b.n 8006c34 <USBD_StdDevReq+0xc8>
case USB_REQ_TYPE_STANDARD:
switch (req->bRequest)
8006ba0: 683b ldr r3, [r7, #0]
8006ba2: 785b ldrb r3, [r3, #1]
8006ba4: 2b09 cmp r3, #9
8006ba6: d83a bhi.n 8006c1e <USBD_StdDevReq+0xb2>
8006ba8: a201 add r2, pc, #4 ; (adr r2, 8006bb0 <USBD_StdDevReq+0x44>)
8006baa: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006bae: bf00 nop
8006bb0: 08006c01 .word 0x08006c01
8006bb4: 08006c15 .word 0x08006c15
8006bb8: 08006c1f .word 0x08006c1f
8006bbc: 08006c0b .word 0x08006c0b
8006bc0: 08006c1f .word 0x08006c1f
8006bc4: 08006be3 .word 0x08006be3
8006bc8: 08006bd9 .word 0x08006bd9
8006bcc: 08006c1f .word 0x08006c1f
8006bd0: 08006bf7 .word 0x08006bf7
8006bd4: 08006bed .word 0x08006bed
{
case USB_REQ_GET_DESCRIPTOR:
USBD_GetDescriptor(pdev, req);
8006bd8: 6839 ldr r1, [r7, #0]
8006bda: 6878 ldr r0, [r7, #4]
8006bdc: f000 f9d4 bl 8006f88 <USBD_GetDescriptor>
break;
8006be0: e022 b.n 8006c28 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_ADDRESS:
USBD_SetAddress(pdev, req);
8006be2: 6839 ldr r1, [r7, #0]
8006be4: 6878 ldr r0, [r7, #4]
8006be6: f000 fb37 bl 8007258 <USBD_SetAddress>
break;
8006bea: e01d b.n 8006c28 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_CONFIGURATION:
USBD_SetConfig(pdev, req);
8006bec: 6839 ldr r1, [r7, #0]
8006bee: 6878 ldr r0, [r7, #4]
8006bf0: f000 fb74 bl 80072dc <USBD_SetConfig>
break;
8006bf4: e018 b.n 8006c28 <USBD_StdDevReq+0xbc>
case USB_REQ_GET_CONFIGURATION:
USBD_GetConfig(pdev, req);
8006bf6: 6839 ldr r1, [r7, #0]
8006bf8: 6878 ldr r0, [r7, #4]
8006bfa: f000 fbfd bl 80073f8 <USBD_GetConfig>
break;
8006bfe: e013 b.n 8006c28 <USBD_StdDevReq+0xbc>
case USB_REQ_GET_STATUS:
USBD_GetStatus(pdev, req);
8006c00: 6839 ldr r1, [r7, #0]
8006c02: 6878 ldr r0, [r7, #4]
8006c04: f000 fc2c bl 8007460 <USBD_GetStatus>
break;
8006c08: e00e b.n 8006c28 <USBD_StdDevReq+0xbc>
case USB_REQ_SET_FEATURE:
USBD_SetFeature(pdev, req);
8006c0a: 6839 ldr r1, [r7, #0]
8006c0c: 6878 ldr r0, [r7, #4]
8006c0e: f000 fc5a bl 80074c6 <USBD_SetFeature>
break;
8006c12: e009 b.n 8006c28 <USBD_StdDevReq+0xbc>
case USB_REQ_CLEAR_FEATURE:
USBD_ClrFeature(pdev, req);
8006c14: 6839 ldr r1, [r7, #0]
8006c16: 6878 ldr r0, [r7, #4]
8006c18: f000 fc69 bl 80074ee <USBD_ClrFeature>
break;
8006c1c: e004 b.n 8006c28 <USBD_StdDevReq+0xbc>
default:
USBD_CtlError(pdev, req);
8006c1e: 6839 ldr r1, [r7, #0]
8006c20: 6878 ldr r0, [r7, #4]
8006c22: f000 fcc1 bl 80075a8 <USBD_CtlError>
break;
8006c26: bf00 nop
}
break;
8006c28: e004 b.n 8006c34 <USBD_StdDevReq+0xc8>
default:
USBD_CtlError(pdev, req);
8006c2a: 6839 ldr r1, [r7, #0]
8006c2c: 6878 ldr r0, [r7, #4]
8006c2e: f000 fcbb bl 80075a8 <USBD_CtlError>
break;
8006c32: bf00 nop
}
return ret;
8006c34: 7bfb ldrb r3, [r7, #15]
}
8006c36: 4618 mov r0, r3
8006c38: 3710 adds r7, #16
8006c3a: 46bd mov sp, r7
8006c3c: bd80 pop {r7, pc}
8006c3e: bf00 nop
08006c40 <USBD_StdItfReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8006c40: b580 push {r7, lr}
8006c42: b084 sub sp, #16
8006c44: af00 add r7, sp, #0
8006c46: 6078 str r0, [r7, #4]
8006c48: 6039 str r1, [r7, #0]
USBD_StatusTypeDef ret = USBD_OK;
8006c4a: 2300 movs r3, #0
8006c4c: 73fb strb r3, [r7, #15]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8006c4e: 683b ldr r3, [r7, #0]
8006c50: 781b ldrb r3, [r3, #0]
8006c52: f003 0360 and.w r3, r3, #96 ; 0x60
8006c56: 2b20 cmp r3, #32
8006c58: d003 beq.n 8006c62 <USBD_StdItfReq+0x22>
8006c5a: 2b40 cmp r3, #64 ; 0x40
8006c5c: d001 beq.n 8006c62 <USBD_StdItfReq+0x22>
8006c5e: 2b00 cmp r3, #0
8006c60: d12a bne.n 8006cb8 <USBD_StdItfReq+0x78>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
case USB_REQ_TYPE_STANDARD:
switch (pdev->dev_state)
8006c62: 687b ldr r3, [r7, #4]
8006c64: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8006c68: 3b01 subs r3, #1
8006c6a: 2b02 cmp r3, #2
8006c6c: d81d bhi.n 8006caa <USBD_StdItfReq+0x6a>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
8006c6e: 683b ldr r3, [r7, #0]
8006c70: 889b ldrh r3, [r3, #4]
8006c72: b2db uxtb r3, r3
8006c74: 2b01 cmp r3, #1
8006c76: d813 bhi.n 8006ca0 <USBD_StdItfReq+0x60>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
8006c78: 687b ldr r3, [r7, #4]
8006c7a: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006c7e: 689b ldr r3, [r3, #8]
8006c80: 6839 ldr r1, [r7, #0]
8006c82: 6878 ldr r0, [r7, #4]
8006c84: 4798 blx r3
8006c86: 4603 mov r3, r0
8006c88: 73fb strb r3, [r7, #15]
if ((req->wLength == 0U) && (ret == USBD_OK))
8006c8a: 683b ldr r3, [r7, #0]
8006c8c: 88db ldrh r3, [r3, #6]
8006c8e: 2b00 cmp r3, #0
8006c90: d110 bne.n 8006cb4 <USBD_StdItfReq+0x74>
8006c92: 7bfb ldrb r3, [r7, #15]
8006c94: 2b00 cmp r3, #0
8006c96: d10d bne.n 8006cb4 <USBD_StdItfReq+0x74>
{
USBD_CtlSendStatus(pdev);
8006c98: 6878 ldr r0, [r7, #4]
8006c9a: f000 fd4d bl 8007738 <USBD_CtlSendStatus>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8006c9e: e009 b.n 8006cb4 <USBD_StdItfReq+0x74>
USBD_CtlError(pdev, req);
8006ca0: 6839 ldr r1, [r7, #0]
8006ca2: 6878 ldr r0, [r7, #4]
8006ca4: f000 fc80 bl 80075a8 <USBD_CtlError>
break;
8006ca8: e004 b.n 8006cb4 <USBD_StdItfReq+0x74>
default:
USBD_CtlError(pdev, req);
8006caa: 6839 ldr r1, [r7, #0]
8006cac: 6878 ldr r0, [r7, #4]
8006cae: f000 fc7b bl 80075a8 <USBD_CtlError>
break;
8006cb2: e000 b.n 8006cb6 <USBD_StdItfReq+0x76>
break;
8006cb4: bf00 nop
}
break;
8006cb6: e004 b.n 8006cc2 <USBD_StdItfReq+0x82>
default:
USBD_CtlError(pdev, req);
8006cb8: 6839 ldr r1, [r7, #0]
8006cba: 6878 ldr r0, [r7, #4]
8006cbc: f000 fc74 bl 80075a8 <USBD_CtlError>
break;
8006cc0: bf00 nop
}
return USBD_OK;
8006cc2: 2300 movs r3, #0
}
8006cc4: 4618 mov r0, r3
8006cc6: 3710 adds r7, #16
8006cc8: 46bd mov sp, r7
8006cca: bd80 pop {r7, pc}
08006ccc <USBD_StdEPReq>:
* @param req: usb request
* @retval status
*/
USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8006ccc: b580 push {r7, lr}
8006cce: b084 sub sp, #16
8006cd0: af00 add r7, sp, #0
8006cd2: 6078 str r0, [r7, #4]
8006cd4: 6039 str r1, [r7, #0]
USBD_EndpointTypeDef *pep;
uint8_t ep_addr;
USBD_StatusTypeDef ret = USBD_OK;
8006cd6: 2300 movs r3, #0
8006cd8: 73fb strb r3, [r7, #15]
ep_addr = LOBYTE(req->wIndex);
8006cda: 683b ldr r3, [r7, #0]
8006cdc: 889b ldrh r3, [r3, #4]
8006cde: 73bb strb r3, [r7, #14]
switch (req->bmRequest & USB_REQ_TYPE_MASK)
8006ce0: 683b ldr r3, [r7, #0]
8006ce2: 781b ldrb r3, [r3, #0]
8006ce4: f003 0360 and.w r3, r3, #96 ; 0x60
8006ce8: 2b20 cmp r3, #32
8006cea: d004 beq.n 8006cf6 <USBD_StdEPReq+0x2a>
8006cec: 2b40 cmp r3, #64 ; 0x40
8006cee: d002 beq.n 8006cf6 <USBD_StdEPReq+0x2a>
8006cf0: 2b00 cmp r3, #0
8006cf2: d008 beq.n 8006d06 <USBD_StdEPReq+0x3a>
8006cf4: e13d b.n 8006f72 <USBD_StdEPReq+0x2a6>
{
case USB_REQ_TYPE_CLASS:
case USB_REQ_TYPE_VENDOR:
pdev->pClass->Setup(pdev, req);
8006cf6: 687b ldr r3, [r7, #4]
8006cf8: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006cfc: 689b ldr r3, [r3, #8]
8006cfe: 6839 ldr r1, [r7, #0]
8006d00: 6878 ldr r0, [r7, #4]
8006d02: 4798 blx r3
break;
8006d04: e13a b.n 8006f7c <USBD_StdEPReq+0x2b0>
case USB_REQ_TYPE_STANDARD:
/* Check if it is a class request */
if ((req->bmRequest & 0x60U) == 0x20U)
8006d06: 683b ldr r3, [r7, #0]
8006d08: 781b ldrb r3, [r3, #0]
8006d0a: f003 0360 and.w r3, r3, #96 ; 0x60
8006d0e: 2b20 cmp r3, #32
8006d10: d10a bne.n 8006d28 <USBD_StdEPReq+0x5c>
{
ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
8006d12: 687b ldr r3, [r7, #4]
8006d14: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006d18: 689b ldr r3, [r3, #8]
8006d1a: 6839 ldr r1, [r7, #0]
8006d1c: 6878 ldr r0, [r7, #4]
8006d1e: 4798 blx r3
8006d20: 4603 mov r3, r0
8006d22: 73fb strb r3, [r7, #15]
return ret;
8006d24: 7bfb ldrb r3, [r7, #15]
8006d26: e12a b.n 8006f7e <USBD_StdEPReq+0x2b2>
}
switch (req->bRequest)
8006d28: 683b ldr r3, [r7, #0]
8006d2a: 785b ldrb r3, [r3, #1]
8006d2c: 2b01 cmp r3, #1
8006d2e: d03e beq.n 8006dae <USBD_StdEPReq+0xe2>
8006d30: 2b03 cmp r3, #3
8006d32: d002 beq.n 8006d3a <USBD_StdEPReq+0x6e>
8006d34: 2b00 cmp r3, #0
8006d36: d070 beq.n 8006e1a <USBD_StdEPReq+0x14e>
8006d38: e115 b.n 8006f66 <USBD_StdEPReq+0x29a>
{
case USB_REQ_SET_FEATURE:
switch (pdev->dev_state)
8006d3a: 687b ldr r3, [r7, #4]
8006d3c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8006d40: 2b02 cmp r3, #2
8006d42: d002 beq.n 8006d4a <USBD_StdEPReq+0x7e>
8006d44: 2b03 cmp r3, #3
8006d46: d015 beq.n 8006d74 <USBD_StdEPReq+0xa8>
8006d48: e02b b.n 8006da2 <USBD_StdEPReq+0xd6>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8006d4a: 7bbb ldrb r3, [r7, #14]
8006d4c: 2b00 cmp r3, #0
8006d4e: d00c beq.n 8006d6a <USBD_StdEPReq+0x9e>
8006d50: 7bbb ldrb r3, [r7, #14]
8006d52: 2b80 cmp r3, #128 ; 0x80
8006d54: d009 beq.n 8006d6a <USBD_StdEPReq+0x9e>
{
USBD_LL_StallEP(pdev, ep_addr);
8006d56: 7bbb ldrb r3, [r7, #14]
8006d58: 4619 mov r1, r3
8006d5a: 6878 ldr r0, [r7, #4]
8006d5c: f001 f89c bl 8007e98 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
8006d60: 2180 movs r1, #128 ; 0x80
8006d62: 6878 ldr r0, [r7, #4]
8006d64: f001 f898 bl 8007e98 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8006d68: e020 b.n 8006dac <USBD_StdEPReq+0xe0>
USBD_CtlError(pdev, req);
8006d6a: 6839 ldr r1, [r7, #0]
8006d6c: 6878 ldr r0, [r7, #4]
8006d6e: f000 fc1b bl 80075a8 <USBD_CtlError>
break;
8006d72: e01b b.n 8006dac <USBD_StdEPReq+0xe0>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8006d74: 683b ldr r3, [r7, #0]
8006d76: 885b ldrh r3, [r3, #2]
8006d78: 2b00 cmp r3, #0
8006d7a: d10e bne.n 8006d9a <USBD_StdEPReq+0xce>
{
if ((ep_addr != 0x00U) &&
8006d7c: 7bbb ldrb r3, [r7, #14]
8006d7e: 2b00 cmp r3, #0
8006d80: d00b beq.n 8006d9a <USBD_StdEPReq+0xce>
8006d82: 7bbb ldrb r3, [r7, #14]
8006d84: 2b80 cmp r3, #128 ; 0x80
8006d86: d008 beq.n 8006d9a <USBD_StdEPReq+0xce>
(ep_addr != 0x80U) && (req->wLength == 0x00U))
8006d88: 683b ldr r3, [r7, #0]
8006d8a: 88db ldrh r3, [r3, #6]
8006d8c: 2b00 cmp r3, #0
8006d8e: d104 bne.n 8006d9a <USBD_StdEPReq+0xce>
{
USBD_LL_StallEP(pdev, ep_addr);
8006d90: 7bbb ldrb r3, [r7, #14]
8006d92: 4619 mov r1, r3
8006d94: 6878 ldr r0, [r7, #4]
8006d96: f001 f87f bl 8007e98 <USBD_LL_StallEP>
}
}
USBD_CtlSendStatus(pdev);
8006d9a: 6878 ldr r0, [r7, #4]
8006d9c: f000 fccc bl 8007738 <USBD_CtlSendStatus>
break;
8006da0: e004 b.n 8006dac <USBD_StdEPReq+0xe0>
default:
USBD_CtlError(pdev, req);
8006da2: 6839 ldr r1, [r7, #0]
8006da4: 6878 ldr r0, [r7, #4]
8006da6: f000 fbff bl 80075a8 <USBD_CtlError>
break;
8006daa: bf00 nop
}
break;
8006dac: e0e0 b.n 8006f70 <USBD_StdEPReq+0x2a4>
case USB_REQ_CLEAR_FEATURE:
switch (pdev->dev_state)
8006dae: 687b ldr r3, [r7, #4]
8006db0: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8006db4: 2b02 cmp r3, #2
8006db6: d002 beq.n 8006dbe <USBD_StdEPReq+0xf2>
8006db8: 2b03 cmp r3, #3
8006dba: d015 beq.n 8006de8 <USBD_StdEPReq+0x11c>
8006dbc: e026 b.n 8006e0c <USBD_StdEPReq+0x140>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8006dbe: 7bbb ldrb r3, [r7, #14]
8006dc0: 2b00 cmp r3, #0
8006dc2: d00c beq.n 8006dde <USBD_StdEPReq+0x112>
8006dc4: 7bbb ldrb r3, [r7, #14]
8006dc6: 2b80 cmp r3, #128 ; 0x80
8006dc8: d009 beq.n 8006dde <USBD_StdEPReq+0x112>
{
USBD_LL_StallEP(pdev, ep_addr);
8006dca: 7bbb ldrb r3, [r7, #14]
8006dcc: 4619 mov r1, r3
8006dce: 6878 ldr r0, [r7, #4]
8006dd0: f001 f862 bl 8007e98 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0x80U);
8006dd4: 2180 movs r1, #128 ; 0x80
8006dd6: 6878 ldr r0, [r7, #4]
8006dd8: f001 f85e bl 8007e98 <USBD_LL_StallEP>
}
else
{
USBD_CtlError(pdev, req);
}
break;
8006ddc: e01c b.n 8006e18 <USBD_StdEPReq+0x14c>
USBD_CtlError(pdev, req);
8006dde: 6839 ldr r1, [r7, #0]
8006de0: 6878 ldr r0, [r7, #4]
8006de2: f000 fbe1 bl 80075a8 <USBD_CtlError>
break;
8006de6: e017 b.n 8006e18 <USBD_StdEPReq+0x14c>
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_EP_HALT)
8006de8: 683b ldr r3, [r7, #0]
8006dea: 885b ldrh r3, [r3, #2]
8006dec: 2b00 cmp r3, #0
8006dee: d112 bne.n 8006e16 <USBD_StdEPReq+0x14a>
{
if ((ep_addr & 0x7FU) != 0x00U)
8006df0: 7bbb ldrb r3, [r7, #14]
8006df2: f003 037f and.w r3, r3, #127 ; 0x7f
8006df6: 2b00 cmp r3, #0
8006df8: d004 beq.n 8006e04 <USBD_StdEPReq+0x138>
{
USBD_LL_ClearStallEP(pdev, ep_addr);
8006dfa: 7bbb ldrb r3, [r7, #14]
8006dfc: 4619 mov r1, r3
8006dfe: 6878 ldr r0, [r7, #4]
8006e00: f001 f869 bl 8007ed6 <USBD_LL_ClearStallEP>
}
USBD_CtlSendStatus(pdev);
8006e04: 6878 ldr r0, [r7, #4]
8006e06: f000 fc97 bl 8007738 <USBD_CtlSendStatus>
}
break;
8006e0a: e004 b.n 8006e16 <USBD_StdEPReq+0x14a>
default:
USBD_CtlError(pdev, req);
8006e0c: 6839 ldr r1, [r7, #0]
8006e0e: 6878 ldr r0, [r7, #4]
8006e10: f000 fbca bl 80075a8 <USBD_CtlError>
break;
8006e14: e000 b.n 8006e18 <USBD_StdEPReq+0x14c>
break;
8006e16: bf00 nop
}
break;
8006e18: e0aa b.n 8006f70 <USBD_StdEPReq+0x2a4>
case USB_REQ_GET_STATUS:
switch (pdev->dev_state)
8006e1a: 687b ldr r3, [r7, #4]
8006e1c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8006e20: 2b02 cmp r3, #2
8006e22: d002 beq.n 8006e2a <USBD_StdEPReq+0x15e>
8006e24: 2b03 cmp r3, #3
8006e26: d032 beq.n 8006e8e <USBD_StdEPReq+0x1c2>
8006e28: e097 b.n 8006f5a <USBD_StdEPReq+0x28e>
{
case USBD_STATE_ADDRESSED:
if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
8006e2a: 7bbb ldrb r3, [r7, #14]
8006e2c: 2b00 cmp r3, #0
8006e2e: d007 beq.n 8006e40 <USBD_StdEPReq+0x174>
8006e30: 7bbb ldrb r3, [r7, #14]
8006e32: 2b80 cmp r3, #128 ; 0x80
8006e34: d004 beq.n 8006e40 <USBD_StdEPReq+0x174>
{
USBD_CtlError(pdev, req);
8006e36: 6839 ldr r1, [r7, #0]
8006e38: 6878 ldr r0, [r7, #4]
8006e3a: f000 fbb5 bl 80075a8 <USBD_CtlError>
break;
8006e3e: e091 b.n 8006f64 <USBD_StdEPReq+0x298>
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8006e40: f997 300e ldrsb.w r3, [r7, #14]
8006e44: 2b00 cmp r3, #0
8006e46: da0b bge.n 8006e60 <USBD_StdEPReq+0x194>
8006e48: 7bbb ldrb r3, [r7, #14]
8006e4a: f003 027f and.w r2, r3, #127 ; 0x7f
8006e4e: 4613 mov r3, r2
8006e50: 009b lsls r3, r3, #2
8006e52: 4413 add r3, r2
8006e54: 009b lsls r3, r3, #2
8006e56: 3310 adds r3, #16
8006e58: 687a ldr r2, [r7, #4]
8006e5a: 4413 add r3, r2
8006e5c: 3304 adds r3, #4
8006e5e: e00b b.n 8006e78 <USBD_StdEPReq+0x1ac>
&pdev->ep_out[ep_addr & 0x7FU];
8006e60: 7bbb ldrb r3, [r7, #14]
8006e62: f003 027f and.w r2, r3, #127 ; 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8006e66: 4613 mov r3, r2
8006e68: 009b lsls r3, r3, #2
8006e6a: 4413 add r3, r2
8006e6c: 009b lsls r3, r3, #2
8006e6e: f503 73a8 add.w r3, r3, #336 ; 0x150
8006e72: 687a ldr r2, [r7, #4]
8006e74: 4413 add r3, r2
8006e76: 3304 adds r3, #4
8006e78: 60bb str r3, [r7, #8]
pep->status = 0x0000U;
8006e7a: 68bb ldr r3, [r7, #8]
8006e7c: 2200 movs r2, #0
8006e7e: 601a str r2, [r3, #0]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
8006e80: 68bb ldr r3, [r7, #8]
8006e82: 2202 movs r2, #2
8006e84: 4619 mov r1, r3
8006e86: 6878 ldr r0, [r7, #4]
8006e88: f000 fbf8 bl 800767c <USBD_CtlSendData>
break;
8006e8c: e06a b.n 8006f64 <USBD_StdEPReq+0x298>
case USBD_STATE_CONFIGURED:
if ((ep_addr & 0x80U) == 0x80U)
8006e8e: f997 300e ldrsb.w r3, [r7, #14]
8006e92: 2b00 cmp r3, #0
8006e94: da11 bge.n 8006eba <USBD_StdEPReq+0x1ee>
{
if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
8006e96: 7bbb ldrb r3, [r7, #14]
8006e98: f003 020f and.w r2, r3, #15
8006e9c: 6879 ldr r1, [r7, #4]
8006e9e: 4613 mov r3, r2
8006ea0: 009b lsls r3, r3, #2
8006ea2: 4413 add r3, r2
8006ea4: 009b lsls r3, r3, #2
8006ea6: 440b add r3, r1
8006ea8: 3318 adds r3, #24
8006eaa: 681b ldr r3, [r3, #0]
8006eac: 2b00 cmp r3, #0
8006eae: d117 bne.n 8006ee0 <USBD_StdEPReq+0x214>
{
USBD_CtlError(pdev, req);
8006eb0: 6839 ldr r1, [r7, #0]
8006eb2: 6878 ldr r0, [r7, #4]
8006eb4: f000 fb78 bl 80075a8 <USBD_CtlError>
break;
8006eb8: e054 b.n 8006f64 <USBD_StdEPReq+0x298>
}
}
else
{
if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
8006eba: 7bbb ldrb r3, [r7, #14]
8006ebc: f003 020f and.w r2, r3, #15
8006ec0: 6879 ldr r1, [r7, #4]
8006ec2: 4613 mov r3, r2
8006ec4: 009b lsls r3, r3, #2
8006ec6: 4413 add r3, r2
8006ec8: 009b lsls r3, r3, #2
8006eca: 440b add r3, r1
8006ecc: f503 73ac add.w r3, r3, #344 ; 0x158
8006ed0: 681b ldr r3, [r3, #0]
8006ed2: 2b00 cmp r3, #0
8006ed4: d104 bne.n 8006ee0 <USBD_StdEPReq+0x214>
{
USBD_CtlError(pdev, req);
8006ed6: 6839 ldr r1, [r7, #0]
8006ed8: 6878 ldr r0, [r7, #4]
8006eda: f000 fb65 bl 80075a8 <USBD_CtlError>
break;
8006ede: e041 b.n 8006f64 <USBD_StdEPReq+0x298>
}
}
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8006ee0: f997 300e ldrsb.w r3, [r7, #14]
8006ee4: 2b00 cmp r3, #0
8006ee6: da0b bge.n 8006f00 <USBD_StdEPReq+0x234>
8006ee8: 7bbb ldrb r3, [r7, #14]
8006eea: f003 027f and.w r2, r3, #127 ; 0x7f
8006eee: 4613 mov r3, r2
8006ef0: 009b lsls r3, r3, #2
8006ef2: 4413 add r3, r2
8006ef4: 009b lsls r3, r3, #2
8006ef6: 3310 adds r3, #16
8006ef8: 687a ldr r2, [r7, #4]
8006efa: 4413 add r3, r2
8006efc: 3304 adds r3, #4
8006efe: e00b b.n 8006f18 <USBD_StdEPReq+0x24c>
&pdev->ep_out[ep_addr & 0x7FU];
8006f00: 7bbb ldrb r3, [r7, #14]
8006f02: f003 027f and.w r2, r3, #127 ; 0x7f
pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
8006f06: 4613 mov r3, r2
8006f08: 009b lsls r3, r3, #2
8006f0a: 4413 add r3, r2
8006f0c: 009b lsls r3, r3, #2
8006f0e: f503 73a8 add.w r3, r3, #336 ; 0x150
8006f12: 687a ldr r2, [r7, #4]
8006f14: 4413 add r3, r2
8006f16: 3304 adds r3, #4
8006f18: 60bb str r3, [r7, #8]
if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
8006f1a: 7bbb ldrb r3, [r7, #14]
8006f1c: 2b00 cmp r3, #0
8006f1e: d002 beq.n 8006f26 <USBD_StdEPReq+0x25a>
8006f20: 7bbb ldrb r3, [r7, #14]
8006f22: 2b80 cmp r3, #128 ; 0x80
8006f24: d103 bne.n 8006f2e <USBD_StdEPReq+0x262>
{
pep->status = 0x0000U;
8006f26: 68bb ldr r3, [r7, #8]
8006f28: 2200 movs r2, #0
8006f2a: 601a str r2, [r3, #0]
8006f2c: e00e b.n 8006f4c <USBD_StdEPReq+0x280>
}
else if (USBD_LL_IsStallEP(pdev, ep_addr))
8006f2e: 7bbb ldrb r3, [r7, #14]
8006f30: 4619 mov r1, r3
8006f32: 6878 ldr r0, [r7, #4]
8006f34: f000 ffee bl 8007f14 <USBD_LL_IsStallEP>
8006f38: 4603 mov r3, r0
8006f3a: 2b00 cmp r3, #0
8006f3c: d003 beq.n 8006f46 <USBD_StdEPReq+0x27a>
{
pep->status = 0x0001U;
8006f3e: 68bb ldr r3, [r7, #8]
8006f40: 2201 movs r2, #1
8006f42: 601a str r2, [r3, #0]
8006f44: e002 b.n 8006f4c <USBD_StdEPReq+0x280>
}
else
{
pep->status = 0x0000U;
8006f46: 68bb ldr r3, [r7, #8]
8006f48: 2200 movs r2, #0
8006f4a: 601a str r2, [r3, #0]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
8006f4c: 68bb ldr r3, [r7, #8]
8006f4e: 2202 movs r2, #2
8006f50: 4619 mov r1, r3
8006f52: 6878 ldr r0, [r7, #4]
8006f54: f000 fb92 bl 800767c <USBD_CtlSendData>
break;
8006f58: e004 b.n 8006f64 <USBD_StdEPReq+0x298>
default:
USBD_CtlError(pdev, req);
8006f5a: 6839 ldr r1, [r7, #0]
8006f5c: 6878 ldr r0, [r7, #4]
8006f5e: f000 fb23 bl 80075a8 <USBD_CtlError>
break;
8006f62: bf00 nop
}
break;
8006f64: e004 b.n 8006f70 <USBD_StdEPReq+0x2a4>
default:
USBD_CtlError(pdev, req);
8006f66: 6839 ldr r1, [r7, #0]
8006f68: 6878 ldr r0, [r7, #4]
8006f6a: f000 fb1d bl 80075a8 <USBD_CtlError>
break;
8006f6e: bf00 nop
}
break;
8006f70: e004 b.n 8006f7c <USBD_StdEPReq+0x2b0>
default:
USBD_CtlError(pdev, req);
8006f72: 6839 ldr r1, [r7, #0]
8006f74: 6878 ldr r0, [r7, #4]
8006f76: f000 fb17 bl 80075a8 <USBD_CtlError>
break;
8006f7a: bf00 nop
}
return ret;
8006f7c: 7bfb ldrb r3, [r7, #15]
}
8006f7e: 4618 mov r0, r3
8006f80: 3710 adds r7, #16
8006f82: 46bd mov sp, r7
8006f84: bd80 pop {r7, pc}
...
08006f88 <USBD_GetDescriptor>:
* @param req: usb request
* @retval status
*/
static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8006f88: b580 push {r7, lr}
8006f8a: b084 sub sp, #16
8006f8c: af00 add r7, sp, #0
8006f8e: 6078 str r0, [r7, #4]
8006f90: 6039 str r1, [r7, #0]
uint16_t len = 0U;
8006f92: 2300 movs r3, #0
8006f94: 813b strh r3, [r7, #8]
uint8_t *pbuf = NULL;
8006f96: 2300 movs r3, #0
8006f98: 60fb str r3, [r7, #12]
uint8_t err = 0U;
8006f9a: 2300 movs r3, #0
8006f9c: 72fb strb r3, [r7, #11]
switch (req->wValue >> 8)
8006f9e: 683b ldr r3, [r7, #0]
8006fa0: 885b ldrh r3, [r3, #2]
8006fa2: 0a1b lsrs r3, r3, #8
8006fa4: b29b uxth r3, r3
8006fa6: 3b01 subs r3, #1
8006fa8: 2b06 cmp r3, #6
8006faa: f200 8128 bhi.w 80071fe <USBD_GetDescriptor+0x276>
8006fae: a201 add r2, pc, #4 ; (adr r2, 8006fb4 <USBD_GetDescriptor+0x2c>)
8006fb0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006fb4: 08006fd1 .word 0x08006fd1
8006fb8: 08006fe9 .word 0x08006fe9
8006fbc: 08007029 .word 0x08007029
8006fc0: 080071ff .word 0x080071ff
8006fc4: 080071ff .word 0x080071ff
8006fc8: 0800719f .word 0x0800719f
8006fcc: 080071cb .word 0x080071cb
err++;
}
break;
#endif
case USB_DESC_TYPE_DEVICE:
pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
8006fd0: 687b ldr r3, [r7, #4]
8006fd2: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
8006fd6: 681b ldr r3, [r3, #0]
8006fd8: 687a ldr r2, [r7, #4]
8006fda: 7c12 ldrb r2, [r2, #16]
8006fdc: f107 0108 add.w r1, r7, #8
8006fe0: 4610 mov r0, r2
8006fe2: 4798 blx r3
8006fe4: 60f8 str r0, [r7, #12]
break;
8006fe6: e112 b.n 800720e <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
8006fe8: 687b ldr r3, [r7, #4]
8006fea: 7c1b ldrb r3, [r3, #16]
8006fec: 2b00 cmp r3, #0
8006fee: d10d bne.n 800700c <USBD_GetDescriptor+0x84>
{
pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
8006ff0: 687b ldr r3, [r7, #4]
8006ff2: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8006ff6: 6a9b ldr r3, [r3, #40] ; 0x28
8006ff8: f107 0208 add.w r2, r7, #8
8006ffc: 4610 mov r0, r2
8006ffe: 4798 blx r3
8007000: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
8007002: 68fb ldr r3, [r7, #12]
8007004: 3301 adds r3, #1
8007006: 2202 movs r2, #2
8007008: 701a strb r2, [r3, #0]
else
{
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
}
break;
800700a: e100 b.n 800720e <USBD_GetDescriptor+0x286>
pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
800700c: 687b ldr r3, [r7, #4]
800700e: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
8007012: 6adb ldr r3, [r3, #44] ; 0x2c
8007014: f107 0208 add.w r2, r7, #8
8007018: 4610 mov r0, r2
800701a: 4798 blx r3
800701c: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
800701e: 68fb ldr r3, [r7, #12]
8007020: 3301 adds r3, #1
8007022: 2202 movs r2, #2
8007024: 701a strb r2, [r3, #0]
break;
8007026: e0f2 b.n 800720e <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_STRING:
switch ((uint8_t)(req->wValue))
8007028: 683b ldr r3, [r7, #0]
800702a: 885b ldrh r3, [r3, #2]
800702c: b2db uxtb r3, r3
800702e: 2b05 cmp r3, #5
8007030: f200 80ac bhi.w 800718c <USBD_GetDescriptor+0x204>
8007034: a201 add r2, pc, #4 ; (adr r2, 800703c <USBD_GetDescriptor+0xb4>)
8007036: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800703a: bf00 nop
800703c: 08007055 .word 0x08007055
8007040: 08007089 .word 0x08007089
8007044: 080070bd .word 0x080070bd
8007048: 080070f1 .word 0x080070f1
800704c: 08007125 .word 0x08007125
8007050: 08007159 .word 0x08007159
{
case USBD_IDX_LANGID_STR:
if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
8007054: 687b ldr r3, [r7, #4]
8007056: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
800705a: 685b ldr r3, [r3, #4]
800705c: 2b00 cmp r3, #0
800705e: d00b beq.n 8007078 <USBD_GetDescriptor+0xf0>
{
pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
8007060: 687b ldr r3, [r7, #4]
8007062: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
8007066: 685b ldr r3, [r3, #4]
8007068: 687a ldr r2, [r7, #4]
800706a: 7c12 ldrb r2, [r2, #16]
800706c: f107 0108 add.w r1, r7, #8
8007070: 4610 mov r0, r2
8007072: 4798 blx r3
8007074: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8007076: e091 b.n 800719c <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
8007078: 6839 ldr r1, [r7, #0]
800707a: 6878 ldr r0, [r7, #4]
800707c: f000 fa94 bl 80075a8 <USBD_CtlError>
err++;
8007080: 7afb ldrb r3, [r7, #11]
8007082: 3301 adds r3, #1
8007084: 72fb strb r3, [r7, #11]
break;
8007086: e089 b.n 800719c <USBD_GetDescriptor+0x214>
case USBD_IDX_MFC_STR:
if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
8007088: 687b ldr r3, [r7, #4]
800708a: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
800708e: 689b ldr r3, [r3, #8]
8007090: 2b00 cmp r3, #0
8007092: d00b beq.n 80070ac <USBD_GetDescriptor+0x124>
{
pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
8007094: 687b ldr r3, [r7, #4]
8007096: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
800709a: 689b ldr r3, [r3, #8]
800709c: 687a ldr r2, [r7, #4]
800709e: 7c12 ldrb r2, [r2, #16]
80070a0: f107 0108 add.w r1, r7, #8
80070a4: 4610 mov r0, r2
80070a6: 4798 blx r3
80070a8: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
80070aa: e077 b.n 800719c <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
80070ac: 6839 ldr r1, [r7, #0]
80070ae: 6878 ldr r0, [r7, #4]
80070b0: f000 fa7a bl 80075a8 <USBD_CtlError>
err++;
80070b4: 7afb ldrb r3, [r7, #11]
80070b6: 3301 adds r3, #1
80070b8: 72fb strb r3, [r7, #11]
break;
80070ba: e06f b.n 800719c <USBD_GetDescriptor+0x214>
case USBD_IDX_PRODUCT_STR:
if (pdev->pDesc->GetProductStrDescriptor != NULL)
80070bc: 687b ldr r3, [r7, #4]
80070be: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
80070c2: 68db ldr r3, [r3, #12]
80070c4: 2b00 cmp r3, #0
80070c6: d00b beq.n 80070e0 <USBD_GetDescriptor+0x158>
{
pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
80070c8: 687b ldr r3, [r7, #4]
80070ca: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
80070ce: 68db ldr r3, [r3, #12]
80070d0: 687a ldr r2, [r7, #4]
80070d2: 7c12 ldrb r2, [r2, #16]
80070d4: f107 0108 add.w r1, r7, #8
80070d8: 4610 mov r0, r2
80070da: 4798 blx r3
80070dc: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
80070de: e05d b.n 800719c <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
80070e0: 6839 ldr r1, [r7, #0]
80070e2: 6878 ldr r0, [r7, #4]
80070e4: f000 fa60 bl 80075a8 <USBD_CtlError>
err++;
80070e8: 7afb ldrb r3, [r7, #11]
80070ea: 3301 adds r3, #1
80070ec: 72fb strb r3, [r7, #11]
break;
80070ee: e055 b.n 800719c <USBD_GetDescriptor+0x214>
case USBD_IDX_SERIAL_STR:
if (pdev->pDesc->GetSerialStrDescriptor != NULL)
80070f0: 687b ldr r3, [r7, #4]
80070f2: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
80070f6: 691b ldr r3, [r3, #16]
80070f8: 2b00 cmp r3, #0
80070fa: d00b beq.n 8007114 <USBD_GetDescriptor+0x18c>
{
pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
80070fc: 687b ldr r3, [r7, #4]
80070fe: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
8007102: 691b ldr r3, [r3, #16]
8007104: 687a ldr r2, [r7, #4]
8007106: 7c12 ldrb r2, [r2, #16]
8007108: f107 0108 add.w r1, r7, #8
800710c: 4610 mov r0, r2
800710e: 4798 blx r3
8007110: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8007112: e043 b.n 800719c <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
8007114: 6839 ldr r1, [r7, #0]
8007116: 6878 ldr r0, [r7, #4]
8007118: f000 fa46 bl 80075a8 <USBD_CtlError>
err++;
800711c: 7afb ldrb r3, [r7, #11]
800711e: 3301 adds r3, #1
8007120: 72fb strb r3, [r7, #11]
break;
8007122: e03b b.n 800719c <USBD_GetDescriptor+0x214>
case USBD_IDX_CONFIG_STR:
if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
8007124: 687b ldr r3, [r7, #4]
8007126: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
800712a: 695b ldr r3, [r3, #20]
800712c: 2b00 cmp r3, #0
800712e: d00b beq.n 8007148 <USBD_GetDescriptor+0x1c0>
{
pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
8007130: 687b ldr r3, [r7, #4]
8007132: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
8007136: 695b ldr r3, [r3, #20]
8007138: 687a ldr r2, [r7, #4]
800713a: 7c12 ldrb r2, [r2, #16]
800713c: f107 0108 add.w r1, r7, #8
8007140: 4610 mov r0, r2
8007142: 4798 blx r3
8007144: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
8007146: e029 b.n 800719c <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
8007148: 6839 ldr r1, [r7, #0]
800714a: 6878 ldr r0, [r7, #4]
800714c: f000 fa2c bl 80075a8 <USBD_CtlError>
err++;
8007150: 7afb ldrb r3, [r7, #11]
8007152: 3301 adds r3, #1
8007154: 72fb strb r3, [r7, #11]
break;
8007156: e021 b.n 800719c <USBD_GetDescriptor+0x214>
case USBD_IDX_INTERFACE_STR:
if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
8007158: 687b ldr r3, [r7, #4]
800715a: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
800715e: 699b ldr r3, [r3, #24]
8007160: 2b00 cmp r3, #0
8007162: d00b beq.n 800717c <USBD_GetDescriptor+0x1f4>
{
pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
8007164: 687b ldr r3, [r7, #4]
8007166: f8d3 32b0 ldr.w r3, [r3, #688] ; 0x2b0
800716a: 699b ldr r3, [r3, #24]
800716c: 687a ldr r2, [r7, #4]
800716e: 7c12 ldrb r2, [r2, #16]
8007170: f107 0108 add.w r1, r7, #8
8007174: 4610 mov r0, r2
8007176: 4798 blx r3
8007178: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
800717a: e00f b.n 800719c <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
800717c: 6839 ldr r1, [r7, #0]
800717e: 6878 ldr r0, [r7, #4]
8007180: f000 fa12 bl 80075a8 <USBD_CtlError>
err++;
8007184: 7afb ldrb r3, [r7, #11]
8007186: 3301 adds r3, #1
8007188: 72fb strb r3, [r7, #11]
break;
800718a: e007 b.n 800719c <USBD_GetDescriptor+0x214>
USBD_CtlError(pdev, req);
err++;
}
break;
#else
USBD_CtlError(pdev, req);
800718c: 6839 ldr r1, [r7, #0]
800718e: 6878 ldr r0, [r7, #4]
8007190: f000 fa0a bl 80075a8 <USBD_CtlError>
err++;
8007194: 7afb ldrb r3, [r7, #11]
8007196: 3301 adds r3, #1
8007198: 72fb strb r3, [r7, #11]
#endif
}
break;
800719a: e038 b.n 800720e <USBD_GetDescriptor+0x286>
800719c: e037 b.n 800720e <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_DEVICE_QUALIFIER:
if (pdev->dev_speed == USBD_SPEED_HIGH)
800719e: 687b ldr r3, [r7, #4]
80071a0: 7c1b ldrb r3, [r3, #16]
80071a2: 2b00 cmp r3, #0
80071a4: d109 bne.n 80071ba <USBD_GetDescriptor+0x232>
{
pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
80071a6: 687b ldr r3, [r7, #4]
80071a8: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
80071ac: 6b5b ldr r3, [r3, #52] ; 0x34
80071ae: f107 0208 add.w r2, r7, #8
80071b2: 4610 mov r0, r2
80071b4: 4798 blx r3
80071b6: 60f8 str r0, [r7, #12]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
80071b8: e029 b.n 800720e <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
80071ba: 6839 ldr r1, [r7, #0]
80071bc: 6878 ldr r0, [r7, #4]
80071be: f000 f9f3 bl 80075a8 <USBD_CtlError>
err++;
80071c2: 7afb ldrb r3, [r7, #11]
80071c4: 3301 adds r3, #1
80071c6: 72fb strb r3, [r7, #11]
break;
80071c8: e021 b.n 800720e <USBD_GetDescriptor+0x286>
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
if (pdev->dev_speed == USBD_SPEED_HIGH)
80071ca: 687b ldr r3, [r7, #4]
80071cc: 7c1b ldrb r3, [r3, #16]
80071ce: 2b00 cmp r3, #0
80071d0: d10d bne.n 80071ee <USBD_GetDescriptor+0x266>
{
pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
80071d2: 687b ldr r3, [r7, #4]
80071d4: f8d3 32b4 ldr.w r3, [r3, #692] ; 0x2b4
80071d8: 6b1b ldr r3, [r3, #48] ; 0x30
80071da: f107 0208 add.w r2, r7, #8
80071de: 4610 mov r0, r2
80071e0: 4798 blx r3
80071e2: 60f8 str r0, [r7, #12]
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
80071e4: 68fb ldr r3, [r7, #12]
80071e6: 3301 adds r3, #1
80071e8: 2207 movs r2, #7
80071ea: 701a strb r2, [r3, #0]
else
{
USBD_CtlError(pdev, req);
err++;
}
break;
80071ec: e00f b.n 800720e <USBD_GetDescriptor+0x286>
USBD_CtlError(pdev, req);
80071ee: 6839 ldr r1, [r7, #0]
80071f0: 6878 ldr r0, [r7, #4]
80071f2: f000 f9d9 bl 80075a8 <USBD_CtlError>
err++;
80071f6: 7afb ldrb r3, [r7, #11]
80071f8: 3301 adds r3, #1
80071fa: 72fb strb r3, [r7, #11]
break;
80071fc: e007 b.n 800720e <USBD_GetDescriptor+0x286>
default:
USBD_CtlError(pdev, req);
80071fe: 6839 ldr r1, [r7, #0]
8007200: 6878 ldr r0, [r7, #4]
8007202: f000 f9d1 bl 80075a8 <USBD_CtlError>
err++;
8007206: 7afb ldrb r3, [r7, #11]
8007208: 3301 adds r3, #1
800720a: 72fb strb r3, [r7, #11]
break;
800720c: bf00 nop
}
if (err != 0U)
800720e: 7afb ldrb r3, [r7, #11]
8007210: 2b00 cmp r3, #0
8007212: d11c bne.n 800724e <USBD_GetDescriptor+0x2c6>
{
return;
}
else
{
if ((len != 0U) && (req->wLength != 0U))
8007214: 893b ldrh r3, [r7, #8]
8007216: 2b00 cmp r3, #0
8007218: d011 beq.n 800723e <USBD_GetDescriptor+0x2b6>
800721a: 683b ldr r3, [r7, #0]
800721c: 88db ldrh r3, [r3, #6]
800721e: 2b00 cmp r3, #0
8007220: d00d beq.n 800723e <USBD_GetDescriptor+0x2b6>
{
len = MIN(len, req->wLength);
8007222: 683b ldr r3, [r7, #0]
8007224: 88da ldrh r2, [r3, #6]
8007226: 893b ldrh r3, [r7, #8]
8007228: 4293 cmp r3, r2
800722a: bf28 it cs
800722c: 4613 movcs r3, r2
800722e: b29b uxth r3, r3
8007230: 813b strh r3, [r7, #8]
(void)USBD_CtlSendData(pdev, pbuf, len);
8007232: 893b ldrh r3, [r7, #8]
8007234: 461a mov r2, r3
8007236: 68f9 ldr r1, [r7, #12]
8007238: 6878 ldr r0, [r7, #4]
800723a: f000 fa1f bl 800767c <USBD_CtlSendData>
}
if (req->wLength == 0U)
800723e: 683b ldr r3, [r7, #0]
8007240: 88db ldrh r3, [r3, #6]
8007242: 2b00 cmp r3, #0
8007244: d104 bne.n 8007250 <USBD_GetDescriptor+0x2c8>
{
(void)USBD_CtlSendStatus(pdev);
8007246: 6878 ldr r0, [r7, #4]
8007248: f000 fa76 bl 8007738 <USBD_CtlSendStatus>
800724c: e000 b.n 8007250 <USBD_GetDescriptor+0x2c8>
return;
800724e: bf00 nop
}
}
}
8007250: 3710 adds r7, #16
8007252: 46bd mov sp, r7
8007254: bd80 pop {r7, pc}
8007256: bf00 nop
08007258 <USBD_SetAddress>:
* @param req: usb request
* @retval status
*/
static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
8007258: b580 push {r7, lr}
800725a: b084 sub sp, #16
800725c: af00 add r7, sp, #0
800725e: 6078 str r0, [r7, #4]
8007260: 6039 str r1, [r7, #0]
uint8_t dev_addr;
if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
8007262: 683b ldr r3, [r7, #0]
8007264: 889b ldrh r3, [r3, #4]
8007266: 2b00 cmp r3, #0
8007268: d130 bne.n 80072cc <USBD_SetAddress+0x74>
800726a: 683b ldr r3, [r7, #0]
800726c: 88db ldrh r3, [r3, #6]
800726e: 2b00 cmp r3, #0
8007270: d12c bne.n 80072cc <USBD_SetAddress+0x74>
8007272: 683b ldr r3, [r7, #0]
8007274: 885b ldrh r3, [r3, #2]
8007276: 2b7f cmp r3, #127 ; 0x7f
8007278: d828 bhi.n 80072cc <USBD_SetAddress+0x74>
{
dev_addr = (uint8_t)(req->wValue) & 0x7FU;
800727a: 683b ldr r3, [r7, #0]
800727c: 885b ldrh r3, [r3, #2]
800727e: b2db uxtb r3, r3
8007280: f003 037f and.w r3, r3, #127 ; 0x7f
8007284: 73fb strb r3, [r7, #15]
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8007286: 687b ldr r3, [r7, #4]
8007288: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
800728c: 2b03 cmp r3, #3
800728e: d104 bne.n 800729a <USBD_SetAddress+0x42>
{
USBD_CtlError(pdev, req);
8007290: 6839 ldr r1, [r7, #0]
8007292: 6878 ldr r0, [r7, #4]
8007294: f000 f988 bl 80075a8 <USBD_CtlError>
if (pdev->dev_state == USBD_STATE_CONFIGURED)
8007298: e01c b.n 80072d4 <USBD_SetAddress+0x7c>
}
else
{
pdev->dev_address = dev_addr;
800729a: 687b ldr r3, [r7, #4]
800729c: 7bfa ldrb r2, [r7, #15]
800729e: f883 229e strb.w r2, [r3, #670] ; 0x29e
USBD_LL_SetUSBAddress(pdev, dev_addr);
80072a2: 7bfb ldrb r3, [r7, #15]
80072a4: 4619 mov r1, r3
80072a6: 6878 ldr r0, [r7, #4]
80072a8: f000 fe59 bl 8007f5e <USBD_LL_SetUSBAddress>
USBD_CtlSendStatus(pdev);
80072ac: 6878 ldr r0, [r7, #4]
80072ae: f000 fa43 bl 8007738 <USBD_CtlSendStatus>
if (dev_addr != 0U)
80072b2: 7bfb ldrb r3, [r7, #15]
80072b4: 2b00 cmp r3, #0
80072b6: d004 beq.n 80072c2 <USBD_SetAddress+0x6a>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
80072b8: 687b ldr r3, [r7, #4]
80072ba: 2202 movs r2, #2
80072bc: f883 229c strb.w r2, [r3, #668] ; 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
80072c0: e008 b.n 80072d4 <USBD_SetAddress+0x7c>
}
else
{
pdev->dev_state = USBD_STATE_DEFAULT;
80072c2: 687b ldr r3, [r7, #4]
80072c4: 2201 movs r2, #1
80072c6: f883 229c strb.w r2, [r3, #668] ; 0x29c
if (pdev->dev_state == USBD_STATE_CONFIGURED)
80072ca: e003 b.n 80072d4 <USBD_SetAddress+0x7c>
}
}
}
else
{
USBD_CtlError(pdev, req);
80072cc: 6839 ldr r1, [r7, #0]
80072ce: 6878 ldr r0, [r7, #4]
80072d0: f000 f96a bl 80075a8 <USBD_CtlError>
}
}
80072d4: bf00 nop
80072d6: 3710 adds r7, #16
80072d8: 46bd mov sp, r7
80072da: bd80 pop {r7, pc}
080072dc <USBD_SetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80072dc: b580 push {r7, lr}
80072de: b082 sub sp, #8
80072e0: af00 add r7, sp, #0
80072e2: 6078 str r0, [r7, #4]
80072e4: 6039 str r1, [r7, #0]
static uint8_t cfgidx;
cfgidx = (uint8_t)(req->wValue);
80072e6: 683b ldr r3, [r7, #0]
80072e8: 885b ldrh r3, [r3, #2]
80072ea: b2da uxtb r2, r3
80072ec: 4b41 ldr r3, [pc, #260] ; (80073f4 <USBD_SetConfig+0x118>)
80072ee: 701a strb r2, [r3, #0]
if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
80072f0: 4b40 ldr r3, [pc, #256] ; (80073f4 <USBD_SetConfig+0x118>)
80072f2: 781b ldrb r3, [r3, #0]
80072f4: 2b01 cmp r3, #1
80072f6: d904 bls.n 8007302 <USBD_SetConfig+0x26>
{
USBD_CtlError(pdev, req);
80072f8: 6839 ldr r1, [r7, #0]
80072fa: 6878 ldr r0, [r7, #4]
80072fc: f000 f954 bl 80075a8 <USBD_CtlError>
8007300: e075 b.n 80073ee <USBD_SetConfig+0x112>
}
else
{
switch (pdev->dev_state)
8007302: 687b ldr r3, [r7, #4]
8007304: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8007308: 2b02 cmp r3, #2
800730a: d002 beq.n 8007312 <USBD_SetConfig+0x36>
800730c: 2b03 cmp r3, #3
800730e: d023 beq.n 8007358 <USBD_SetConfig+0x7c>
8007310: e062 b.n 80073d8 <USBD_SetConfig+0xfc>
{
case USBD_STATE_ADDRESSED:
if (cfgidx)
8007312: 4b38 ldr r3, [pc, #224] ; (80073f4 <USBD_SetConfig+0x118>)
8007314: 781b ldrb r3, [r3, #0]
8007316: 2b00 cmp r3, #0
8007318: d01a beq.n 8007350 <USBD_SetConfig+0x74>
{
pdev->dev_config = cfgidx;
800731a: 4b36 ldr r3, [pc, #216] ; (80073f4 <USBD_SetConfig+0x118>)
800731c: 781b ldrb r3, [r3, #0]
800731e: 461a mov r2, r3
8007320: 687b ldr r3, [r7, #4]
8007322: 605a str r2, [r3, #4]
pdev->dev_state = USBD_STATE_CONFIGURED;
8007324: 687b ldr r3, [r7, #4]
8007326: 2203 movs r2, #3
8007328: f883 229c strb.w r2, [r3, #668] ; 0x29c
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
800732c: 4b31 ldr r3, [pc, #196] ; (80073f4 <USBD_SetConfig+0x118>)
800732e: 781b ldrb r3, [r3, #0]
8007330: 4619 mov r1, r3
8007332: 6878 ldr r0, [r7, #4]
8007334: f7ff f9f3 bl 800671e <USBD_SetClassConfig>
8007338: 4603 mov r3, r0
800733a: 2b02 cmp r3, #2
800733c: d104 bne.n 8007348 <USBD_SetConfig+0x6c>
{
USBD_CtlError(pdev, req);
800733e: 6839 ldr r1, [r7, #0]
8007340: 6878 ldr r0, [r7, #4]
8007342: f000 f931 bl 80075a8 <USBD_CtlError>
return;
8007346: e052 b.n 80073ee <USBD_SetConfig+0x112>
}
USBD_CtlSendStatus(pdev);
8007348: 6878 ldr r0, [r7, #4]
800734a: f000 f9f5 bl 8007738 <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
800734e: e04e b.n 80073ee <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
8007350: 6878 ldr r0, [r7, #4]
8007352: f000 f9f1 bl 8007738 <USBD_CtlSendStatus>
break;
8007356: e04a b.n 80073ee <USBD_SetConfig+0x112>
case USBD_STATE_CONFIGURED:
if (cfgidx == 0U)
8007358: 4b26 ldr r3, [pc, #152] ; (80073f4 <USBD_SetConfig+0x118>)
800735a: 781b ldrb r3, [r3, #0]
800735c: 2b00 cmp r3, #0
800735e: d112 bne.n 8007386 <USBD_SetConfig+0xaa>
{
pdev->dev_state = USBD_STATE_ADDRESSED;
8007360: 687b ldr r3, [r7, #4]
8007362: 2202 movs r2, #2
8007364: f883 229c strb.w r2, [r3, #668] ; 0x29c
pdev->dev_config = cfgidx;
8007368: 4b22 ldr r3, [pc, #136] ; (80073f4 <USBD_SetConfig+0x118>)
800736a: 781b ldrb r3, [r3, #0]
800736c: 461a mov r2, r3
800736e: 687b ldr r3, [r7, #4]
8007370: 605a str r2, [r3, #4]
USBD_ClrClassConfig(pdev, cfgidx);
8007372: 4b20 ldr r3, [pc, #128] ; (80073f4 <USBD_SetConfig+0x118>)
8007374: 781b ldrb r3, [r3, #0]
8007376: 4619 mov r1, r3
8007378: 6878 ldr r0, [r7, #4]
800737a: f7ff f9ef bl 800675c <USBD_ClrClassConfig>
USBD_CtlSendStatus(pdev);
800737e: 6878 ldr r0, [r7, #4]
8007380: f000 f9da bl 8007738 <USBD_CtlSendStatus>
}
else
{
USBD_CtlSendStatus(pdev);
}
break;
8007384: e033 b.n 80073ee <USBD_SetConfig+0x112>
else if (cfgidx != pdev->dev_config)
8007386: 4b1b ldr r3, [pc, #108] ; (80073f4 <USBD_SetConfig+0x118>)
8007388: 781b ldrb r3, [r3, #0]
800738a: 461a mov r2, r3
800738c: 687b ldr r3, [r7, #4]
800738e: 685b ldr r3, [r3, #4]
8007390: 429a cmp r2, r3
8007392: d01d beq.n 80073d0 <USBD_SetConfig+0xf4>
USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
8007394: 687b ldr r3, [r7, #4]
8007396: 685b ldr r3, [r3, #4]
8007398: b2db uxtb r3, r3
800739a: 4619 mov r1, r3
800739c: 6878 ldr r0, [r7, #4]
800739e: f7ff f9dd bl 800675c <USBD_ClrClassConfig>
pdev->dev_config = cfgidx;
80073a2: 4b14 ldr r3, [pc, #80] ; (80073f4 <USBD_SetConfig+0x118>)
80073a4: 781b ldrb r3, [r3, #0]
80073a6: 461a mov r2, r3
80073a8: 687b ldr r3, [r7, #4]
80073aa: 605a str r2, [r3, #4]
if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
80073ac: 4b11 ldr r3, [pc, #68] ; (80073f4 <USBD_SetConfig+0x118>)
80073ae: 781b ldrb r3, [r3, #0]
80073b0: 4619 mov r1, r3
80073b2: 6878 ldr r0, [r7, #4]
80073b4: f7ff f9b3 bl 800671e <USBD_SetClassConfig>
80073b8: 4603 mov r3, r0
80073ba: 2b02 cmp r3, #2
80073bc: d104 bne.n 80073c8 <USBD_SetConfig+0xec>
USBD_CtlError(pdev, req);
80073be: 6839 ldr r1, [r7, #0]
80073c0: 6878 ldr r0, [r7, #4]
80073c2: f000 f8f1 bl 80075a8 <USBD_CtlError>
return;
80073c6: e012 b.n 80073ee <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
80073c8: 6878 ldr r0, [r7, #4]
80073ca: f000 f9b5 bl 8007738 <USBD_CtlSendStatus>
break;
80073ce: e00e b.n 80073ee <USBD_SetConfig+0x112>
USBD_CtlSendStatus(pdev);
80073d0: 6878 ldr r0, [r7, #4]
80073d2: f000 f9b1 bl 8007738 <USBD_CtlSendStatus>
break;
80073d6: e00a b.n 80073ee <USBD_SetConfig+0x112>
default:
USBD_CtlError(pdev, req);
80073d8: 6839 ldr r1, [r7, #0]
80073da: 6878 ldr r0, [r7, #4]
80073dc: f000 f8e4 bl 80075a8 <USBD_CtlError>
USBD_ClrClassConfig(pdev, cfgidx);
80073e0: 4b04 ldr r3, [pc, #16] ; (80073f4 <USBD_SetConfig+0x118>)
80073e2: 781b ldrb r3, [r3, #0]
80073e4: 4619 mov r1, r3
80073e6: 6878 ldr r0, [r7, #4]
80073e8: f7ff f9b8 bl 800675c <USBD_ClrClassConfig>
break;
80073ec: bf00 nop
}
}
}
80073ee: 3708 adds r7, #8
80073f0: 46bd mov sp, r7
80073f2: bd80 pop {r7, pc}
80073f4: 20000590 .word 0x20000590
080073f8 <USBD_GetConfig>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
80073f8: b580 push {r7, lr}
80073fa: b082 sub sp, #8
80073fc: af00 add r7, sp, #0
80073fe: 6078 str r0, [r7, #4]
8007400: 6039 str r1, [r7, #0]
if (req->wLength != 1U)
8007402: 683b ldr r3, [r7, #0]
8007404: 88db ldrh r3, [r3, #6]
8007406: 2b01 cmp r3, #1
8007408: d004 beq.n 8007414 <USBD_GetConfig+0x1c>
{
USBD_CtlError(pdev, req);
800740a: 6839 ldr r1, [r7, #0]
800740c: 6878 ldr r0, [r7, #4]
800740e: f000 f8cb bl 80075a8 <USBD_CtlError>
default:
USBD_CtlError(pdev, req);
break;
}
}
}
8007412: e021 b.n 8007458 <USBD_GetConfig+0x60>
switch (pdev->dev_state)
8007414: 687b ldr r3, [r7, #4]
8007416: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
800741a: 2b01 cmp r3, #1
800741c: db17 blt.n 800744e <USBD_GetConfig+0x56>
800741e: 2b02 cmp r3, #2
8007420: dd02 ble.n 8007428 <USBD_GetConfig+0x30>
8007422: 2b03 cmp r3, #3
8007424: d00b beq.n 800743e <USBD_GetConfig+0x46>
8007426: e012 b.n 800744e <USBD_GetConfig+0x56>
pdev->dev_default_config = 0U;
8007428: 687b ldr r3, [r7, #4]
800742a: 2200 movs r2, #0
800742c: 609a str r2, [r3, #8]
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
800742e: 687b ldr r3, [r7, #4]
8007430: 3308 adds r3, #8
8007432: 2201 movs r2, #1
8007434: 4619 mov r1, r3
8007436: 6878 ldr r0, [r7, #4]
8007438: f000 f920 bl 800767c <USBD_CtlSendData>
break;
800743c: e00c b.n 8007458 <USBD_GetConfig+0x60>
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
800743e: 687b ldr r3, [r7, #4]
8007440: 3304 adds r3, #4
8007442: 2201 movs r2, #1
8007444: 4619 mov r1, r3
8007446: 6878 ldr r0, [r7, #4]
8007448: f000 f918 bl 800767c <USBD_CtlSendData>
break;
800744c: e004 b.n 8007458 <USBD_GetConfig+0x60>
USBD_CtlError(pdev, req);
800744e: 6839 ldr r1, [r7, #0]
8007450: 6878 ldr r0, [r7, #4]
8007452: f000 f8a9 bl 80075a8 <USBD_CtlError>
break;
8007456: bf00 nop
}
8007458: bf00 nop
800745a: 3708 adds r7, #8
800745c: 46bd mov sp, r7
800745e: bd80 pop {r7, pc}
08007460 <USBD_GetStatus>:
* @param pdev: device instance
* @param req: usb request
* @retval status
*/
static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
{
8007460: b580 push {r7, lr}
8007462: b082 sub sp, #8
8007464: af00 add r7, sp, #0
8007466: 6078 str r0, [r7, #4]
8007468: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
800746a: 687b ldr r3, [r7, #4]
800746c: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
8007470: 3b01 subs r3, #1
8007472: 2b02 cmp r3, #2
8007474: d81e bhi.n 80074b4 <USBD_GetStatus+0x54>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wLength != 0x2U)
8007476: 683b ldr r3, [r7, #0]
8007478: 88db ldrh r3, [r3, #6]
800747a: 2b02 cmp r3, #2
800747c: d004 beq.n 8007488 <USBD_GetStatus+0x28>
{
USBD_CtlError(pdev, req);
800747e: 6839 ldr r1, [r7, #0]
8007480: 6878 ldr r0, [r7, #4]
8007482: f000 f891 bl 80075a8 <USBD_CtlError>
break;
8007486: e01a b.n 80074be <USBD_GetStatus+0x5e>
}
#if (USBD_SELF_POWERED == 1U)
pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
8007488: 687b ldr r3, [r7, #4]
800748a: 2201 movs r2, #1
800748c: 60da str r2, [r3, #12]
#else
pdev->dev_config_status = 0U;
#endif
if (pdev->dev_remote_wakeup)
800748e: 687b ldr r3, [r7, #4]
8007490: f8d3 32a4 ldr.w r3, [r3, #676] ; 0x2a4
8007494: 2b00 cmp r3, #0
8007496: d005 beq.n 80074a4 <USBD_GetStatus+0x44>
{
pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
8007498: 687b ldr r3, [r7, #4]
800749a: 68db ldr r3, [r3, #12]
800749c: f043 0202 orr.w r2, r3, #2
80074a0: 687b ldr r3, [r7, #4]
80074a2: 60da str r2, [r3, #12]
}
USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
80074a4: 687b ldr r3, [r7, #4]
80074a6: 330c adds r3, #12
80074a8: 2202 movs r2, #2
80074aa: 4619 mov r1, r3
80074ac: 6878 ldr r0, [r7, #4]
80074ae: f000 f8e5 bl 800767c <USBD_CtlSendData>
break;
80074b2: e004 b.n 80074be <USBD_GetStatus+0x5e>
default:
USBD_CtlError(pdev, req);
80074b4: 6839 ldr r1, [r7, #0]
80074b6: 6878 ldr r0, [r7, #4]
80074b8: f000 f876 bl 80075a8 <USBD_CtlError>
break;
80074bc: bf00 nop
}
}
80074be: bf00 nop
80074c0: 3708 adds r7, #8
80074c2: 46bd mov sp, r7
80074c4: bd80 pop {r7, pc}
080074c6 <USBD_SetFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
80074c6: b580 push {r7, lr}
80074c8: b082 sub sp, #8
80074ca: af00 add r7, sp, #0
80074cc: 6078 str r0, [r7, #4]
80074ce: 6039 str r1, [r7, #0]
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
80074d0: 683b ldr r3, [r7, #0]
80074d2: 885b ldrh r3, [r3, #2]
80074d4: 2b01 cmp r3, #1
80074d6: d106 bne.n 80074e6 <USBD_SetFeature+0x20>
{
pdev->dev_remote_wakeup = 1U;
80074d8: 687b ldr r3, [r7, #4]
80074da: 2201 movs r2, #1
80074dc: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4
USBD_CtlSendStatus(pdev);
80074e0: 6878 ldr r0, [r7, #4]
80074e2: f000 f929 bl 8007738 <USBD_CtlSendStatus>
}
}
80074e6: bf00 nop
80074e8: 3708 adds r7, #8
80074ea: 46bd mov sp, r7
80074ec: bd80 pop {r7, pc}
080074ee <USBD_ClrFeature>:
* @param req: usb request
* @retval status
*/
static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
80074ee: b580 push {r7, lr}
80074f0: b082 sub sp, #8
80074f2: af00 add r7, sp, #0
80074f4: 6078 str r0, [r7, #4]
80074f6: 6039 str r1, [r7, #0]
switch (pdev->dev_state)
80074f8: 687b ldr r3, [r7, #4]
80074fa: f893 329c ldrb.w r3, [r3, #668] ; 0x29c
80074fe: 3b01 subs r3, #1
8007500: 2b02 cmp r3, #2
8007502: d80b bhi.n 800751c <USBD_ClrFeature+0x2e>
{
case USBD_STATE_DEFAULT:
case USBD_STATE_ADDRESSED:
case USBD_STATE_CONFIGURED:
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
8007504: 683b ldr r3, [r7, #0]
8007506: 885b ldrh r3, [r3, #2]
8007508: 2b01 cmp r3, #1
800750a: d10c bne.n 8007526 <USBD_ClrFeature+0x38>
{
pdev->dev_remote_wakeup = 0U;
800750c: 687b ldr r3, [r7, #4]
800750e: 2200 movs r2, #0
8007510: f8c3 22a4 str.w r2, [r3, #676] ; 0x2a4
USBD_CtlSendStatus(pdev);
8007514: 6878 ldr r0, [r7, #4]
8007516: f000 f90f bl 8007738 <USBD_CtlSendStatus>
}
break;
800751a: e004 b.n 8007526 <USBD_ClrFeature+0x38>
default:
USBD_CtlError(pdev, req);
800751c: 6839 ldr r1, [r7, #0]
800751e: 6878 ldr r0, [r7, #4]
8007520: f000 f842 bl 80075a8 <USBD_CtlError>
break;
8007524: e000 b.n 8007528 <USBD_ClrFeature+0x3a>
break;
8007526: bf00 nop
}
}
8007528: bf00 nop
800752a: 3708 adds r7, #8
800752c: 46bd mov sp, r7
800752e: bd80 pop {r7, pc}
08007530 <USBD_ParseSetupRequest>:
* @param req: usb request
* @retval None
*/
void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
{
8007530: b480 push {r7}
8007532: b083 sub sp, #12
8007534: af00 add r7, sp, #0
8007536: 6078 str r0, [r7, #4]
8007538: 6039 str r1, [r7, #0]
req->bmRequest = *(uint8_t *)(pdata);
800753a: 683b ldr r3, [r7, #0]
800753c: 781a ldrb r2, [r3, #0]
800753e: 687b ldr r3, [r7, #4]
8007540: 701a strb r2, [r3, #0]
req->bRequest = *(uint8_t *)(pdata + 1U);
8007542: 683b ldr r3, [r7, #0]
8007544: 785a ldrb r2, [r3, #1]
8007546: 687b ldr r3, [r7, #4]
8007548: 705a strb r2, [r3, #1]
req->wValue = SWAPBYTE(pdata + 2U);
800754a: 683b ldr r3, [r7, #0]
800754c: 3302 adds r3, #2
800754e: 781b ldrb r3, [r3, #0]
8007550: b29a uxth r2, r3
8007552: 683b ldr r3, [r7, #0]
8007554: 3303 adds r3, #3
8007556: 781b ldrb r3, [r3, #0]
8007558: b29b uxth r3, r3
800755a: 021b lsls r3, r3, #8
800755c: b29b uxth r3, r3
800755e: 4413 add r3, r2
8007560: b29a uxth r2, r3
8007562: 687b ldr r3, [r7, #4]
8007564: 805a strh r2, [r3, #2]
req->wIndex = SWAPBYTE(pdata + 4U);
8007566: 683b ldr r3, [r7, #0]
8007568: 3304 adds r3, #4
800756a: 781b ldrb r3, [r3, #0]
800756c: b29a uxth r2, r3
800756e: 683b ldr r3, [r7, #0]
8007570: 3305 adds r3, #5
8007572: 781b ldrb r3, [r3, #0]
8007574: b29b uxth r3, r3
8007576: 021b lsls r3, r3, #8
8007578: b29b uxth r3, r3
800757a: 4413 add r3, r2
800757c: b29a uxth r2, r3
800757e: 687b ldr r3, [r7, #4]
8007580: 809a strh r2, [r3, #4]
req->wLength = SWAPBYTE(pdata + 6U);
8007582: 683b ldr r3, [r7, #0]
8007584: 3306 adds r3, #6
8007586: 781b ldrb r3, [r3, #0]
8007588: b29a uxth r2, r3
800758a: 683b ldr r3, [r7, #0]
800758c: 3307 adds r3, #7
800758e: 781b ldrb r3, [r3, #0]
8007590: b29b uxth r3, r3
8007592: 021b lsls r3, r3, #8
8007594: b29b uxth r3, r3
8007596: 4413 add r3, r2
8007598: b29a uxth r2, r3
800759a: 687b ldr r3, [r7, #4]
800759c: 80da strh r2, [r3, #6]
}
800759e: bf00 nop
80075a0: 370c adds r7, #12
80075a2: 46bd mov sp, r7
80075a4: bc80 pop {r7}
80075a6: 4770 bx lr
080075a8 <USBD_CtlError>:
* @retval None
*/
void USBD_CtlError(USBD_HandleTypeDef *pdev,
USBD_SetupReqTypedef *req)
{
80075a8: b580 push {r7, lr}
80075aa: b082 sub sp, #8
80075ac: af00 add r7, sp, #0
80075ae: 6078 str r0, [r7, #4]
80075b0: 6039 str r1, [r7, #0]
USBD_LL_StallEP(pdev, 0x80U);
80075b2: 2180 movs r1, #128 ; 0x80
80075b4: 6878 ldr r0, [r7, #4]
80075b6: f000 fc6f bl 8007e98 <USBD_LL_StallEP>
USBD_LL_StallEP(pdev, 0U);
80075ba: 2100 movs r1, #0
80075bc: 6878 ldr r0, [r7, #4]
80075be: f000 fc6b bl 8007e98 <USBD_LL_StallEP>
}
80075c2: bf00 nop
80075c4: 3708 adds r7, #8
80075c6: 46bd mov sp, r7
80075c8: bd80 pop {r7, pc}
080075ca <USBD_GetString>:
* @param unicode : Formatted string buffer (unicode)
* @param len : descriptor length
* @retval None
*/
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
{
80075ca: b580 push {r7, lr}
80075cc: b086 sub sp, #24
80075ce: af00 add r7, sp, #0
80075d0: 60f8 str r0, [r7, #12]
80075d2: 60b9 str r1, [r7, #8]
80075d4: 607a str r2, [r7, #4]
uint8_t idx = 0U;
80075d6: 2300 movs r3, #0
80075d8: 75fb strb r3, [r7, #23]
if (desc != NULL)
80075da: 68fb ldr r3, [r7, #12]
80075dc: 2b00 cmp r3, #0
80075de: d032 beq.n 8007646 <USBD_GetString+0x7c>
{
*len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
80075e0: 68f8 ldr r0, [r7, #12]
80075e2: f000 f834 bl 800764e <USBD_GetLen>
80075e6: 4603 mov r3, r0
80075e8: 3301 adds r3, #1
80075ea: b29b uxth r3, r3
80075ec: 005b lsls r3, r3, #1
80075ee: b29a uxth r2, r3
80075f0: 687b ldr r3, [r7, #4]
80075f2: 801a strh r2, [r3, #0]
unicode[idx++] = *(uint8_t *)(void *)len;
80075f4: 7dfb ldrb r3, [r7, #23]
80075f6: 1c5a adds r2, r3, #1
80075f8: 75fa strb r2, [r7, #23]
80075fa: 461a mov r2, r3
80075fc: 68bb ldr r3, [r7, #8]
80075fe: 4413 add r3, r2
8007600: 687a ldr r2, [r7, #4]
8007602: 7812 ldrb r2, [r2, #0]
8007604: 701a strb r2, [r3, #0]
unicode[idx++] = USB_DESC_TYPE_STRING;
8007606: 7dfb ldrb r3, [r7, #23]
8007608: 1c5a adds r2, r3, #1
800760a: 75fa strb r2, [r7, #23]
800760c: 461a mov r2, r3
800760e: 68bb ldr r3, [r7, #8]
8007610: 4413 add r3, r2
8007612: 2203 movs r2, #3
8007614: 701a strb r2, [r3, #0]
while (*desc != '\0')
8007616: e012 b.n 800763e <USBD_GetString+0x74>
{
unicode[idx++] = *desc++;
8007618: 68fb ldr r3, [r7, #12]
800761a: 1c5a adds r2, r3, #1
800761c: 60fa str r2, [r7, #12]
800761e: 7dfa ldrb r2, [r7, #23]
8007620: 1c51 adds r1, r2, #1
8007622: 75f9 strb r1, [r7, #23]
8007624: 4611 mov r1, r2
8007626: 68ba ldr r2, [r7, #8]
8007628: 440a add r2, r1
800762a: 781b ldrb r3, [r3, #0]
800762c: 7013 strb r3, [r2, #0]
unicode[idx++] = 0U;
800762e: 7dfb ldrb r3, [r7, #23]
8007630: 1c5a adds r2, r3, #1
8007632: 75fa strb r2, [r7, #23]
8007634: 461a mov r2, r3
8007636: 68bb ldr r3, [r7, #8]
8007638: 4413 add r3, r2
800763a: 2200 movs r2, #0
800763c: 701a strb r2, [r3, #0]
while (*desc != '\0')
800763e: 68fb ldr r3, [r7, #12]
8007640: 781b ldrb r3, [r3, #0]
8007642: 2b00 cmp r3, #0
8007644: d1e8 bne.n 8007618 <USBD_GetString+0x4e>
}
}
}
8007646: bf00 nop
8007648: 3718 adds r7, #24
800764a: 46bd mov sp, r7
800764c: bd80 pop {r7, pc}
0800764e <USBD_GetLen>:
* return the string length
* @param buf : pointer to the ascii string buffer
* @retval string length
*/
static uint8_t USBD_GetLen(uint8_t *buf)
{
800764e: b480 push {r7}
8007650: b085 sub sp, #20
8007652: af00 add r7, sp, #0
8007654: 6078 str r0, [r7, #4]
uint8_t len = 0U;
8007656: 2300 movs r3, #0
8007658: 73fb strb r3, [r7, #15]
while (*buf != '\0')
800765a: e005 b.n 8007668 <USBD_GetLen+0x1a>
{
len++;
800765c: 7bfb ldrb r3, [r7, #15]
800765e: 3301 adds r3, #1
8007660: 73fb strb r3, [r7, #15]
buf++;
8007662: 687b ldr r3, [r7, #4]
8007664: 3301 adds r3, #1
8007666: 607b str r3, [r7, #4]
while (*buf != '\0')
8007668: 687b ldr r3, [r7, #4]
800766a: 781b ldrb r3, [r3, #0]
800766c: 2b00 cmp r3, #0
800766e: d1f5 bne.n 800765c <USBD_GetLen+0xe>
}
return len;
8007670: 7bfb ldrb r3, [r7, #15]
}
8007672: 4618 mov r0, r3
8007674: 3714 adds r7, #20
8007676: 46bd mov sp, r7
8007678: bc80 pop {r7}
800767a: 4770 bx lr
0800767c <USBD_CtlSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
800767c: b580 push {r7, lr}
800767e: b084 sub sp, #16
8007680: af00 add r7, sp, #0
8007682: 60f8 str r0, [r7, #12]
8007684: 60b9 str r1, [r7, #8]
8007686: 4613 mov r3, r2
8007688: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN;
800768a: 68fb ldr r3, [r7, #12]
800768c: 2202 movs r2, #2
800768e: f8c3 2294 str.w r2, [r3, #660] ; 0x294
pdev->ep_in[0].total_length = len;
8007692: 88fa ldrh r2, [r7, #6]
8007694: 68fb ldr r3, [r7, #12]
8007696: 61da str r2, [r3, #28]
pdev->ep_in[0].rem_length = len;
8007698: 88fa ldrh r2, [r7, #6]
800769a: 68fb ldr r3, [r7, #12]
800769c: 621a str r2, [r3, #32]
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
800769e: 88fb ldrh r3, [r7, #6]
80076a0: 68ba ldr r2, [r7, #8]
80076a2: 2100 movs r1, #0
80076a4: 68f8 ldr r0, [r7, #12]
80076a6: f000 fc79 bl 8007f9c <USBD_LL_Transmit>
return USBD_OK;
80076aa: 2300 movs r3, #0
}
80076ac: 4618 mov r0, r3
80076ae: 3710 adds r7, #16
80076b0: 46bd mov sp, r7
80076b2: bd80 pop {r7, pc}
080076b4 <USBD_CtlContinueSendData>:
* @param len: length of data to be sent
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
80076b4: b580 push {r7, lr}
80076b6: b084 sub sp, #16
80076b8: af00 add r7, sp, #0
80076ba: 60f8 str r0, [r7, #12]
80076bc: 60b9 str r1, [r7, #8]
80076be: 4613 mov r3, r2
80076c0: 80fb strh r3, [r7, #6]
/* Start the next transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
80076c2: 88fb ldrh r3, [r7, #6]
80076c4: 68ba ldr r2, [r7, #8]
80076c6: 2100 movs r1, #0
80076c8: 68f8 ldr r0, [r7, #12]
80076ca: f000 fc67 bl 8007f9c <USBD_LL_Transmit>
return USBD_OK;
80076ce: 2300 movs r3, #0
}
80076d0: 4618 mov r0, r3
80076d2: 3710 adds r7, #16
80076d4: 46bd mov sp, r7
80076d6: bd80 pop {r7, pc}
080076d8 <USBD_CtlPrepareRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
80076d8: b580 push {r7, lr}
80076da: b084 sub sp, #16
80076dc: af00 add r7, sp, #0
80076de: 60f8 str r0, [r7, #12]
80076e0: 60b9 str r1, [r7, #8]
80076e2: 4613 mov r3, r2
80076e4: 80fb strh r3, [r7, #6]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT;
80076e6: 68fb ldr r3, [r7, #12]
80076e8: 2203 movs r2, #3
80076ea: f8c3 2294 str.w r2, [r3, #660] ; 0x294
pdev->ep_out[0].total_length = len;
80076ee: 88fa ldrh r2, [r7, #6]
80076f0: 68fb ldr r3, [r7, #12]
80076f2: f8c3 215c str.w r2, [r3, #348] ; 0x15c
pdev->ep_out[0].rem_length = len;
80076f6: 88fa ldrh r2, [r7, #6]
80076f8: 68fb ldr r3, [r7, #12]
80076fa: f8c3 2160 str.w r2, [r3, #352] ; 0x160
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
80076fe: 88fb ldrh r3, [r7, #6]
8007700: 68ba ldr r2, [r7, #8]
8007702: 2100 movs r1, #0
8007704: 68f8 ldr r0, [r7, #12]
8007706: f000 fc6c bl 8007fe2 <USBD_LL_PrepareReceive>
return USBD_OK;
800770a: 2300 movs r3, #0
}
800770c: 4618 mov r0, r3
800770e: 3710 adds r7, #16
8007710: 46bd mov sp, r7
8007712: bd80 pop {r7, pc}
08007714 <USBD_CtlContinueRx>:
* @param len: length of data to be received
* @retval status
*/
USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint16_t len)
{
8007714: b580 push {r7, lr}
8007716: b084 sub sp, #16
8007718: af00 add r7, sp, #0
800771a: 60f8 str r0, [r7, #12]
800771c: 60b9 str r1, [r7, #8]
800771e: 4613 mov r3, r2
8007720: 80fb strh r3, [r7, #6]
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
8007722: 88fb ldrh r3, [r7, #6]
8007724: 68ba ldr r2, [r7, #8]
8007726: 2100 movs r1, #0
8007728: 68f8 ldr r0, [r7, #12]
800772a: f000 fc5a bl 8007fe2 <USBD_LL_PrepareReceive>
return USBD_OK;
800772e: 2300 movs r3, #0
}
8007730: 4618 mov r0, r3
8007732: 3710 adds r7, #16
8007734: 46bd mov sp, r7
8007736: bd80 pop {r7, pc}
08007738 <USBD_CtlSendStatus>:
* send zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{
8007738: b580 push {r7, lr}
800773a: b082 sub sp, #8
800773c: af00 add r7, sp, #0
800773e: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN;
8007740: 687b ldr r3, [r7, #4]
8007742: 2204 movs r2, #4
8007744: f8c3 2294 str.w r2, [r3, #660] ; 0x294
/* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
8007748: 2300 movs r3, #0
800774a: 2200 movs r2, #0
800774c: 2100 movs r1, #0
800774e: 6878 ldr r0, [r7, #4]
8007750: f000 fc24 bl 8007f9c <USBD_LL_Transmit>
return USBD_OK;
8007754: 2300 movs r3, #0
}
8007756: 4618 mov r0, r3
8007758: 3708 adds r7, #8
800775a: 46bd mov sp, r7
800775c: bd80 pop {r7, pc}
0800775e <USBD_CtlReceiveStatus>:
* receive zero lzngth packet on the ctl pipe
* @param pdev: device instance
* @retval status
*/
USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{
800775e: b580 push {r7, lr}
8007760: b082 sub sp, #8
8007762: af00 add r7, sp, #0
8007764: 6078 str r0, [r7, #4]
/* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT;
8007766: 687b ldr r3, [r7, #4]
8007768: 2205 movs r2, #5
800776a: f8c3 2294 str.w r2, [r3, #660] ; 0x294
/* Start the transfer */
USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
800776e: 2300 movs r3, #0
8007770: 2200 movs r2, #0
8007772: 2100 movs r1, #0
8007774: 6878 ldr r0, [r7, #4]
8007776: f000 fc34 bl 8007fe2 <USBD_LL_PrepareReceive>
return USBD_OK;
800777a: 2300 movs r3, #0
}
800777c: 4618 mov r0, r3
800777e: 3708 adds r7, #8
8007780: 46bd mov sp, r7
8007782: bd80 pop {r7, pc}
08007784 <MX_USB_DEVICE_Init>:
/**
* Init USB device Library, add supported class and start the library
* @retval None
*/
void MX_USB_DEVICE_Init(void)
{
8007784: b580 push {r7, lr}
8007786: af00 add r7, sp, #0
/* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
/* USER CODE END USB_DEVICE_Init_PreTreatment */
/* Init Device Library, add supported class and start the library. */
if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
8007788: 2200 movs r2, #0
800778a: 4912 ldr r1, [pc, #72] ; (80077d4 <MX_USB_DEVICE_Init+0x50>)
800778c: 4812 ldr r0, [pc, #72] ; (80077d8 <MX_USB_DEVICE_Init+0x54>)
800778e: f7fe ff6c bl 800666a <USBD_Init>
8007792: 4603 mov r3, r0
8007794: 2b00 cmp r3, #0
8007796: d001 beq.n 800779c <MX_USB_DEVICE_Init+0x18>
{
Error_Handler();
8007798: f7f9 fc2e bl 8000ff8 <Error_Handler>
}
if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
800779c: 490f ldr r1, [pc, #60] ; (80077dc <MX_USB_DEVICE_Init+0x58>)
800779e: 480e ldr r0, [pc, #56] ; (80077d8 <MX_USB_DEVICE_Init+0x54>)
80077a0: f7fe ff8e bl 80066c0 <USBD_RegisterClass>
80077a4: 4603 mov r3, r0
80077a6: 2b00 cmp r3, #0
80077a8: d001 beq.n 80077ae <MX_USB_DEVICE_Init+0x2a>
{
Error_Handler();
80077aa: f7f9 fc25 bl 8000ff8 <Error_Handler>
}
if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)
80077ae: 490c ldr r1, [pc, #48] ; (80077e0 <MX_USB_DEVICE_Init+0x5c>)
80077b0: 4809 ldr r0, [pc, #36] ; (80077d8 <MX_USB_DEVICE_Init+0x54>)
80077b2: f7fe febf bl 8006534 <USBD_CDC_RegisterInterface>
80077b6: 4603 mov r3, r0
80077b8: 2b00 cmp r3, #0
80077ba: d001 beq.n 80077c0 <MX_USB_DEVICE_Init+0x3c>
{
Error_Handler();
80077bc: f7f9 fc1c bl 8000ff8 <Error_Handler>
}
if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
80077c0: 4805 ldr r0, [pc, #20] ; (80077d8 <MX_USB_DEVICE_Init+0x54>)
80077c2: f7fe ff96 bl 80066f2 <USBD_Start>
80077c6: 4603 mov r3, r0
80077c8: 2b00 cmp r3, #0
80077ca: d001 beq.n 80077d0 <MX_USB_DEVICE_Init+0x4c>
{
Error_Handler();
80077cc: f7f9 fc14 bl 8000ff8 <Error_Handler>
}
/* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
/* USER CODE END USB_DEVICE_Init_PostTreatment */
}
80077d0: bf00 nop
80077d2: bd80 pop {r7, pc}
80077d4: 20000138 .word 0x20000138
80077d8: 20000d54 .word 0x20000d54
80077dc: 20000024 .word 0x20000024
80077e0: 20000128 .word 0x20000128
080077e4 <CDC_Init_FS>:
/**
* @brief Initializes the CDC media low layer over the FS USB IP
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Init_FS(void)
{
80077e4: b580 push {r7, lr}
80077e6: af00 add r7, sp, #0
/* USER CODE BEGIN 3 */
/* Set Application Buffers */
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
80077e8: 2200 movs r2, #0
80077ea: 4905 ldr r1, [pc, #20] ; (8007800 <CDC_Init_FS+0x1c>)
80077ec: 4805 ldr r0, [pc, #20] ; (8007804 <CDC_Init_FS+0x20>)
80077ee: f7fe feb7 bl 8006560 <USBD_CDC_SetTxBuffer>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS);
80077f2: 4905 ldr r1, [pc, #20] ; (8007808 <CDC_Init_FS+0x24>)
80077f4: 4803 ldr r0, [pc, #12] ; (8007804 <CDC_Init_FS+0x20>)
80077f6: f7fe fecc bl 8006592 <USBD_CDC_SetRxBuffer>
return (USBD_OK);
80077fa: 2300 movs r3, #0
/* USER CODE END 3 */
}
80077fc: 4618 mov r0, r3
80077fe: bd80 pop {r7, pc}
8007800: 20001400 .word 0x20001400
8007804: 20000d54 .word 0x20000d54
8007808: 20001018 .word 0x20001018
0800780c <CDC_DeInit_FS>:
/**
* @brief DeInitializes the CDC media low layer
* @retval USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_DeInit_FS(void)
{
800780c: b480 push {r7}
800780e: af00 add r7, sp, #0
/* USER CODE BEGIN 4 */
return (USBD_OK);
8007810: 2300 movs r3, #0
/* USER CODE END 4 */
}
8007812: 4618 mov r0, r3
8007814: 46bd mov sp, r7
8007816: bc80 pop {r7}
8007818: 4770 bx lr
...
0800781c <CDC_Control_FS>:
* @param pbuf: Buffer containing command data (request parameters)
* @param length: Number of data to be sent (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
{
800781c: b580 push {r7, lr}
800781e: b082 sub sp, #8
8007820: af00 add r7, sp, #0
8007822: 4603 mov r3, r0
8007824: 6039 str r1, [r7, #0]
8007826: 71fb strb r3, [r7, #7]
8007828: 4613 mov r3, r2
800782a: 80bb strh r3, [r7, #4]
/* USER CODE BEGIN 5 */
switch(cmd)
800782c: 79fb ldrb r3, [r7, #7]
800782e: 2b23 cmp r3, #35 ; 0x23
8007830: d866 bhi.n 8007900 <CDC_Control_FS+0xe4>
8007832: a201 add r2, pc, #4 ; (adr r2, 8007838 <CDC_Control_FS+0x1c>)
8007834: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007838: 08007901 .word 0x08007901
800783c: 08007901 .word 0x08007901
8007840: 08007901 .word 0x08007901
8007844: 08007901 .word 0x08007901
8007848: 08007901 .word 0x08007901
800784c: 08007901 .word 0x08007901
8007850: 08007901 .word 0x08007901
8007854: 08007901 .word 0x08007901
8007858: 08007901 .word 0x08007901
800785c: 08007901 .word 0x08007901
8007860: 08007901 .word 0x08007901
8007864: 08007901 .word 0x08007901
8007868: 08007901 .word 0x08007901
800786c: 08007901 .word 0x08007901
8007870: 08007901 .word 0x08007901
8007874: 08007901 .word 0x08007901
8007878: 08007901 .word 0x08007901
800787c: 08007901 .word 0x08007901
8007880: 08007901 .word 0x08007901
8007884: 08007901 .word 0x08007901
8007888: 08007901 .word 0x08007901
800788c: 08007901 .word 0x08007901
8007890: 08007901 .word 0x08007901
8007894: 08007901 .word 0x08007901
8007898: 08007901 .word 0x08007901
800789c: 08007901 .word 0x08007901
80078a0: 08007901 .word 0x08007901
80078a4: 08007901 .word 0x08007901
80078a8: 08007901 .word 0x08007901
80078ac: 08007901 .word 0x08007901
80078b0: 08007901 .word 0x08007901
80078b4: 08007901 .word 0x08007901
80078b8: 080078c9 .word 0x080078c9
80078bc: 080078eb .word 0x080078eb
80078c0: 08007901 .word 0x08007901
80078c4: 08007901 .word 0x08007901
/* 3 - Mark */
/* 4 - Space */
/* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */
/*******************************************************************************/
case CDC_SET_LINE_CODING:
memcpy(&linecode,pbuf,length>sizeof(linecode)?(sizeof(linecode)):(length));
80078c8: 88bb ldrh r3, [r7, #4]
80078ca: 2b0c cmp r3, #12
80078cc: bf28 it cs
80078ce: 230c movcs r3, #12
80078d0: b29b uxth r3, r3
80078d2: 461a mov r2, r3
80078d4: 6839 ldr r1, [r7, #0]
80078d6: 480d ldr r0, [pc, #52] ; (800790c <CDC_Control_FS+0xf0>)
80078d8: f000 fc2a bl 8008130 <memcpy>
linecode.IsUpdate++;
80078dc: 4b0b ldr r3, [pc, #44] ; (800790c <CDC_Control_FS+0xf0>)
80078de: 7a1b ldrb r3, [r3, #8]
80078e0: 3301 adds r3, #1
80078e2: b2da uxtb r2, r3
80078e4: 4b09 ldr r3, [pc, #36] ; (800790c <CDC_Control_FS+0xf0>)
80078e6: 721a strb r2, [r3, #8]
break;
80078e8: e00b b.n 8007902 <CDC_Control_FS+0xe6>
case CDC_GET_LINE_CODING:
memcpy(pbuf,&linecode,length>sizeof(linecode)?(sizeof(linecode)):(length));
80078ea: 88bb ldrh r3, [r7, #4]
80078ec: 2b0c cmp r3, #12
80078ee: bf28 it cs
80078f0: 230c movcs r3, #12
80078f2: b29b uxth r3, r3
80078f4: 461a mov r2, r3
80078f6: 4905 ldr r1, [pc, #20] ; (800790c <CDC_Control_FS+0xf0>)
80078f8: 6838 ldr r0, [r7, #0]
80078fa: f000 fc19 bl 8008130 <memcpy>
break;
80078fe: e000 b.n 8007902 <CDC_Control_FS+0xe6>
case CDC_SEND_BREAK:
break;
default:
break;
8007900: bf00 nop
}
return (USBD_OK);
8007902: 2300 movs r3, #0
/* USER CODE END 5 */
}
8007904: 4618 mov r0, r3
8007906: 3708 adds r7, #8
8007908: 46bd mov sp, r7
800790a: bd80 pop {r7, pc}
800790c: 20000000 .word 0x20000000
08007910 <CDC_Receive_FS>:
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)
* @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
*/
static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
{
8007910: b580 push {r7, lr}
8007912: b082 sub sp, #8
8007914: af00 add r7, sp, #0
8007916: 6078 str r0, [r7, #4]
8007918: 6039 str r1, [r7, #0]
/* USER CODE BEGIN 6 */
cdc_receive_call(Buf, *Len);
800791a: 683b ldr r3, [r7, #0]
800791c: 681b ldr r3, [r3, #0]
800791e: 4619 mov r1, r3
8007920: 6878 ldr r0, [r7, #4]
8007922: f7f9 f8b1 bl 8000a88 <cdc_receive_call>
USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
8007926: 6879 ldr r1, [r7, #4]
8007928: 4805 ldr r0, [pc, #20] ; (8007940 <CDC_Receive_FS+0x30>)
800792a: f7fe fe32 bl 8006592 <USBD_CDC_SetRxBuffer>
USBD_CDC_ReceivePacket(&hUsbDeviceFS);
800792e: 4804 ldr r0, [pc, #16] ; (8007940 <CDC_Receive_FS+0x30>)
8007930: f7fe fe71 bl 8006616 <USBD_CDC_ReceivePacket>
return (USBD_OK);
8007934: 2300 movs r3, #0
/* USER CODE END 6 */
}
8007936: 4618 mov r0, r3
8007938: 3708 adds r7, #8
800793a: 46bd mov sp, r7
800793c: bd80 pop {r7, pc}
800793e: bf00 nop
8007940: 20000d54 .word 0x20000d54
08007944 <CDC_Transmit_FS>:
* @param Buf: Buffer of data to be sent
* @param Len: Number of data to be sent (in bytes)
* @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
*/
uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
{
8007944: b580 push {r7, lr}
8007946: b084 sub sp, #16
8007948: af00 add r7, sp, #0
800794a: 6078 str r0, [r7, #4]
800794c: 460b mov r3, r1
800794e: 807b strh r3, [r7, #2]
uint8_t result = USBD_OK;
8007950: 2300 movs r3, #0
8007952: 73fb strb r3, [r7, #15]
/* USER CODE BEGIN 7 */
USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
8007954: 4b0d ldr r3, [pc, #52] ; (800798c <CDC_Transmit_FS+0x48>)
8007956: f8d3 32b8 ldr.w r3, [r3, #696] ; 0x2b8
800795a: 60bb str r3, [r7, #8]
if (hcdc->TxState != 0){
800795c: 68bb ldr r3, [r7, #8]
800795e: f8d3 3214 ldr.w r3, [r3, #532] ; 0x214
8007962: 2b00 cmp r3, #0
8007964: d001 beq.n 800796a <CDC_Transmit_FS+0x26>
return USBD_BUSY;
8007966: 2301 movs r3, #1
8007968: e00b b.n 8007982 <CDC_Transmit_FS+0x3e>
}
USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
800796a: 887b ldrh r3, [r7, #2]
800796c: 461a mov r2, r3
800796e: 6879 ldr r1, [r7, #4]
8007970: 4806 ldr r0, [pc, #24] ; (800798c <CDC_Transmit_FS+0x48>)
8007972: f7fe fdf5 bl 8006560 <USBD_CDC_SetTxBuffer>
result = USBD_CDC_TransmitPacket(&hUsbDeviceFS);
8007976: 4805 ldr r0, [pc, #20] ; (800798c <CDC_Transmit_FS+0x48>)
8007978: f7fe fe1e bl 80065b8 <USBD_CDC_TransmitPacket>
800797c: 4603 mov r3, r0
800797e: 73fb strb r3, [r7, #15]
/* USER CODE END 7 */
return result;
8007980: 7bfb ldrb r3, [r7, #15]
}
8007982: 4618 mov r0, r3
8007984: 3710 adds r7, #16
8007986: 46bd mov sp, r7
8007988: bd80 pop {r7, pc}
800798a: bf00 nop
800798c: 20000d54 .word 0x20000d54
08007990 <USBD_FS_DeviceDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8007990: b480 push {r7}
8007992: b083 sub sp, #12
8007994: af00 add r7, sp, #0
8007996: 4603 mov r3, r0
8007998: 6039 str r1, [r7, #0]
800799a: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc);
800799c: 683b ldr r3, [r7, #0]
800799e: 2212 movs r2, #18
80079a0: 801a strh r2, [r3, #0]
return USBD_FS_DeviceDesc;
80079a2: 4b03 ldr r3, [pc, #12] ; (80079b0 <USBD_FS_DeviceDescriptor+0x20>)
}
80079a4: 4618 mov r0, r3
80079a6: 370c adds r7, #12
80079a8: 46bd mov sp, r7
80079aa: bc80 pop {r7}
80079ac: 4770 bx lr
80079ae: bf00 nop
80079b0: 20000154 .word 0x20000154
080079b4 <USBD_FS_LangIDStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80079b4: b480 push {r7}
80079b6: b083 sub sp, #12
80079b8: af00 add r7, sp, #0
80079ba: 4603 mov r3, r0
80079bc: 6039 str r1, [r7, #0]
80079be: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc);
80079c0: 683b ldr r3, [r7, #0]
80079c2: 2204 movs r2, #4
80079c4: 801a strh r2, [r3, #0]
return USBD_LangIDDesc;
80079c6: 4b03 ldr r3, [pc, #12] ; (80079d4 <USBD_FS_LangIDStrDescriptor+0x20>)
}
80079c8: 4618 mov r0, r3
80079ca: 370c adds r7, #12
80079cc: 46bd mov sp, r7
80079ce: bc80 pop {r7}
80079d0: 4770 bx lr
80079d2: bf00 nop
80079d4: 20000168 .word 0x20000168
080079d8 <USBD_FS_ProductStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
80079d8: b580 push {r7, lr}
80079da: b082 sub sp, #8
80079dc: af00 add r7, sp, #0
80079de: 4603 mov r3, r0
80079e0: 6039 str r1, [r7, #0]
80079e2: 71fb strb r3, [r7, #7]
if(speed == 0)
80079e4: 79fb ldrb r3, [r7, #7]
80079e6: 2b00 cmp r3, #0
80079e8: d105 bne.n 80079f6 <USBD_FS_ProductStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
80079ea: 683a ldr r2, [r7, #0]
80079ec: 4907 ldr r1, [pc, #28] ; (8007a0c <USBD_FS_ProductStrDescriptor+0x34>)
80079ee: 4808 ldr r0, [pc, #32] ; (8007a10 <USBD_FS_ProductStrDescriptor+0x38>)
80079f0: f7ff fdeb bl 80075ca <USBD_GetString>
80079f4: e004 b.n 8007a00 <USBD_FS_ProductStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
80079f6: 683a ldr r2, [r7, #0]
80079f8: 4904 ldr r1, [pc, #16] ; (8007a0c <USBD_FS_ProductStrDescriptor+0x34>)
80079fa: 4805 ldr r0, [pc, #20] ; (8007a10 <USBD_FS_ProductStrDescriptor+0x38>)
80079fc: f7ff fde5 bl 80075ca <USBD_GetString>
}
return USBD_StrDesc;
8007a00: 4b02 ldr r3, [pc, #8] ; (8007a0c <USBD_FS_ProductStrDescriptor+0x34>)
}
8007a02: 4618 mov r0, r3
8007a04: 3708 adds r7, #8
8007a06: 46bd mov sp, r7
8007a08: bd80 pop {r7, pc}
8007a0a: bf00 nop
8007a0c: 200017e8 .word 0x200017e8
8007a10: 08008184 .word 0x08008184
08007a14 <USBD_FS_ManufacturerStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8007a14: b580 push {r7, lr}
8007a16: b082 sub sp, #8
8007a18: af00 add r7, sp, #0
8007a1a: 4603 mov r3, r0
8007a1c: 6039 str r1, [r7, #0]
8007a1e: 71fb strb r3, [r7, #7]
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
8007a20: 683a ldr r2, [r7, #0]
8007a22: 4904 ldr r1, [pc, #16] ; (8007a34 <USBD_FS_ManufacturerStrDescriptor+0x20>)
8007a24: 4804 ldr r0, [pc, #16] ; (8007a38 <USBD_FS_ManufacturerStrDescriptor+0x24>)
8007a26: f7ff fdd0 bl 80075ca <USBD_GetString>
return USBD_StrDesc;
8007a2a: 4b02 ldr r3, [pc, #8] ; (8007a34 <USBD_FS_ManufacturerStrDescriptor+0x20>)
}
8007a2c: 4618 mov r0, r3
8007a2e: 3708 adds r7, #8
8007a30: 46bd mov sp, r7
8007a32: bd80 pop {r7, pc}
8007a34: 200017e8 .word 0x200017e8
8007a38: 08008184 .word 0x08008184
08007a3c <USBD_FS_SerialStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8007a3c: b580 push {r7, lr}
8007a3e: b082 sub sp, #8
8007a40: af00 add r7, sp, #0
8007a42: 4603 mov r3, r0
8007a44: 6039 str r1, [r7, #0]
8007a46: 71fb strb r3, [r7, #7]
UNUSED(speed);
*length = USB_SIZ_STRING_SERIAL;
8007a48: 683b ldr r3, [r7, #0]
8007a4a: 221a movs r2, #26
8007a4c: 801a strh r2, [r3, #0]
/* Update the serial number string descriptor with the data from the unique
* ID */
Get_SerialNum();
8007a4e: f000 f843 bl 8007ad8 <Get_SerialNum>
/* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
/* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
8007a52: 4b02 ldr r3, [pc, #8] ; (8007a5c <USBD_FS_SerialStrDescriptor+0x20>)
}
8007a54: 4618 mov r0, r3
8007a56: 3708 adds r7, #8
8007a58: 46bd mov sp, r7
8007a5a: bd80 pop {r7, pc}
8007a5c: 2000016c .word 0x2000016c
08007a60 <USBD_FS_ConfigStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8007a60: b580 push {r7, lr}
8007a62: b082 sub sp, #8
8007a64: af00 add r7, sp, #0
8007a66: 4603 mov r3, r0
8007a68: 6039 str r1, [r7, #0]
8007a6a: 71fb strb r3, [r7, #7]
if(speed == USBD_SPEED_HIGH)
8007a6c: 79fb ldrb r3, [r7, #7]
8007a6e: 2b00 cmp r3, #0
8007a70: d105 bne.n 8007a7e <USBD_FS_ConfigStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
8007a72: 683a ldr r2, [r7, #0]
8007a74: 4907 ldr r1, [pc, #28] ; (8007a94 <USBD_FS_ConfigStrDescriptor+0x34>)
8007a76: 4808 ldr r0, [pc, #32] ; (8007a98 <USBD_FS_ConfigStrDescriptor+0x38>)
8007a78: f7ff fda7 bl 80075ca <USBD_GetString>
8007a7c: e004 b.n 8007a88 <USBD_FS_ConfigStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
8007a7e: 683a ldr r2, [r7, #0]
8007a80: 4904 ldr r1, [pc, #16] ; (8007a94 <USBD_FS_ConfigStrDescriptor+0x34>)
8007a82: 4805 ldr r0, [pc, #20] ; (8007a98 <USBD_FS_ConfigStrDescriptor+0x38>)
8007a84: f7ff fda1 bl 80075ca <USBD_GetString>
}
return USBD_StrDesc;
8007a88: 4b02 ldr r3, [pc, #8] ; (8007a94 <USBD_FS_ConfigStrDescriptor+0x34>)
}
8007a8a: 4618 mov r0, r3
8007a8c: 3708 adds r7, #8
8007a8e: 46bd mov sp, r7
8007a90: bd80 pop {r7, pc}
8007a92: bf00 nop
8007a94: 200017e8 .word 0x200017e8
8007a98: 08008188 .word 0x08008188
08007a9c <USBD_FS_InterfaceStrDescriptor>:
* @param speed : Current device speed
* @param length : Pointer to data length variable
* @retval Pointer to descriptor buffer
*/
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{
8007a9c: b580 push {r7, lr}
8007a9e: b082 sub sp, #8
8007aa0: af00 add r7, sp, #0
8007aa2: 4603 mov r3, r0
8007aa4: 6039 str r1, [r7, #0]
8007aa6: 71fb strb r3, [r7, #7]
if(speed == 0)
8007aa8: 79fb ldrb r3, [r7, #7]
8007aaa: 2b00 cmp r3, #0
8007aac: d105 bne.n 8007aba <USBD_FS_InterfaceStrDescriptor+0x1e>
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
8007aae: 683a ldr r2, [r7, #0]
8007ab0: 4907 ldr r1, [pc, #28] ; (8007ad0 <USBD_FS_InterfaceStrDescriptor+0x34>)
8007ab2: 4808 ldr r0, [pc, #32] ; (8007ad4 <USBD_FS_InterfaceStrDescriptor+0x38>)
8007ab4: f7ff fd89 bl 80075ca <USBD_GetString>
8007ab8: e004 b.n 8007ac4 <USBD_FS_InterfaceStrDescriptor+0x28>
}
else
{
USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
8007aba: 683a ldr r2, [r7, #0]
8007abc: 4904 ldr r1, [pc, #16] ; (8007ad0 <USBD_FS_InterfaceStrDescriptor+0x34>)
8007abe: 4805 ldr r0, [pc, #20] ; (8007ad4 <USBD_FS_InterfaceStrDescriptor+0x38>)
8007ac0: f7ff fd83 bl 80075ca <USBD_GetString>
}
return USBD_StrDesc;
8007ac4: 4b02 ldr r3, [pc, #8] ; (8007ad0 <USBD_FS_InterfaceStrDescriptor+0x34>)
}
8007ac6: 4618 mov r0, r3
8007ac8: 3708 adds r7, #8
8007aca: 46bd mov sp, r7
8007acc: bd80 pop {r7, pc}
8007ace: bf00 nop
8007ad0: 200017e8 .word 0x200017e8
8007ad4: 08008194 .word 0x08008194
08007ad8 <Get_SerialNum>:
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
8007ad8: b580 push {r7, lr}
8007ada: b084 sub sp, #16
8007adc: af00 add r7, sp, #0
uint32_t deviceserial0, deviceserial1, deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
8007ade: 4b0f ldr r3, [pc, #60] ; (8007b1c <Get_SerialNum+0x44>)
8007ae0: 681b ldr r3, [r3, #0]
8007ae2: 60fb str r3, [r7, #12]
deviceserial1 = *(uint32_t *) DEVICE_ID2;
8007ae4: 4b0e ldr r3, [pc, #56] ; (8007b20 <Get_SerialNum+0x48>)
8007ae6: 681b ldr r3, [r3, #0]
8007ae8: 60bb str r3, [r7, #8]
deviceserial2 = *(uint32_t *) DEVICE_ID3;
8007aea: 4b0e ldr r3, [pc, #56] ; (8007b24 <Get_SerialNum+0x4c>)
8007aec: 681b ldr r3, [r3, #0]
8007aee: 607b str r3, [r7, #4]
deviceserial0 += deviceserial2;
8007af0: 68fa ldr r2, [r7, #12]
8007af2: 687b ldr r3, [r7, #4]
8007af4: 4413 add r3, r2
8007af6: 60fb str r3, [r7, #12]
if (deviceserial0 != 0)
8007af8: 68fb ldr r3, [r7, #12]
8007afa: 2b00 cmp r3, #0
8007afc: d009 beq.n 8007b12 <Get_SerialNum+0x3a>
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
8007afe: 2208 movs r2, #8
8007b00: 4909 ldr r1, [pc, #36] ; (8007b28 <Get_SerialNum+0x50>)
8007b02: 68f8 ldr r0, [r7, #12]
8007b04: f000 f814 bl 8007b30 <IntToUnicode>
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
8007b08: 2204 movs r2, #4
8007b0a: 4908 ldr r1, [pc, #32] ; (8007b2c <Get_SerialNum+0x54>)
8007b0c: 68b8 ldr r0, [r7, #8]
8007b0e: f000 f80f bl 8007b30 <IntToUnicode>
}
}
8007b12: bf00 nop
8007b14: 3710 adds r7, #16
8007b16: 46bd mov sp, r7
8007b18: bd80 pop {r7, pc}
8007b1a: bf00 nop
8007b1c: 1ffff7e8 .word 0x1ffff7e8
8007b20: 1ffff7ec .word 0x1ffff7ec
8007b24: 1ffff7f0 .word 0x1ffff7f0
8007b28: 2000016e .word 0x2000016e
8007b2c: 2000017e .word 0x2000017e
08007b30 <IntToUnicode>:
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
8007b30: b480 push {r7}
8007b32: b087 sub sp, #28
8007b34: af00 add r7, sp, #0
8007b36: 60f8 str r0, [r7, #12]
8007b38: 60b9 str r1, [r7, #8]
8007b3a: 4613 mov r3, r2
8007b3c: 71fb strb r3, [r7, #7]
uint8_t idx = 0;
8007b3e: 2300 movs r3, #0
8007b40: 75fb strb r3, [r7, #23]
for (idx = 0; idx < len; idx++)
8007b42: 2300 movs r3, #0
8007b44: 75fb strb r3, [r7, #23]
8007b46: e027 b.n 8007b98 <IntToUnicode+0x68>
{
if (((value >> 28)) < 0xA)
8007b48: 68fb ldr r3, [r7, #12]
8007b4a: 0f1b lsrs r3, r3, #28
8007b4c: 2b09 cmp r3, #9
8007b4e: d80b bhi.n 8007b68 <IntToUnicode+0x38>
{
pbuf[2 * idx] = (value >> 28) + '0';
8007b50: 68fb ldr r3, [r7, #12]
8007b52: 0f1b lsrs r3, r3, #28
8007b54: b2da uxtb r2, r3
8007b56: 7dfb ldrb r3, [r7, #23]
8007b58: 005b lsls r3, r3, #1
8007b5a: 4619 mov r1, r3
8007b5c: 68bb ldr r3, [r7, #8]
8007b5e: 440b add r3, r1
8007b60: 3230 adds r2, #48 ; 0x30
8007b62: b2d2 uxtb r2, r2
8007b64: 701a strb r2, [r3, #0]
8007b66: e00a b.n 8007b7e <IntToUnicode+0x4e>
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
8007b68: 68fb ldr r3, [r7, #12]
8007b6a: 0f1b lsrs r3, r3, #28
8007b6c: b2da uxtb r2, r3
8007b6e: 7dfb ldrb r3, [r7, #23]
8007b70: 005b lsls r3, r3, #1
8007b72: 4619 mov r1, r3
8007b74: 68bb ldr r3, [r7, #8]
8007b76: 440b add r3, r1
8007b78: 3237 adds r2, #55 ; 0x37
8007b7a: b2d2 uxtb r2, r2
8007b7c: 701a strb r2, [r3, #0]
}
value = value << 4;
8007b7e: 68fb ldr r3, [r7, #12]
8007b80: 011b lsls r3, r3, #4
8007b82: 60fb str r3, [r7, #12]
pbuf[2 * idx + 1] = 0;
8007b84: 7dfb ldrb r3, [r7, #23]
8007b86: 005b lsls r3, r3, #1
8007b88: 3301 adds r3, #1
8007b8a: 68ba ldr r2, [r7, #8]
8007b8c: 4413 add r3, r2
8007b8e: 2200 movs r2, #0
8007b90: 701a strb r2, [r3, #0]
for (idx = 0; idx < len; idx++)
8007b92: 7dfb ldrb r3, [r7, #23]
8007b94: 3301 adds r3, #1
8007b96: 75fb strb r3, [r7, #23]
8007b98: 7dfa ldrb r2, [r7, #23]
8007b9a: 79fb ldrb r3, [r7, #7]
8007b9c: 429a cmp r2, r3
8007b9e: d3d3 bcc.n 8007b48 <IntToUnicode+0x18>
}
}
8007ba0: bf00 nop
8007ba2: 371c adds r7, #28
8007ba4: 46bd mov sp, r7
8007ba6: bc80 pop {r7}
8007ba8: 4770 bx lr
...
08007bac <HAL_PCD_MspInit>:
LL Driver Callbacks (PCD -> USB Device Library)
*******************************************************************************/
/* MSP Init */
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
8007bac: b580 push {r7, lr}
8007bae: b084 sub sp, #16
8007bb0: af00 add r7, sp, #0
8007bb2: 6078 str r0, [r7, #4]
if(pcdHandle->Instance==USB)
8007bb4: 687b ldr r3, [r7, #4]
8007bb6: 681b ldr r3, [r3, #0]
8007bb8: 4a0d ldr r2, [pc, #52] ; (8007bf0 <HAL_PCD_MspInit+0x44>)
8007bba: 4293 cmp r3, r2
8007bbc: d113 bne.n 8007be6 <HAL_PCD_MspInit+0x3a>
{
/* USER CODE BEGIN USB_MspInit 0 */
/* USER CODE END USB_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
8007bbe: 4b0d ldr r3, [pc, #52] ; (8007bf4 <HAL_PCD_MspInit+0x48>)
8007bc0: 69db ldr r3, [r3, #28]
8007bc2: 4a0c ldr r2, [pc, #48] ; (8007bf4 <HAL_PCD_MspInit+0x48>)
8007bc4: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8007bc8: 61d3 str r3, [r2, #28]
8007bca: 4b0a ldr r3, [pc, #40] ; (8007bf4 <HAL_PCD_MspInit+0x48>)
8007bcc: 69db ldr r3, [r3, #28]
8007bce: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8007bd2: 60fb str r3, [r7, #12]
8007bd4: 68fb ldr r3, [r7, #12]
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0);
8007bd6: 2200 movs r2, #0
8007bd8: 2100 movs r1, #0
8007bda: 2014 movs r0, #20
8007bdc: f7f9 fd9f bl 800171e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
8007be0: 2014 movs r0, #20
8007be2: f7f9 fdb8 bl 8001756 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USB_MspInit 1 */
/* USER CODE END USB_MspInit 1 */
}
}
8007be6: bf00 nop
8007be8: 3710 adds r7, #16
8007bea: 46bd mov sp, r7
8007bec: bd80 pop {r7, pc}
8007bee: bf00 nop
8007bf0: 40005c00 .word 0x40005c00
8007bf4: 40021000 .word 0x40021000
08007bf8 <HAL_PCD_SetupStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007bf8: b580 push {r7, lr}
8007bfa: b082 sub sp, #8
8007bfc: af00 add r7, sp, #0
8007bfe: 6078 str r0, [r7, #4]
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
8007c00: 687b ldr r3, [r7, #4]
8007c02: f8d3 2268 ldr.w r2, [r3, #616] ; 0x268
8007c06: 687b ldr r3, [r7, #4]
8007c08: f503 730c add.w r3, r3, #560 ; 0x230
8007c0c: 4619 mov r1, r3
8007c0e: 4610 mov r0, r2
8007c10: f7fe fdb7 bl 8006782 <USBD_LL_SetupStage>
}
8007c14: bf00 nop
8007c16: 3708 adds r7, #8
8007c18: 46bd mov sp, r7
8007c1a: bd80 pop {r7, pc}
08007c1c <HAL_PCD_DataOutStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007c1c: b580 push {r7, lr}
8007c1e: b082 sub sp, #8
8007c20: af00 add r7, sp, #0
8007c22: 6078 str r0, [r7, #4]
8007c24: 460b mov r3, r1
8007c26: 70fb strb r3, [r7, #3]
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
8007c28: 687b ldr r3, [r7, #4]
8007c2a: f8d3 0268 ldr.w r0, [r3, #616] ; 0x268
8007c2e: 78fb ldrb r3, [r7, #3]
8007c30: 687a ldr r2, [r7, #4]
8007c32: 015b lsls r3, r3, #5
8007c34: 4413 add r3, r2
8007c36: f503 739e add.w r3, r3, #316 ; 0x13c
8007c3a: 681a ldr r2, [r3, #0]
8007c3c: 78fb ldrb r3, [r7, #3]
8007c3e: 4619 mov r1, r3
8007c40: f7fe fdea bl 8006818 <USBD_LL_DataOutStage>
}
8007c44: bf00 nop
8007c46: 3708 adds r7, #8
8007c48: 46bd mov sp, r7
8007c4a: bd80 pop {r7, pc}
08007c4c <HAL_PCD_DataInStageCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007c4c: b580 push {r7, lr}
8007c4e: b082 sub sp, #8
8007c50: af00 add r7, sp, #0
8007c52: 6078 str r0, [r7, #4]
8007c54: 460b mov r3, r1
8007c56: 70fb strb r3, [r7, #3]
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
8007c58: 687b ldr r3, [r7, #4]
8007c5a: f8d3 0268 ldr.w r0, [r3, #616] ; 0x268
8007c5e: 78fb ldrb r3, [r7, #3]
8007c60: 687a ldr r2, [r7, #4]
8007c62: 015b lsls r3, r3, #5
8007c64: 4413 add r3, r2
8007c66: 333c adds r3, #60 ; 0x3c
8007c68: 681a ldr r2, [r3, #0]
8007c6a: 78fb ldrb r3, [r7, #3]
8007c6c: 4619 mov r1, r3
8007c6e: f7fe fe44 bl 80068fa <USBD_LL_DataInStage>
}
8007c72: bf00 nop
8007c74: 3708 adds r7, #8
8007c76: 46bd mov sp, r7
8007c78: bd80 pop {r7, pc}
08007c7a <HAL_PCD_SOFCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007c7a: b580 push {r7, lr}
8007c7c: b082 sub sp, #8
8007c7e: af00 add r7, sp, #0
8007c80: 6078 str r0, [r7, #4]
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
8007c82: 687b ldr r3, [r7, #4]
8007c84: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268
8007c88: 4618 mov r0, r3
8007c8a: f7fe ff54 bl 8006b36 <USBD_LL_SOF>
}
8007c8e: bf00 nop
8007c90: 3708 adds r7, #8
8007c92: 46bd mov sp, r7
8007c94: bd80 pop {r7, pc}
08007c96 <HAL_PCD_ResetCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007c96: b580 push {r7, lr}
8007c98: b084 sub sp, #16
8007c9a: af00 add r7, sp, #0
8007c9c: 6078 str r0, [r7, #4]
USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
8007c9e: 2301 movs r3, #1
8007ca0: 73fb strb r3, [r7, #15]
if ( hpcd->Init.speed != PCD_SPEED_FULL)
8007ca2: 687b ldr r3, [r7, #4]
8007ca4: 689b ldr r3, [r3, #8]
8007ca6: 2b02 cmp r3, #2
8007ca8: d001 beq.n 8007cae <HAL_PCD_ResetCallback+0x18>
{
Error_Handler();
8007caa: f7f9 f9a5 bl 8000ff8 <Error_Handler>
}
/* Set Speed. */
USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
8007cae: 687b ldr r3, [r7, #4]
8007cb0: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268
8007cb4: 7bfa ldrb r2, [r7, #15]
8007cb6: 4611 mov r1, r2
8007cb8: 4618 mov r0, r3
8007cba: f7fe ff04 bl 8006ac6 <USBD_LL_SetSpeed>
/* Reset Device. */
USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
8007cbe: 687b ldr r3, [r7, #4]
8007cc0: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268
8007cc4: 4618 mov r0, r3
8007cc6: f7fe febd bl 8006a44 <USBD_LL_Reset>
}
8007cca: bf00 nop
8007ccc: 3710 adds r7, #16
8007cce: 46bd mov sp, r7
8007cd0: bd80 pop {r7, pc}
...
08007cd4 <HAL_PCD_SuspendCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007cd4: b580 push {r7, lr}
8007cd6: b082 sub sp, #8
8007cd8: af00 add r7, sp, #0
8007cda: 6078 str r0, [r7, #4]
/* Inform USB library that core enters in suspend Mode. */
USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
8007cdc: 687b ldr r3, [r7, #4]
8007cde: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268
8007ce2: 4618 mov r0, r3
8007ce4: f7fe fefe bl 8006ae4 <USBD_LL_Suspend>
/* Enter in STOP mode. */
/* USER CODE BEGIN 2 */
if (hpcd->Init.low_power_enable)
8007ce8: 687b ldr r3, [r7, #4]
8007cea: 699b ldr r3, [r3, #24]
8007cec: 2b00 cmp r3, #0
8007cee: d005 beq.n 8007cfc <HAL_PCD_SuspendCallback+0x28>
{
/* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
8007cf0: 4b04 ldr r3, [pc, #16] ; (8007d04 <HAL_PCD_SuspendCallback+0x30>)
8007cf2: 691b ldr r3, [r3, #16]
8007cf4: 4a03 ldr r2, [pc, #12] ; (8007d04 <HAL_PCD_SuspendCallback+0x30>)
8007cf6: f043 0306 orr.w r3, r3, #6
8007cfa: 6113 str r3, [r2, #16]
}
/* USER CODE END 2 */
}
8007cfc: bf00 nop
8007cfe: 3708 adds r7, #8
8007d00: 46bd mov sp, r7
8007d02: bd80 pop {r7, pc}
8007d04: e000ed00 .word 0xe000ed00
08007d08 <HAL_PCD_ResumeCallback>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
8007d08: b580 push {r7, lr}
8007d0a: b082 sub sp, #8
8007d0c: af00 add r7, sp, #0
8007d0e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
8007d10: 687b ldr r3, [r7, #4]
8007d12: f8d3 3268 ldr.w r3, [r3, #616] ; 0x268
8007d16: 4618 mov r0, r3
8007d18: f7fe fef8 bl 8006b0c <USBD_LL_Resume>
}
8007d1c: bf00 nop
8007d1e: 3708 adds r7, #8
8007d20: 46bd mov sp, r7
8007d22: bd80 pop {r7, pc}
08007d24 <USBD_LL_Init>:
* @brief Initializes the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
{
8007d24: b580 push {r7, lr}
8007d26: b082 sub sp, #8
8007d28: af00 add r7, sp, #0
8007d2a: 6078 str r0, [r7, #4]
/* Init USB Ip. */
/* Link the driver to the stack. */
hpcd_USB_FS.pData = pdev;
8007d2c: 4a28 ldr r2, [pc, #160] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d2e: 687b ldr r3, [r7, #4]
8007d30: f8c2 3268 str.w r3, [r2, #616] ; 0x268
pdev->pData = &hpcd_USB_FS;
8007d34: 687b ldr r3, [r7, #4]
8007d36: 4a26 ldr r2, [pc, #152] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d38: f8c3 22c0 str.w r2, [r3, #704] ; 0x2c0
hpcd_USB_FS.Instance = USB;
8007d3c: 4b24 ldr r3, [pc, #144] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d3e: 4a25 ldr r2, [pc, #148] ; (8007dd4 <USBD_LL_Init+0xb0>)
8007d40: 601a str r2, [r3, #0]
hpcd_USB_FS.Init.dev_endpoints = 8;
8007d42: 4b23 ldr r3, [pc, #140] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d44: 2208 movs r2, #8
8007d46: 605a str r2, [r3, #4]
hpcd_USB_FS.Init.speed = PCD_SPEED_FULL;
8007d48: 4b21 ldr r3, [pc, #132] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d4a: 2202 movs r2, #2
8007d4c: 609a str r2, [r3, #8]
hpcd_USB_FS.Init.low_power_enable = DISABLE;
8007d4e: 4b20 ldr r3, [pc, #128] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d50: 2200 movs r2, #0
8007d52: 619a str r2, [r3, #24]
hpcd_USB_FS.Init.lpm_enable = DISABLE;
8007d54: 4b1e ldr r3, [pc, #120] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d56: 2200 movs r2, #0
8007d58: 61da str r2, [r3, #28]
hpcd_USB_FS.Init.battery_charging_enable = DISABLE;
8007d5a: 4b1d ldr r3, [pc, #116] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d5c: 2200 movs r2, #0
8007d5e: 621a str r2, [r3, #32]
if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK)
8007d60: 481b ldr r0, [pc, #108] ; (8007dd0 <USBD_LL_Init+0xac>)
8007d62: f7fa fa3f bl 80021e4 <HAL_PCD_Init>
8007d66: 4603 mov r3, r0
8007d68: 2b00 cmp r3, #0
8007d6a: d001 beq.n 8007d70 <USBD_LL_Init+0x4c>
{
Error_Handler( );
8007d6c: f7f9 f944 bl 8000ff8 <Error_Handler>
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* USER CODE BEGIN EndPoint_Configuration */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
8007d70: 687b ldr r3, [r7, #4]
8007d72: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0
8007d76: 2318 movs r3, #24
8007d78: 2200 movs r2, #0
8007d7a: 2100 movs r1, #0
8007d7c: f7fb f8d8 bl 8002f30 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
8007d80: 687b ldr r3, [r7, #4]
8007d82: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0
8007d86: 2358 movs r3, #88 ; 0x58
8007d88: 2200 movs r2, #0
8007d8a: 2180 movs r1, #128 ; 0x80
8007d8c: f7fb f8d0 bl 8002f30 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration */
/* USER CODE BEGIN EndPoint_Configuration_CDC */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
8007d90: 687b ldr r3, [r7, #4]
8007d92: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0
8007d96: 23c0 movs r3, #192 ; 0xc0
8007d98: 2200 movs r2, #0
8007d9a: 2181 movs r1, #129 ; 0x81
8007d9c: f7fb f8c8 bl 8002f30 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
8007da0: 687b ldr r3, [r7, #4]
8007da2: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0
8007da6: f44f 7388 mov.w r3, #272 ; 0x110
8007daa: 2200 movs r2, #0
8007dac: 2101 movs r1, #1
8007dae: f7fb f8bf bl 8002f30 <HAL_PCDEx_PMAConfig>
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
8007db2: 687b ldr r3, [r7, #4]
8007db4: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0
8007db8: f44f 7380 mov.w r3, #256 ; 0x100
8007dbc: 2200 movs r2, #0
8007dbe: 2182 movs r1, #130 ; 0x82
8007dc0: f7fb f8b6 bl 8002f30 <HAL_PCDEx_PMAConfig>
/* USER CODE END EndPoint_Configuration_CDC */
return USBD_OK;
8007dc4: 2300 movs r3, #0
}
8007dc6: 4618 mov r0, r3
8007dc8: 3708 adds r7, #8
8007dca: 46bd mov sp, r7
8007dcc: bd80 pop {r7, pc}
8007dce: bf00 nop
8007dd0: 200019e8 .word 0x200019e8
8007dd4: 40005c00 .word 0x40005c00
08007dd8 <USBD_LL_Start>:
* @brief Starts the low level portion of the device driver.
* @param pdev: Device handle
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
{
8007dd8: b580 push {r7, lr}
8007dda: b084 sub sp, #16
8007ddc: af00 add r7, sp, #0
8007dde: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
8007de0: 2300 movs r3, #0
8007de2: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8007de4: 2300 movs r3, #0
8007de6: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_Start(pdev->pData);
8007de8: 687b ldr r3, [r7, #4]
8007dea: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
8007dee: 4618 mov r0, r3
8007df0: f7fa fad9 bl 80023a6 <HAL_PCD_Start>
8007df4: 4603 mov r3, r0
8007df6: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8007df8: 7bfb ldrb r3, [r7, #15]
8007dfa: 4618 mov r0, r3
8007dfc: f000 f948 bl 8008090 <USBD_Get_USB_Status>
8007e00: 4603 mov r3, r0
8007e02: 73bb strb r3, [r7, #14]
return usb_status;
8007e04: 7bbb ldrb r3, [r7, #14]
}
8007e06: 4618 mov r0, r3
8007e08: 3710 adds r7, #16
8007e0a: 46bd mov sp, r7
8007e0c: bd80 pop {r7, pc}
08007e0e <USBD_LL_OpenEP>:
* @param ep_type: Endpoint type
* @param ep_mps: Endpoint max packet size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
{
8007e0e: b580 push {r7, lr}
8007e10: b084 sub sp, #16
8007e12: af00 add r7, sp, #0
8007e14: 6078 str r0, [r7, #4]
8007e16: 4608 mov r0, r1
8007e18: 4611 mov r1, r2
8007e1a: 461a mov r2, r3
8007e1c: 4603 mov r3, r0
8007e1e: 70fb strb r3, [r7, #3]
8007e20: 460b mov r3, r1
8007e22: 70bb strb r3, [r7, #2]
8007e24: 4613 mov r3, r2
8007e26: 803b strh r3, [r7, #0]
HAL_StatusTypeDef hal_status = HAL_OK;
8007e28: 2300 movs r3, #0
8007e2a: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8007e2c: 2300 movs r3, #0
8007e2e: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
8007e30: 687b ldr r3, [r7, #4]
8007e32: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0
8007e36: 78bb ldrb r3, [r7, #2]
8007e38: 883a ldrh r2, [r7, #0]
8007e3a: 78f9 ldrb r1, [r7, #3]
8007e3c: f7fa fc0c bl 8002658 <HAL_PCD_EP_Open>
8007e40: 4603 mov r3, r0
8007e42: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8007e44: 7bfb ldrb r3, [r7, #15]
8007e46: 4618 mov r0, r3
8007e48: f000 f922 bl 8008090 <USBD_Get_USB_Status>
8007e4c: 4603 mov r3, r0
8007e4e: 73bb strb r3, [r7, #14]
return usb_status;
8007e50: 7bbb ldrb r3, [r7, #14]
}
8007e52: 4618 mov r0, r3
8007e54: 3710 adds r7, #16
8007e56: 46bd mov sp, r7
8007e58: bd80 pop {r7, pc}
08007e5a <USBD_LL_CloseEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8007e5a: b580 push {r7, lr}
8007e5c: b084 sub sp, #16
8007e5e: af00 add r7, sp, #0
8007e60: 6078 str r0, [r7, #4]
8007e62: 460b mov r3, r1
8007e64: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8007e66: 2300 movs r3, #0
8007e68: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8007e6a: 2300 movs r3, #0
8007e6c: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
8007e6e: 687b ldr r3, [r7, #4]
8007e70: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
8007e74: 78fa ldrb r2, [r7, #3]
8007e76: 4611 mov r1, r2
8007e78: 4618 mov r0, r3
8007e7a: f7fa fc4d bl 8002718 <HAL_PCD_EP_Close>
8007e7e: 4603 mov r3, r0
8007e80: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8007e82: 7bfb ldrb r3, [r7, #15]
8007e84: 4618 mov r0, r3
8007e86: f000 f903 bl 8008090 <USBD_Get_USB_Status>
8007e8a: 4603 mov r3, r0
8007e8c: 73bb strb r3, [r7, #14]
return usb_status;
8007e8e: 7bbb ldrb r3, [r7, #14]
}
8007e90: 4618 mov r0, r3
8007e92: 3710 adds r7, #16
8007e94: 46bd mov sp, r7
8007e96: bd80 pop {r7, pc}
08007e98 <USBD_LL_StallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8007e98: b580 push {r7, lr}
8007e9a: b084 sub sp, #16
8007e9c: af00 add r7, sp, #0
8007e9e: 6078 str r0, [r7, #4]
8007ea0: 460b mov r3, r1
8007ea2: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8007ea4: 2300 movs r3, #0
8007ea6: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8007ea8: 2300 movs r3, #0
8007eaa: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
8007eac: 687b ldr r3, [r7, #4]
8007eae: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
8007eb2: 78fa ldrb r2, [r7, #3]
8007eb4: 4611 mov r1, r2
8007eb6: 4618 mov r0, r3
8007eb8: f7fa fcf7 bl 80028aa <HAL_PCD_EP_SetStall>
8007ebc: 4603 mov r3, r0
8007ebe: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8007ec0: 7bfb ldrb r3, [r7, #15]
8007ec2: 4618 mov r0, r3
8007ec4: f000 f8e4 bl 8008090 <USBD_Get_USB_Status>
8007ec8: 4603 mov r3, r0
8007eca: 73bb strb r3, [r7, #14]
return usb_status;
8007ecc: 7bbb ldrb r3, [r7, #14]
}
8007ece: 4618 mov r0, r3
8007ed0: 3710 adds r7, #16
8007ed2: 46bd mov sp, r7
8007ed4: bd80 pop {r7, pc}
08007ed6 <USBD_LL_ClearStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8007ed6: b580 push {r7, lr}
8007ed8: b084 sub sp, #16
8007eda: af00 add r7, sp, #0
8007edc: 6078 str r0, [r7, #4]
8007ede: 460b mov r3, r1
8007ee0: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8007ee2: 2300 movs r3, #0
8007ee4: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8007ee6: 2300 movs r3, #0
8007ee8: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
8007eea: 687b ldr r3, [r7, #4]
8007eec: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
8007ef0: 78fa ldrb r2, [r7, #3]
8007ef2: 4611 mov r1, r2
8007ef4: 4618 mov r0, r3
8007ef6: f7fa fd32 bl 800295e <HAL_PCD_EP_ClrStall>
8007efa: 4603 mov r3, r0
8007efc: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8007efe: 7bfb ldrb r3, [r7, #15]
8007f00: 4618 mov r0, r3
8007f02: f000 f8c5 bl 8008090 <USBD_Get_USB_Status>
8007f06: 4603 mov r3, r0
8007f08: 73bb strb r3, [r7, #14]
return usb_status;
8007f0a: 7bbb ldrb r3, [r7, #14]
}
8007f0c: 4618 mov r0, r3
8007f0e: 3710 adds r7, #16
8007f10: 46bd mov sp, r7
8007f12: bd80 pop {r7, pc}
08007f14 <USBD_LL_IsStallEP>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Stall (1: Yes, 0: No)
*/
uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8007f14: b480 push {r7}
8007f16: b085 sub sp, #20
8007f18: af00 add r7, sp, #0
8007f1a: 6078 str r0, [r7, #4]
8007f1c: 460b mov r3, r1
8007f1e: 70fb strb r3, [r7, #3]
PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
8007f20: 687b ldr r3, [r7, #4]
8007f22: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
8007f26: 60fb str r3, [r7, #12]
if((ep_addr & 0x80) == 0x80)
8007f28: f997 3003 ldrsb.w r3, [r7, #3]
8007f2c: 2b00 cmp r3, #0
8007f2e: da08 bge.n 8007f42 <USBD_LL_IsStallEP+0x2e>
{
return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
8007f30: 78fb ldrb r3, [r7, #3]
8007f32: f003 037f and.w r3, r3, #127 ; 0x7f
8007f36: 68fa ldr r2, [r7, #12]
8007f38: 015b lsls r3, r3, #5
8007f3a: 4413 add r3, r2
8007f3c: 332a adds r3, #42 ; 0x2a
8007f3e: 781b ldrb r3, [r3, #0]
8007f40: e008 b.n 8007f54 <USBD_LL_IsStallEP+0x40>
}
else
{
return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
8007f42: 78fb ldrb r3, [r7, #3]
8007f44: f003 037f and.w r3, r3, #127 ; 0x7f
8007f48: 68fa ldr r2, [r7, #12]
8007f4a: 015b lsls r3, r3, #5
8007f4c: 4413 add r3, r2
8007f4e: f503 7395 add.w r3, r3, #298 ; 0x12a
8007f52: 781b ldrb r3, [r3, #0]
}
}
8007f54: 4618 mov r0, r3
8007f56: 3714 adds r7, #20
8007f58: 46bd mov sp, r7
8007f5a: bc80 pop {r7}
8007f5c: 4770 bx lr
08007f5e <USBD_LL_SetUSBAddress>:
* @param pdev: Device handle
* @param dev_addr: Device address
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
{
8007f5e: b580 push {r7, lr}
8007f60: b084 sub sp, #16
8007f62: af00 add r7, sp, #0
8007f64: 6078 str r0, [r7, #4]
8007f66: 460b mov r3, r1
8007f68: 70fb strb r3, [r7, #3]
HAL_StatusTypeDef hal_status = HAL_OK;
8007f6a: 2300 movs r3, #0
8007f6c: 73fb strb r3, [r7, #15]
USBD_StatusTypeDef usb_status = USBD_OK;
8007f6e: 2300 movs r3, #0
8007f70: 73bb strb r3, [r7, #14]
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
8007f72: 687b ldr r3, [r7, #4]
8007f74: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
8007f78: 78fa ldrb r2, [r7, #3]
8007f7a: 4611 mov r1, r2
8007f7c: 4618 mov r0, r3
8007f7e: f7fa fb46 bl 800260e <HAL_PCD_SetAddress>
8007f82: 4603 mov r3, r0
8007f84: 73fb strb r3, [r7, #15]
usb_status = USBD_Get_USB_Status(hal_status);
8007f86: 7bfb ldrb r3, [r7, #15]
8007f88: 4618 mov r0, r3
8007f8a: f000 f881 bl 8008090 <USBD_Get_USB_Status>
8007f8e: 4603 mov r3, r0
8007f90: 73bb strb r3, [r7, #14]
return usb_status;
8007f92: 7bbb ldrb r3, [r7, #14]
}
8007f94: 4618 mov r0, r3
8007f96: 3710 adds r7, #16
8007f98: 46bd mov sp, r7
8007f9a: bd80 pop {r7, pc}
08007f9c <USBD_LL_Transmit>:
* @param pbuf: Pointer to data to be sent
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
8007f9c: b580 push {r7, lr}
8007f9e: b086 sub sp, #24
8007fa0: af00 add r7, sp, #0
8007fa2: 60f8 str r0, [r7, #12]
8007fa4: 607a str r2, [r7, #4]
8007fa6: 461a mov r2, r3
8007fa8: 460b mov r3, r1
8007faa: 72fb strb r3, [r7, #11]
8007fac: 4613 mov r3, r2
8007fae: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
8007fb0: 2300 movs r3, #0
8007fb2: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
8007fb4: 2300 movs r3, #0
8007fb6: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
8007fb8: 68fb ldr r3, [r7, #12]
8007fba: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0
8007fbe: 893b ldrh r3, [r7, #8]
8007fc0: 7af9 ldrb r1, [r7, #11]
8007fc2: 687a ldr r2, [r7, #4]
8007fc4: f7fa fc38 bl 8002838 <HAL_PCD_EP_Transmit>
8007fc8: 4603 mov r3, r0
8007fca: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
8007fcc: 7dfb ldrb r3, [r7, #23]
8007fce: 4618 mov r0, r3
8007fd0: f000 f85e bl 8008090 <USBD_Get_USB_Status>
8007fd4: 4603 mov r3, r0
8007fd6: 75bb strb r3, [r7, #22]
return usb_status;
8007fd8: 7dbb ldrb r3, [r7, #22]
}
8007fda: 4618 mov r0, r3
8007fdc: 3718 adds r7, #24
8007fde: 46bd mov sp, r7
8007fe0: bd80 pop {r7, pc}
08007fe2 <USBD_LL_PrepareReceive>:
* @param pbuf: Pointer to data to be received
* @param size: Data size
* @retval USBD status
*/
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
{
8007fe2: b580 push {r7, lr}
8007fe4: b086 sub sp, #24
8007fe6: af00 add r7, sp, #0
8007fe8: 60f8 str r0, [r7, #12]
8007fea: 607a str r2, [r7, #4]
8007fec: 461a mov r2, r3
8007fee: 460b mov r3, r1
8007ff0: 72fb strb r3, [r7, #11]
8007ff2: 4613 mov r3, r2
8007ff4: 813b strh r3, [r7, #8]
HAL_StatusTypeDef hal_status = HAL_OK;
8007ff6: 2300 movs r3, #0
8007ff8: 75fb strb r3, [r7, #23]
USBD_StatusTypeDef usb_status = USBD_OK;
8007ffa: 2300 movs r3, #0
8007ffc: 75bb strb r3, [r7, #22]
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
8007ffe: 68fb ldr r3, [r7, #12]
8008000: f8d3 02c0 ldr.w r0, [r3, #704] ; 0x2c0
8008004: 893b ldrh r3, [r7, #8]
8008006: 7af9 ldrb r1, [r7, #11]
8008008: 687a ldr r2, [r7, #4]
800800a: f7fa fbc7 bl 800279c <HAL_PCD_EP_Receive>
800800e: 4603 mov r3, r0
8008010: 75fb strb r3, [r7, #23]
usb_status = USBD_Get_USB_Status(hal_status);
8008012: 7dfb ldrb r3, [r7, #23]
8008014: 4618 mov r0, r3
8008016: f000 f83b bl 8008090 <USBD_Get_USB_Status>
800801a: 4603 mov r3, r0
800801c: 75bb strb r3, [r7, #22]
return usb_status;
800801e: 7dbb ldrb r3, [r7, #22]
}
8008020: 4618 mov r0, r3
8008022: 3718 adds r7, #24
8008024: 46bd mov sp, r7
8008026: bd80 pop {r7, pc}
08008028 <USBD_LL_GetRxDataSize>:
* @param pdev: Device handle
* @param ep_addr: Endpoint number
* @retval Recived Data Size
*/
uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{
8008028: b580 push {r7, lr}
800802a: b082 sub sp, #8
800802c: af00 add r7, sp, #0
800802e: 6078 str r0, [r7, #4]
8008030: 460b mov r3, r1
8008032: 70fb strb r3, [r7, #3]
return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
8008034: 687b ldr r3, [r7, #4]
8008036: f8d3 32c0 ldr.w r3, [r3, #704] ; 0x2c0
800803a: 78fa ldrb r2, [r7, #3]
800803c: 4611 mov r1, r2
800803e: 4618 mov r0, r3
8008040: f7fa fbe6 bl 8002810 <HAL_PCD_EP_GetRxCount>
8008044: 4603 mov r3, r0
}
8008046: 4618 mov r0, r3
8008048: 3708 adds r7, #8
800804a: 46bd mov sp, r7
800804c: bd80 pop {r7, pc}
...
08008050 <USBD_static_malloc>:
* @brief Static single allocation.
* @param size: Size of allocated memory
* @retval None
*/
void *USBD_static_malloc(uint32_t size)
{
8008050: b480 push {r7}
8008052: b083 sub sp, #12
8008054: af00 add r7, sp, #0
8008056: 6078 str r0, [r7, #4]
static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
return mem;
8008058: 4b02 ldr r3, [pc, #8] ; (8008064 <USBD_static_malloc+0x14>)
}
800805a: 4618 mov r0, r3
800805c: 370c adds r7, #12
800805e: 46bd mov sp, r7
8008060: bc80 pop {r7}
8008062: 4770 bx lr
8008064: 20000594 .word 0x20000594
08008068 <USBD_static_free>:
* @brief Dummy memory free
* @param p: Pointer to allocated memory address
* @retval None
*/
void USBD_static_free(void *p)
{
8008068: b480 push {r7}
800806a: b083 sub sp, #12
800806c: af00 add r7, sp, #0
800806e: 6078 str r0, [r7, #4]
}
8008070: bf00 nop
8008072: 370c adds r7, #12
8008074: 46bd mov sp, r7
8008076: bc80 pop {r7}
8008078: 4770 bx lr
0800807a <HAL_PCDEx_SetConnectionState>:
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#else
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
800807a: b480 push {r7}
800807c: b083 sub sp, #12
800807e: af00 add r7, sp, #0
8008080: 6078 str r0, [r7, #4]
8008082: 460b mov r3, r1
8008084: 70fb strb r3, [r7, #3]
{
/* Configure High connection state. */
}
/* USER CODE END 6 */
}
8008086: bf00 nop
8008088: 370c adds r7, #12
800808a: 46bd mov sp, r7
800808c: bc80 pop {r7}
800808e: 4770 bx lr
08008090 <USBD_Get_USB_Status>:
* @brief Retuns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
{
8008090: b480 push {r7}
8008092: b085 sub sp, #20
8008094: af00 add r7, sp, #0
8008096: 4603 mov r3, r0
8008098: 71fb strb r3, [r7, #7]
USBD_StatusTypeDef usb_status = USBD_OK;
800809a: 2300 movs r3, #0
800809c: 73fb strb r3, [r7, #15]
switch (hal_status)
800809e: 79fb ldrb r3, [r7, #7]
80080a0: 2b03 cmp r3, #3
80080a2: d817 bhi.n 80080d4 <USBD_Get_USB_Status+0x44>
80080a4: a201 add r2, pc, #4 ; (adr r2, 80080ac <USBD_Get_USB_Status+0x1c>)
80080a6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80080aa: bf00 nop
80080ac: 080080bd .word 0x080080bd
80080b0: 080080c3 .word 0x080080c3
80080b4: 080080c9 .word 0x080080c9
80080b8: 080080cf .word 0x080080cf
{
case HAL_OK :
usb_status = USBD_OK;
80080bc: 2300 movs r3, #0
80080be: 73fb strb r3, [r7, #15]
break;
80080c0: e00b b.n 80080da <USBD_Get_USB_Status+0x4a>
case HAL_ERROR :
usb_status = USBD_FAIL;
80080c2: 2302 movs r3, #2
80080c4: 73fb strb r3, [r7, #15]
break;
80080c6: e008 b.n 80080da <USBD_Get_USB_Status+0x4a>
case HAL_BUSY :
usb_status = USBD_BUSY;
80080c8: 2301 movs r3, #1
80080ca: 73fb strb r3, [r7, #15]
break;
80080cc: e005 b.n 80080da <USBD_Get_USB_Status+0x4a>
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
80080ce: 2302 movs r3, #2
80080d0: 73fb strb r3, [r7, #15]
break;
80080d2: e002 b.n 80080da <USBD_Get_USB_Status+0x4a>
default :
usb_status = USBD_FAIL;
80080d4: 2302 movs r3, #2
80080d6: 73fb strb r3, [r7, #15]
break;
80080d8: bf00 nop
}
return usb_status;
80080da: 7bfb ldrb r3, [r7, #15]
}
80080dc: 4618 mov r0, r3
80080de: 3714 adds r7, #20
80080e0: 46bd mov sp, r7
80080e2: bc80 pop {r7}
80080e4: 4770 bx lr
80080e6: bf00 nop
080080e8 <__libc_init_array>:
80080e8: b570 push {r4, r5, r6, lr}
80080ea: 2500 movs r5, #0
80080ec: 4e0c ldr r6, [pc, #48] ; (8008120 <__libc_init_array+0x38>)
80080ee: 4c0d ldr r4, [pc, #52] ; (8008124 <__libc_init_array+0x3c>)
80080f0: 1ba4 subs r4, r4, r6
80080f2: 10a4 asrs r4, r4, #2
80080f4: 42a5 cmp r5, r4
80080f6: d109 bne.n 800810c <__libc_init_array+0x24>
80080f8: f000 f82e bl 8008158 <_init>
80080fc: 2500 movs r5, #0
80080fe: 4e0a ldr r6, [pc, #40] ; (8008128 <__libc_init_array+0x40>)
8008100: 4c0a ldr r4, [pc, #40] ; (800812c <__libc_init_array+0x44>)
8008102: 1ba4 subs r4, r4, r6
8008104: 10a4 asrs r4, r4, #2
8008106: 42a5 cmp r5, r4
8008108: d105 bne.n 8008116 <__libc_init_array+0x2e>
800810a: bd70 pop {r4, r5, r6, pc}
800810c: f856 3025 ldr.w r3, [r6, r5, lsl #2]
8008110: 4798 blx r3
8008112: 3501 adds r5, #1
8008114: e7ee b.n 80080f4 <__libc_init_array+0xc>
8008116: f856 3025 ldr.w r3, [r6, r5, lsl #2]
800811a: 4798 blx r3
800811c: 3501 adds r5, #1
800811e: e7f2 b.n 8008106 <__libc_init_array+0x1e>
8008120: 080081bc .word 0x080081bc
8008124: 080081bc .word 0x080081bc
8008128: 080081bc .word 0x080081bc
800812c: 080081c0 .word 0x080081c0
08008130 <memcpy>:
8008130: b510 push {r4, lr}
8008132: 1e43 subs r3, r0, #1
8008134: 440a add r2, r1
8008136: 4291 cmp r1, r2
8008138: d100 bne.n 800813c <memcpy+0xc>
800813a: bd10 pop {r4, pc}
800813c: f811 4b01 ldrb.w r4, [r1], #1
8008140: f803 4f01 strb.w r4, [r3, #1]!
8008144: e7f7 b.n 8008136 <memcpy+0x6>
08008146 <memset>:
8008146: 4603 mov r3, r0
8008148: 4402 add r2, r0
800814a: 4293 cmp r3, r2
800814c: d100 bne.n 8008150 <memset+0xa>
800814e: 4770 bx lr
8008150: f803 1b01 strb.w r1, [r3], #1
8008154: e7f9 b.n 800814a <memset+0x4>
...
08008158 <_init>:
8008158: b5f8 push {r3, r4, r5, r6, r7, lr}
800815a: bf00 nop
800815c: bcf8 pop {r3, r4, r5, r6, r7}
800815e: bc08 pop {r3}
8008160: 469e mov lr, r3
8008162: 4770 bx lr
08008164 <_fini>:
8008164: b5f8 push {r3, r4, r5, r6, r7, lr}
8008166: bf00 nop
8008168: bcf8 pop {r3, r4, r5, r6, r7}
800816a: bc08 pop {r3}
800816c: 469e mov lr, r3
800816e: 4770 bx lr
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