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7 Commits

Author SHA1 Message Date
blta
b1a9c4c4ea [libcpu/arm]: add dsb and isb instructions in the end of rt_hw_context_switch_to (#5748) 2022-04-08 12:52:22 +08:00
aozima
c3d63e49de set Systick interrupt priority to the lowest 2020-05-30 15:23:25 +08:00
Bernard Xiong
bde47018b8 [libcpu] Add SConscript in libcpu. 2019-01-07 06:09:45 +08:00
aozima
2c47f2e683 Fix some spell error; 2014-07-31 13:59:25 +08:00
aozima
a2ff85c03f update libcpu/arm/cortex-m0: restore MSP. 2013-06-22 18:59:51 +08:00
Bernard Xiong
72782e9203 convert end of line 2013-01-08 05:05:02 -08:00
wuyangyong
056228cce6 fixed bug: store r8 - r11. 
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2258 bbd45198-f89e-11dd-88c7-29a3b14d5316
 2012-08-22 15:53:54 +00:00