mirror of
https://github.com/apache/nuttx.git
synced 2025-05-08 22:32:04 +08:00
Fix typos and some incorrect comments
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle against .c and .h files and fix it
Author: Juha Niskanen <juha.niskanen@haltian.com>
Fix typos and some incorrect comments
This commit is contained in:
Juha Niskanen
Alan Carvalho de Assis
parent
bcfb45dfa0
commit
a762c06ed9
@ -21912,7 +21912,7 @@ Additional new features and extended functionality:
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number as an argument. This makes it possible to have multiple
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instances of the NX server running on boards that support multiple
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displays. Also includes updates to boardctl() to accept display
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number paramters. From Gregory Nutt.
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number parameters. From Gregory Nutt.
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- Graphics: nx_openwindow() and nxtk_openwindow() now accept an
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additional 'flag' parameter. This argument is current used only to
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select a RAM backed, per-window framebuffer. From Gregory Nutt.
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@ -26590,7 +26590,7 @@ information):
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- apps/system/cu/: (1) Fix early exit. getc(stdin) can return 0 the
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first time around. (2) Set optind to zero. getopt() was being
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left in a bad state, causing parsing errors on second use. (3) Fix
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priority of cu_listen(). (4) Add suppor for -h. From David
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priority of cu_listen(). (4) Add support for -h. From David
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Alessio.
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- apps/system/lzf/: Check the protection by CONFIG_SYSTEM_LZF !=
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CONFIG_m (not elf binary) instead of CONFIG_KERNEL_BUILD. From
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@ -101,12 +101,12 @@
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/* The Type of a spinlock.
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*
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* ARMv6 architecture introuced the concept of exclusive accesses to memory
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* ARMv6 architecture introduced the concept of exclusive accesses to memory
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* locations in the form of the Load-Exclusive (LDREX) and Store-Exclusive
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* (STREX) instructions in ARM and Thumb instruction sets. ARMv6K extended
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* this to included byte, halfword, and doubleword variants of LDREX and
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* STREX. ARMv7-M supports byte and halfword, but not the doubleword varient
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* (ARMv6-M does not support exclusive access)
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* STREX. ARMv7-M supports byte and halfword, but not the doubleword variant
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* (ARMv6-M does not support exclusive access).
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*
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* ARM architectures prior to ARMv6 supported SWP and SWPB instructions that
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* atomically swap a 32-bit word for byte value between a register and a
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@ -128,6 +128,7 @@ void arm_gic0_initialize(void)
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*/
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/* Enable GIC distributor */
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putreg32(0x3, GIC_ICDDCR);
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/* Registers with 1-bit per interrupt */
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@ -183,12 +184,12 @@ void arm_gic_initialize(void)
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/* Registers with 1-bit per interrupt */
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putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */
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putreg32(0xf8000000, GIC_ICDICER(0)); /* PPIs disabled */
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putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */
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putreg32(0xf8000000, GIC_ICDICER(0)); /* PPIs disabled */
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/* Registers with 8-bits per interrupt */
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putreg32(0x80808080, GIC_ICDIPR(0)); /* SGI[3:0] priority */
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putreg32(0x80808080, GIC_ICDIPR(0)); /* SGI[3:0] priority */
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putreg32(0x80808080, GIC_ICDIPR(4)); /* SGI[4:7] priority */
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putreg32(0x80808080, GIC_ICDIPR(8)); /* SGI[8:11] priority */
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putreg32(0x80808080, GIC_ICDIPR(12)); /* SGI[12:15] priority */
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@ -219,12 +220,25 @@ void arm_gic_initialize(void)
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#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
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/* Clear secure state ICCICR bits to be configured below */
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iccicr &= ~(GIC_ICCICRS_FIQEN | GIC_ICCICRS_ACKTCTL | GIC_ICCICRS_CBPR | GIC_ICCICRS_EOIMODES | GIC_ICCICRS_EOIMODENS | GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 | GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
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iccicr &= ~(GIC_ICCICRS_FIQEN |
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GIC_ICCICRS_ACKTCTL |
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GIC_ICCICRS_CBPR |
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GIC_ICCICRS_EOIMODES |
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GIC_ICCICRS_EOIMODENS |
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GIC_ICCICRS_ENABLEGRP0 |
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GIC_ICCICRS_ENABLEGRP1 |
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GIC_ICCICRS_FIQBYPDISGRP0 |
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GIC_ICCICRS_IRQBYPDISGRP0 |
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GIC_ICCICRS_FIQBYPDISGRP1 |
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GIC_ICCICRS_IRQBYPDISGRP1);
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#elif defined(CONFIG_ARCH_TRUSTZONE_NONSECURE)
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/* Clear non-secure state ICCICR bits to be configured below */
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iccicr &= ~(GIC_ICCICRS_EOIMODENS | GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1);
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iccicr &= ~(GIC_ICCICRS_EOIMODENS |
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GIC_ICCICRU_ENABLEGRP1 |
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GIC_ICCICRU_FIQBYPDISGRP1 |
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GIC_ICCICRU_IRQBYPDISGRP1);
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#endif
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@ -247,7 +261,7 @@ void arm_gic_initialize(void)
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* REVISIT: I don't yet fully understand this setting.
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*/
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// iccicr |= GIC_ICCICRS_ACKTCTL;
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/* iccicr |= GIC_ICCICRS_ACKTCTL; */
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/* Program the SBPR bit to select the required binary pointer behavior.
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*
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@ -256,7 +270,8 @@ void arm_gic_initialize(void)
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* REVISIT: I don't yet fully understand this setting.
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*/
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// iccicr |= GIC_ICCICRS_CBPR;
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/* iccicr |= GIC_ICCICRS_CBPR; */
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#endif
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#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_BOTH)
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@ -307,19 +322,30 @@ void arm_gic_initialize(void)
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* bypass.
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*/
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iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
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iccicr |= (GIC_ICCICRS_ENABLEGRP0 |
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GIC_ICCICRS_FIQBYPDISGRP0 |
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GIC_ICCICRS_IRQBYPDISGRP0 |
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GIC_ICCICRS_FIQBYPDISGRP1 |
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GIC_ICCICRS_IRQBYPDISGRP1);
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#elif defined(CONFIG_ARCH_TRUSTZONE_BOTH)
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/* Enable the Group 0/1 interrupts, FIQEn and disable Group 0/1
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* bypass.
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*/
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iccicr |= (GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 | GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1);
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iccicr |= (GIC_ICCICRS_ENABLEGRP0 |
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GIC_ICCICRS_ENABLEGRP1 |
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GIC_ICCICRS_FIQBYPDISGRP0 |
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GIC_ICCICRS_IRQBYPDISGRP0 |
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GIC_ICCICRS_FIQBYPDISGRP1 |
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GIC_ICCICRS_IRQBYPDISGRP1);
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#else /* defined(CONFIG_ARCH_TRUSTZONE_NONSECURE) */
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#else /* defined(CONFIG_ARCH_TRUSTZONE_NONSECURE) */
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/* Enable the Group 1 interrupts and disable Group 1 bypass. */
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iccicr |= (GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1);
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iccicr |= (GIC_ICCICRU_ENABLEGRP1 |
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GIC_ICCICRU_FIQBYPDISGRP1 |
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GIC_ICCICRU_IRQBYPDISGRP1);
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#endif
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@ -503,7 +529,7 @@ int up_prioritize_irq(int irq, int priority)
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* If CONFIG_SMP is not selected, the cpuset is ignored and SGI is sent
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* only to the current CPU.
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*
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* Input Paramters
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* Input Parameters
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* sgi - The SGI interrupt ID (0-15)
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* cpuset - The set of CPUs to receive the SGI
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*
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@ -517,9 +543,13 @@ int arm_cpu_sgi(int sgi, unsigned int cpuset)
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uint32_t regval;
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#ifdef CONFIG_SMP
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regval = GIC_ICDSGIR_INTID(sgi) | GIC_ICDSGIR_CPUTARGET(cpuset) | GIC_ICDSGIR_TGTFILTER_LIST;
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regval = GIC_ICDSGIR_INTID(sgi) |
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GIC_ICDSGIR_CPUTARGET(cpuset) |
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GIC_ICDSGIR_TGTFILTER_LIST;
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#else
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regval = GIC_ICDSGIR_INTID(sgi) | GIC_ICDSGIR_CPUTARGET(0) | GIC_ICDSGIR_TGTFILTER_THIS;
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regval = GIC_ICDSGIR_INTID(sgi) |
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GIC_ICDSGIR_CPUTARGET(0) |
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GIC_ICDSGIR_TGTFILTER_THIS;
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#endif
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putreg32(regval, GIC_ICDSGIR);
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@ -57,7 +57,9 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Generic indexing helpers *************************************************/
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/* 1x32 bit field per register */
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#define GIC_INDEX1(n) (n) /* 1 field per word */
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@ -101,6 +103,7 @@
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#define GIC_MASK32(n) (1U << GIC_SHIFT32(n)) /* 1-bit mask */
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/* GIC Register Offsets *****************************************************/
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/* Interrupt Interface registers */
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#define GIC_ICCICR_OFFSET 0x0000 /* CPU Interface Control Register */
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@ -120,6 +123,7 @@
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#define GIC_ICDIIDR_OFFSET 0x0008 /* Distributor Implementer ID Register */
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/* 0x000c-0x007c: Reserved */
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/* Interrupt Security Registers: 0x0080-0x009c */
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#define GIC_ICDISR_OFFSET(n) (0x0080 + GIC_OFFSET32(n))
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@ -145,16 +149,19 @@
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#define GIC_ICDABR_OFFSET(n) (0x0300 + GIC_OFFSET32(n))
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/* 0x0380-0x03fc: Reserved */
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/* Interrupt Priority Registers: 0x0400-0x04fc */
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#define GIC_ICDIPR_OFFSET(n) (0x0400 + GIC_OFFSET4(n))
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/* 0x0500-0x07fc: Reserved */
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/* Interrupt Processor Target Registers: 0x0800-0x08fc */
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#define GIC_ICDIPTR_OFFSET(n) (0x0800 + GIC_OFFSET4(n))
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/* 0x0900-0x0bfc: Reserved */
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/* Interrupt Configuration Registers: 0x0c00-0x0c3c */
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#define GIC_ICDICFR_OFFSET(n) (0x0c00 + GIC_OFFSET16(n))
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@ -168,11 +175,13 @@
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#define GIC_ICDSPISR_OFFSET(n) (0x0d04 + GIC_OFFSET32(n))
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/* 0x0d80-0x0efc: Reserved */
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/* Software Generated Interrupt Register: 0x0f00 */
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#define GIC_ICDSGIR_OFFSET 0x0f00 /* Software Generated Interrupt Register */
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/* 0x0f0c-0x0fcc: Reserved */
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/* Peripheral Identification Registers: 0x0fd0-0xfe8 */
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#define GIC_ICDPIDR_OFFSET(n) (0x0fd0 + ((n) << 2))
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@ -225,19 +234,28 @@
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/* GIC Register Bit Definitions *********************************************/
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/* Interrupt Interface registers */
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/* CPU Interface Control Register -- without security extensions */
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#define GIC_ICCICR_ENABLE (1 << 0) /* Bit 0: Enable the CPU interface for this GIC */
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/* Bits 1-31: Reserved */
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/* CPU Interface Control Register -- with security extensions, non-secure copy */
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#define GIC_ICCICRU_ENABLEGRP1 (1 << 0) /* Bit 0: Enable Group 1 interrupts for the CPU */
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/* Bits 1-4: Reserved */
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#define GIC_ICCICRU_FIQBYPDISGRP1 (1 << 5) /* Bit 5: FIQ disabled for CPU Group 1 */
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#define GIC_ICCICRU_IRQBYPDISGRP1 (1 << 6) /* Bit 6: IRQ disabled for CPU Group 1 */
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/* Bits 7-8: Reserved */
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#define GIC_ICCICRU_EOIMODENS (1 << 9) /* Bit 9: Control EIOIR access (non-secure) */
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/* Bits 10-31: Reserved */
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/* CPU Interface Control Register -- with security extensions, secure copy */
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#define GIC_ICCICRS_ENABLEGRP0 (1 << 0) /* Bit 0: Enable Group 0 interrupts for the CPU */
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@ -251,7 +269,9 @@
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#define GIC_ICCICRS_IRQBYPDISGRP1 (1 << 8) /* Bit 6: IRQ disabled for CPU Group 1 */
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#define GIC_ICCICRS_EOIMODES (1 << 9) /* Bit 6: Control EIOIR access (secure) */
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#define GIC_ICCICRS_EOIMODENS (1 << 10) /* Bit 10: Control EIOIR access (non-secure) */
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/* Bits 11-31: Reserved */
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/* Interrupt Priority Mask Register. Priority values are 8-bit unsigned
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* binary. A GIC supports a minimum of 16 and a maximum of 256 priority
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* levels. As a result, PMR settings make sense.
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@ -260,7 +280,9 @@
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#define GIC_ICCPMR_SHIFT (0) /* Bits 0-7: Priority mask */
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#define GIC_ICCPMR_MASK (0xff << GIC_ICCPMR_SHIFT)
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#define GIC_ICCPMR_VALUE(n) ((uint32_t)(n) << GIC_ICCPMR_SHIFT)
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/* Bits 8-31: Reserved */
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/* Binary point Register and Aliased Non-secure Binary Point Register.
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* Priority values are 8-bit unsigned binary. A GIC supports a minimum of
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* 16 and a maximum of 256 priority levels. As a result, not all binary
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@ -277,7 +299,9 @@
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#define GIC_ICCBPR_6_7 (5 << GIC_ICCBPR_SHIFT) /* Priority bits [7:6] compared for pre-emption */
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#define GIC_ICCBPR_7_7 (6 << GIC_ICCBPR_SHIFT) /* Priority bit [7] compared for pre-emption */
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#define GIC_ICCBPR_NOPREMPT (7 << GIC_ICCBPR_SHIFT) /* No pre-emption is performed */
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/* Bits 3-31: Reserved */
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/* Interrupt Acknowledge Register */
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#define GIC_ICCIAR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */
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@ -286,7 +310,9 @@
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#define GIC_ICCIAR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */
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#define GIC_ICCIAR_CPUSRC_MASK (7 << GIC_ICCIAR_CPUSRC_SHIFT)
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#define GIC_ICCIAR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCIAR_CPUSRC_SHIFT)
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/* Bits 13-31: Reserved */
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/* End of Interrupt Register */
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#define GIC_ICCEOIR_SPURIOUS (0x3ff)
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@ -297,14 +323,19 @@
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#define GIC_ICCEOIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */
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#define GIC_ICCEOIR_CPUSRC_MASK (7 << GIC_ICCEOIR_CPUSRC_SHIFT)
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#define GIC_ICCEOIR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCEOIR_CPUSRC_SHIFT)
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/* Bits 13-31: Reserved */
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/* Running Interrupt Register */
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/* Bits 0-3: Reserved */
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#define GIC_ICCRPR_PRIO_SHIFT (4) /* Bits 4-7: Priority mask */
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#define GIC_ICCRPR_PRIO_MASK (15 << GIC_ICCRPR_PRIO_SHIFT)
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#define GIC_ICCRPR_PRIO_VALUE(n) ((uint32_t)(n) << GIC_ICCRPR_PRIO_SHIFT)
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/* Bits 8-31: Reserved */
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/* Highest Pending Interrupt Register */
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#define GIC_ICCHPIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */
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@ -313,6 +344,7 @@
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#define GIC_ICCHPIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */
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#define GIC_ICCHPIR_CPUSRC_MASK (7 << GIC_ICCHPIR_CPUSRC_SHIFT)
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#define GIC_ICCHPIR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCHPIR_CPUSRC_SHIFT)
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/* Bits 13-31: Reserved */
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/* CPU Interface Implementer ID Register */
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@ -327,22 +359,29 @@
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#define GIC_ICCIDR_PARTNO_MASK (0xfff << GIC_ICCIDR_PARTNO_SHIFT)
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/* Distributor Registers */
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/* Distributor Control Register */
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#define GIC_ICDDCR_NONSECENAB (1 << 0) /* Bit 0: Enable distributor for Non-secure interrupts */
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#define GIC_ICDDCR_SECENABLE (1 << 1) /* Bit 1: Enable distributor for Secure interrupts */
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/* Bits 2-31: Reserved */
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/* Interrupt Controller Type Register */
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#define GIC_ICDICTR_ITLINES_SHIFT (0) /* Bits 0-4: It lines number */
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#define GIC_ICDICTR_ITLINES_MASK (0x1f << GIC_ICDICTR_ITLINES_SHIFT)
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#define GIC_ICDICTR_CPUNO_SHIFT (5) /* Bits 5-7: CPU number */
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#define GIC_ICDICTR_CPUNO_MASK (7 << GIC_ICDICTR_CPUNO_SHIFT)
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/* Bits 8-9: Reserved */
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#define GIC_ICDICTR_SECEXTNS (1 << 10) /* Bit 10: Number of security domains */
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#define GIC_ICDICTR_LSPI_SHIFT (11) /* Bits 11-15: Number of Lockable Shared Peripheral Interrupts */
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#define GIC_ICDICTR_LSPI_MASK (0x1f << GIC_ICDICTR_LSPI_SHIFT)
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/* Bits 16-31: Reserved */
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/* Distributor Implementer ID Register */
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#define GIC_ICDIIDR_IMPL_SHIFT (0) /* Bits 0-11: Implementer */
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@ -430,11 +469,15 @@
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#define GIC_ICDSGIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */
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#define GIC_ICDSGIR_INTID_MASK (0x3ff << GIC_ICDSGIR_INTID_SHIFT)
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#define GIC_ICDSGIR_INTID(n) ((uint32_t)(n) << GIC_ICDSGIR_INTID_SHIFT)
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/* Bits 10-15: Reserved */
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#define GIC_ICDSGIR_CPUTARGET_SHIFT (16) /* Bits 16-23: CPU target */
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#define GIC_ICDSGIR_CPUTARGET_MASK (0xff << GIC_ICDSGIR_CPUTARGET_SHIFT)
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#define GIC_ICDSGIR_CPUTARGET(n) ((uint32_t)(n) << GIC_ICDSGIR_CPUTARGET_SHIFT)
|
||||
|
||||
/* Bits 26-31: Reserved */
|
||||
|
||||
#define GIC_ICDSGIR_TGTFILTER_SHIFT (24) /* Bits 24-25: Target filter */
|
||||
#define GIC_ICDSGIR_TGTFILTER_MASK (3 << GIC_ICDSGIR_TGTFILTER_SHIFT)
|
||||
#define GIC_ICDSGIR_TGTFILTER_LIST (0 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt sent to CPUs CPU target list */
|
||||
@ -442,6 +485,7 @@
|
||||
#define GIC_ICDSGIR_TGTFILTER_THIS (2 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt is sent to requesting CPU only */
|
||||
|
||||
/* Interrupt IDs ************************************************************/
|
||||
|
||||
/* The Global Interrupt Controller (GIC) collects up to 224 interrupt
|
||||
* requests and provides a memory mapped interface to each of the CPU core.
|
||||
*
|
||||
@ -457,6 +501,7 @@
|
||||
*/
|
||||
|
||||
/* Private Peripheral Interrupts (PPI) **************************************/
|
||||
|
||||
/* Each Cortex-A9 processor has private interrupts, ID0-ID15, that can only
|
||||
* be triggered by software. These interrupts are aliased so that there is
|
||||
* no requirement for a requesting Cortex-A9 processor to determine its own
|
||||
@ -502,7 +547,8 @@
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
@ -569,12 +615,12 @@ uint32_t *arm_decodeirq(uint32_t *regs);
|
||||
* If CONFIG_SMP is not selected, the cpuset is ignored and SGI is sent
|
||||
* only to the current CPU.
|
||||
*
|
||||
* Input Paramters
|
||||
* Input Parameters
|
||||
* sgi - The SGI interrupt ID (0-15)
|
||||
* cpuset - The set of CPUs to receive the SGI
|
||||
*
|
||||
* Returned Value:
|
||||
* OK is always retured at present.
|
||||
* OK is always returned at present.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* include files
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
@ -334,8 +334,8 @@ struct cxd56_scudev_s g_scudev;
|
||||
|
||||
/* SCU firmware (iSoP) */
|
||||
|
||||
extern const unsigned long scuIsopProgArray[];
|
||||
extern const unsigned long sizeOfscuIsopProgArray;
|
||||
extern const unsigned long scu_isopprog_array[];
|
||||
extern const unsigned long sizeof_scu_isopprog_array;
|
||||
|
||||
/* XXX: Convert coefficiencies register address. */
|
||||
|
||||
@ -368,6 +368,7 @@ static const struct coeff_addr_s g_caddrs[3][2] =
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: seq_semtake
|
||||
****************************************************************************/
|
||||
@ -503,6 +504,7 @@ static inline int8_t deci_alloc(void)
|
||||
|
||||
seq_inhibitrequest(REQ_SLEEP, true);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -1033,6 +1035,7 @@ static int seq_oneshot(int bustype, int slave, FAR uint16_t *inst,
|
||||
leave_critical_section(flags);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
/* Remake last instruction, if needed. */
|
||||
@ -1046,6 +1049,7 @@ static int seq_oneshot(int bustype, int slave, FAR uint16_t *inst,
|
||||
{
|
||||
putreg16(inst[i], SCUSEQ_INSTRUCTION(istart + i));
|
||||
}
|
||||
|
||||
putreg16(lastinst, SCUSEQ_INSTRUCTION(istart + nr_insts - 1));
|
||||
|
||||
/* Setup sequencer as oneshot mode
|
||||
@ -1133,6 +1137,7 @@ static void seq_offsetgainenable(int sid, bool enable)
|
||||
{
|
||||
val &= ~(1 << n);
|
||||
}
|
||||
|
||||
putreg32(val, SCU_OFST_GAIN_EN);
|
||||
}
|
||||
|
||||
@ -1419,6 +1424,7 @@ static int seq_setsamplingrate(FAR struct seq_s *seq, uint8_t samplingrate)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
seq->rate = samplingrate;
|
||||
|
||||
return OK;
|
||||
@ -1569,6 +1575,7 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv,
|
||||
getreg32(SCU_EVENT_TIMESTAMP0_R_LSB + (i * 8));
|
||||
notify->arg->type = SCU_EV_RISE;
|
||||
}
|
||||
|
||||
detected = 1;
|
||||
#endif
|
||||
}
|
||||
@ -1590,6 +1597,7 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv,
|
||||
getreg32(SCU_EVENT_TIMESTAMP0_F_LSB + (i * 8));
|
||||
notify->arg->type = SCU_EV_FALL;
|
||||
}
|
||||
|
||||
detected = 1;
|
||||
#endif
|
||||
}
|
||||
@ -1750,6 +1758,7 @@ static int seq_scuirqhandler(int irq, FAR void *context, FAR void *arg)
|
||||
seq_stopseq(i);
|
||||
}
|
||||
}
|
||||
|
||||
putreg32(0x03ff, SCU_INT_CLEAR_ERR_2);
|
||||
}
|
||||
|
||||
@ -1782,6 +1791,7 @@ static FAR struct seq_s *seq_new(void)
|
||||
leave_critical_section(flags);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
seq = (FAR struct seq_s *)kmm_malloc(sizeof(struct seq_s));
|
||||
@ -1790,6 +1800,7 @@ static FAR struct seq_s *seq_new(void)
|
||||
seq_free(sid);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
memset(seq, 0, sizeof(struct seq_s));
|
||||
|
||||
seq->id = sid;
|
||||
@ -1823,6 +1834,7 @@ static FAR struct seq_s *deci_new(void)
|
||||
leave_critical_section(flags);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
deci = (FAR struct decimator_s *)kmm_malloc(sizeof(struct decimator_s));
|
||||
@ -1831,6 +1843,7 @@ static FAR struct seq_s *deci_new(void)
|
||||
deci_free(sid);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
memset(deci, 0, sizeof(struct decimator_s));
|
||||
|
||||
deci->seq.id = sid;
|
||||
@ -2163,7 +2176,7 @@ static int seq_setadjustment(FAR struct seq_s *seq,
|
||||
* Description:
|
||||
* Set MATHFUNC IIR filter feature
|
||||
*
|
||||
* Input Paramters:
|
||||
* Input Parameters:
|
||||
* fifo - An instance of FIFO
|
||||
* pos - Where to IIR filter inserted
|
||||
* iir - IIR filter coefficiencies
|
||||
@ -2241,6 +2254,7 @@ static int seq_seteventnotifier(FAR struct scufifo_s *fifo,
|
||||
{
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
mid = fifo->mid;
|
||||
|
||||
#ifndef CONFIG_DISABLE_SIGNAL
|
||||
@ -2521,6 +2535,7 @@ static void seq_setfifomode(FAR struct seq_s *seq, int fifoid, int enable)
|
||||
{
|
||||
val |= (0x1 << 4);
|
||||
}
|
||||
|
||||
putreg32(val, SCUFIFO_W_CTRL1(fifo->wid));
|
||||
|
||||
if (enable)
|
||||
@ -2563,6 +2578,7 @@ static void seq_setfifomode(FAR struct seq_s *seq, int fifoid, int enable)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
@ -2616,6 +2632,7 @@ static void scu_hwinit(void)
|
||||
putreg32(0x08000000, SCUSEQ_MATH_PROC_OFST_GAIN_Y(i));
|
||||
putreg32(0x08000000, SCUSEQ_MATH_PROC_OFST_GAIN_Z(i));
|
||||
}
|
||||
|
||||
putreg32(0, SCU_OFST_GAIN_EN);
|
||||
|
||||
putreg32(0x0f0f0f00, SCU_DECIMATION_PARAM0);
|
||||
@ -2646,6 +2663,7 @@ static void scu_hwinit(void)
|
||||
putreg32(0x00010000, SCUFIFO_W_CTRL1(i));
|
||||
putreg32(0, SCUFIFO_W_CTRL1(i));
|
||||
}
|
||||
|
||||
for (i = 0; i < 14; i++)
|
||||
{
|
||||
putreg32(0x00010003, SCUFIFO_R_CTRL1(i));
|
||||
@ -2740,6 +2758,7 @@ FAR struct seq_s *seq_open(int type, int bustype)
|
||||
{
|
||||
seq = seq_new();
|
||||
}
|
||||
|
||||
if (!seq)
|
||||
{
|
||||
return NULL;
|
||||
@ -2798,6 +2817,7 @@ int seq_setinstruction(FAR struct seq_s *seq, const uint16_t *inst,
|
||||
{
|
||||
putreg16(inst[i], SCUSEQ_INSTRUCTION(istart + i));
|
||||
}
|
||||
|
||||
putreg16(lastinst, SCUSEQ_INSTRUCTION(istart + nr_insts - 1));
|
||||
|
||||
/* Set instruction parameters */
|
||||
@ -2937,7 +2957,7 @@ int seq_read(FAR struct seq_s *seq, int fifoid, FAR char *buffer, int length)
|
||||
int maxlen = 1024;
|
||||
int dmalen;
|
||||
int rest;
|
||||
int need_wakelock=0;
|
||||
int need_wakelock = 0;
|
||||
struct pm_cpu_wakelock_s wlock;
|
||||
wlock.info = PM_CPUWAKELOCK_TAG('S', 'C', 0);
|
||||
wlock.count = 0;
|
||||
@ -2971,6 +2991,7 @@ int seq_read(FAR struct seq_s *seq, int fifoid, FAR char *buffer, int length)
|
||||
|
||||
#ifdef CONFIG_CXD56_UDMAC
|
||||
/* Get sensor data from FIFO by uDMAC (PL230) */
|
||||
|
||||
/* TODO: Check DMA transfer limit or restart DMA to get all data. */
|
||||
|
||||
config.channel_cfg = CXD56_UDMA_SINGLE;
|
||||
@ -2999,12 +3020,14 @@ int seq_read(FAR struct seq_s *seq, int fifoid, FAR char *buffer, int length)
|
||||
config.channel_cfg |= CXD56_UDMA_XFERSIZE_WORD;
|
||||
maxlen = 4096;
|
||||
}
|
||||
if (((uint32_t)dst >= CXD56_RAM_BASE)
|
||||
&& ((uint32_t)dst <= (CXD56_RAM_BASE + CXD56_RAM_SIZE)))
|
||||
|
||||
if (((uint32_t)dst >= CXD56_RAM_BASE) &&
|
||||
((uint32_t)dst <= (CXD56_RAM_BASE + CXD56_RAM_SIZE)))
|
||||
{
|
||||
need_wakelock = 1;
|
||||
up_pm_acquire_wakelock(&wlock);
|
||||
}
|
||||
|
||||
rest = length;
|
||||
while (rest > 0)
|
||||
{
|
||||
@ -3022,13 +3045,15 @@ int seq_read(FAR struct seq_s *seq, int fifoid, FAR char *buffer, int length)
|
||||
length = length - rest;
|
||||
break;
|
||||
}
|
||||
|
||||
dst += dmalen;
|
||||
rest -= dmalen;
|
||||
}
|
||||
if (need_wakelock)
|
||||
{
|
||||
up_pm_release_wakelock(&wlock);
|
||||
}
|
||||
|
||||
if (need_wakelock)
|
||||
{
|
||||
up_pm_release_wakelock(&wlock);
|
||||
}
|
||||
#else
|
||||
/* Get sensor data from FIFO by PIO */
|
||||
|
||||
@ -3145,6 +3170,7 @@ int seq_ioctl(FAR struct seq_s *seq, int fifoid, int cmd, unsigned long arg)
|
||||
fifo = seq->fifo;
|
||||
seq->fifo = NULL;
|
||||
}
|
||||
|
||||
seq_fifofree(fifo);
|
||||
}
|
||||
break;
|
||||
@ -3444,8 +3470,8 @@ void scu_initialize(void)
|
||||
|
||||
/* Load firmware & clear data RAM */
|
||||
|
||||
memcpy((void *)CXD56_SCU_SEQ_IRAM_BASE, scuIsopProgArray,
|
||||
sizeOfscuIsopProgArray);
|
||||
memcpy((void *)CXD56_SCU_SEQ_IRAM_BASE, scu_isopprog_array,
|
||||
sizeof_scu_isopprog_array);
|
||||
memset((void *)CXD56_SCU_SEQ_DRAM_BASE, 0, 0x324);
|
||||
|
||||
/* Release SCU reset to bring up SCU firmware */
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* This file is generated at May 18 2016 16:19:52 */
|
||||
|
||||
const unsigned long scuIsopProgArray[] = {
|
||||
const unsigned long scu_isopprog_array[] = {
|
||||
0xf7f8d600, 0xa2024f86, 0x0001a200, 0x18004081,
|
||||
0x00008014, 0x00000000, 0x0000a207, 0x00000000,
|
||||
0x0000a070, 0xac2d4ec6, 0xd000ac27, 0x50a2e444,
|
||||
@ -441,4 +441,4 @@ const unsigned long scuIsopProgArray[] = {
|
||||
0xfc311011, 0xfc212000, 0x800621fc, 0xf338d100,
|
||||
0xf418d300, 0x1d320103, 0x0002f531, 0x0000a070,
|
||||
};
|
||||
const unsigned long sizeOfscuIsopProgArray = 7024; /* 0x00001b70 */
|
||||
const unsigned long sizeof_scu_isopprog_array = 7024; /* 0x00001b70 */
|
||||
|
||||
@ -1030,6 +1030,7 @@ static int kinetis_i2c_interrupt(int irq, void *context, void *arg)
|
||||
}
|
||||
|
||||
/* TODO: handle zero-length reads */
|
||||
|
||||
/* Dummy read to initiate reception */
|
||||
|
||||
dummy = kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
|
||||
@ -1395,8 +1396,7 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port)
|
||||
#endif
|
||||
|
||||
default:
|
||||
i2cerr("ERROR: Kinetis I2C Only suppors ports 0 and %d\n",
|
||||
KINETIS_NI2C - 1);
|
||||
i2cerr("ERROR: Unsupported I2C port %d\n", port);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -1410,9 +1410,11 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port)
|
||||
priv->refs--;
|
||||
goto errout;
|
||||
}
|
||||
|
||||
kinetis_i2c_sem_init(priv);
|
||||
kinetis_i2c_init(priv);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
return &priv->dev;
|
||||
@ -1420,7 +1422,6 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port)
|
||||
errout:
|
||||
leave_critical_section(flags);
|
||||
return NULL;
|
||||
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -102,7 +102,7 @@ struct lpc43_i2cdev_s
|
||||
struct i2c_master_s dev; /* Generic I2C device */
|
||||
unsigned int base; /* Base address of registers */
|
||||
uint16_t irqid; /* IRQ for this device */
|
||||
uint32_t baseFreq; /* branch frequency */
|
||||
uint32_t base_freq; /* branch frequency */
|
||||
|
||||
sem_t mutex; /* Only one thread can access at a time */
|
||||
sem_t wait; /* Place to wait for state machine completion */
|
||||
@ -169,18 +169,18 @@ static void lpc43_i2c_setfrequency(struct lpc43_i2cdev_s *priv,
|
||||
{
|
||||
/* asymetric per 400Khz I2C spec */
|
||||
|
||||
putreg32(priv->baseFreq / (83 + 47) * 47 / frequency,
|
||||
putreg32(priv->base_freq / (83 + 47) * 47 / frequency,
|
||||
priv->base + LPC43_I2C_SCLH_OFFSET);
|
||||
putreg32(priv->baseFreq / (83 + 47) * 83 / frequency,
|
||||
putreg32(priv->base_freq / (83 + 47) * 83 / frequency,
|
||||
priv->base + LPC43_I2C_SCLL_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 50/50 mark space ratio */
|
||||
|
||||
putreg32(priv->baseFreq / 100 * 50 / frequency,
|
||||
putreg32(priv->base_freq / 100 * 50 / frequency,
|
||||
priv->base + LPC43_I2C_SCLH_OFFSET);
|
||||
putreg32(priv->baseFreq / 100 * 50 / frequency,
|
||||
putreg32(priv->base_freq / 100 * 50 / frequency,
|
||||
priv->base + LPC43_I2C_SCLL_OFFSET);
|
||||
}
|
||||
|
||||
@ -295,7 +295,6 @@ static int lpc43_i2c_interrupt(int irq, FAR void *context, FAR void *arg)
|
||||
state &= 0xf8; /* state mask, only 0xX8 is possible */
|
||||
switch (state)
|
||||
{
|
||||
|
||||
case 0x08: /* A START condition has been transmitted. */
|
||||
case 0x10: /* A Repeated START condition has been transmitted. */
|
||||
/* Set address */
|
||||
@ -450,7 +449,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
|
||||
|
||||
if (port > 1)
|
||||
{
|
||||
i2cerr("ERROR: lpc I2C Only suppors ports 0 and 1\n");
|
||||
i2cerr("ERROR: lpc I2C only supports ports 0 and 1\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -465,7 +464,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
|
||||
priv = &g_i2c0dev;
|
||||
priv->base = LPC43_I2C0_BASE;
|
||||
priv->irqid = LPC43M4_IRQ_I2C0;
|
||||
priv->baseFreq = BOARD_ABP1_FREQUENCY;
|
||||
priv->base_freq = BOARD_ABP1_FREQUENCY;
|
||||
|
||||
/* Enable, set mode */
|
||||
|
||||
@ -498,7 +497,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
|
||||
priv = &g_i2c1dev;
|
||||
priv->base = LPC43_I2C1_BASE;
|
||||
priv->irqid = LPC43M4_IRQ_I2C1;
|
||||
priv->baseFreq = BOARD_ABP3_FREQUENCY;
|
||||
priv->base_freq = BOARD_ABP3_FREQUENCY;
|
||||
|
||||
/* No need to enable */
|
||||
|
||||
|
||||
@ -670,6 +670,7 @@ static int up_attach(struct uart_dev_s *dev)
|
||||
|
||||
up_enable_irq(priv->irq);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -789,6 +790,7 @@ static int up_interrupt(int irq, void *context, void *arg)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -801,7 +803,7 @@ static int up_interrupt(int irq, void *context, void *arg)
|
||||
*
|
||||
* Supported and un-supported LPC43 RS-485 features:
|
||||
*
|
||||
* RS-485/EIA-485 Normal Multidrop Mode (NMM) -- NOT suppored
|
||||
* RS-485/EIA-485 Normal Multidrop Mode (NMM) -- NOT supported
|
||||
*
|
||||
* In this mode, an address is detected when a received byte causes the
|
||||
* USART to set the parity error and generate an interrupt. When the
|
||||
@ -888,13 +890,13 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv,
|
||||
|
||||
#ifdef BOARD_LPC43_UART1_DTRDIR
|
||||
if (priv->dtrdir)
|
||||
{
|
||||
/* If we ar using DTR for direction then ensure the H/W is
|
||||
* configured correctly.
|
||||
*/
|
||||
{
|
||||
/* If we ar using DTR for direction then ensure the H/W is
|
||||
* configured correctly.
|
||||
*/
|
||||
|
||||
regval |= UART_RS485CTRL_SEL;
|
||||
}
|
||||
regval |= UART_RS485CTRL_SEL;
|
||||
}
|
||||
#endif
|
||||
|
||||
up_serialout(priv, LPC43_UART_RS485CTRL_OFFSET, regval);
|
||||
@ -936,7 +938,6 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv,
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
up_serialout(priv, LPC43_UART_RS485DLY_OFFSET, regval);
|
||||
}
|
||||
|
||||
@ -966,7 +967,7 @@ static inline int up_get_rs485_mode(struct up_dev_s *priv,
|
||||
|
||||
/* Assume disabled */
|
||||
|
||||
memset(mode, 0, sizeof(struct serial_rs485));
|
||||
memset(mode, 0, sizeof(struct serial_rs485));
|
||||
|
||||
/* If RS-485 mode is enabled, then the DCTRL will be set in the RS485CTRL
|
||||
* register.
|
||||
@ -1226,6 +1227,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
||||
priv->ier &= ~UART_IER_THREIE;
|
||||
up_serialout(priv, LPC43_UART_IER_OFFSET, priv->ier);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
|
||||
@ -70,6 +70,7 @@
|
||||
****************************************************************************/
|
||||
|
||||
/* Some sanity checks *******************************************************/
|
||||
|
||||
/* DMA configuration */
|
||||
|
||||
/* If DMA is enabled on any USART, then very that other pre-requisites
|
||||
@ -148,6 +149,7 @@
|
||||
* When streaming data, the generic serial layer will be called
|
||||
* every time the FIFO receives half this number of bytes.
|
||||
*/
|
||||
|
||||
# if !defined(CONFIG_STM32_HCIUART_RXDMA_BUFSIZE)
|
||||
# define CONFIG_STM32_HCIUART_RXDMA_BUFSIZE 32
|
||||
# endif
|
||||
@ -1070,7 +1072,7 @@ static ssize_t hciuart_copytorxbuffer(const struct hciuart_config_s *config)
|
||||
* incremented tail index would make the Rx buffer appear empty,
|
||||
* then we must stop the copy. If there is data pending in the Rx
|
||||
* DMA buffer, this could be very bad because a data overrun
|
||||
condition is likely to occur.
|
||||
* condition is likely to occur.
|
||||
*/
|
||||
|
||||
rxnext = rxtail + 1;
|
||||
@ -1342,7 +1344,7 @@ static void hciuart_line_configure(const struct hciuart_config_s *config)
|
||||
* usartdiv8 = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
usartdiv8 = ((config->apbclock << 1) + (baud >> 1)) / baud;
|
||||
usartdiv8 = ((config->apbclock << 1) + (baud >> 1)) / baud;
|
||||
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
@ -1608,7 +1610,9 @@ static int hciuart_configure(const struct hciuart_config_s *config)
|
||||
stm32_configgpio(pinset);
|
||||
|
||||
/* Configure CR2 */
|
||||
|
||||
/* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */
|
||||
|
||||
/* HCI UART spec: 1 stop bit */
|
||||
|
||||
regval = hciuart_getreg32(config, STM32_USART_CR2_OFFSET);
|
||||
@ -1617,6 +1621,7 @@ static int hciuart_configure(const struct hciuart_config_s *config)
|
||||
hciuart_putreg32(config, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Configure CR1 */
|
||||
|
||||
/* Clear TE, REm and all interrupt enable bits */
|
||||
|
||||
regval = hciuart_getreg32(config, STM32_USART_CR1_OFFSET);
|
||||
@ -1625,6 +1630,7 @@ static int hciuart_configure(const struct hciuart_config_s *config)
|
||||
hciuart_putreg32(config, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure CR3 */
|
||||
|
||||
/* Clear CTSE, RTSE, and all interrupt enable bits */
|
||||
|
||||
regval = hciuart_getreg32(config, STM32_USART_CR3_OFFSET);
|
||||
@ -1737,7 +1743,7 @@ static int hciuart_interrupt(int irq, void *context, void *arg)
|
||||
* USART_CR1_IDLEIE USART_SR_IDLE Idle Line Detected (not used)
|
||||
* USART_CR1_RXNEIE USART_SR_RXNE Received Data Ready to be Read
|
||||
* " " USART_SR_ORE Overrun Error Detected
|
||||
* USART_CR1_TCIE USART_SR_TC Transmission Complete (used only for RS-485)
|
||||
* USART_CR1_TCIE USART_SR_TC Transmission Complete (only for RS-485)
|
||||
* USART_CR1_TXEIE USART_SR_TXE Transmit Data Register Empty
|
||||
* USART_CR1_PEIE USART_SR_PE Parity Error (No parity)
|
||||
*
|
||||
@ -1983,8 +1989,8 @@ static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower,
|
||||
flags = spin_lock_irqsave();
|
||||
if (enable)
|
||||
{
|
||||
/* Receive an interrupt when their is anything in the Rx data register (or an Rx
|
||||
* timeout occurs).
|
||||
/* Receive an interrupt when their is anything in the Rx data
|
||||
* register (or an Rx timeout occurs).
|
||||
*/
|
||||
|
||||
intset = USART_CR1_RXNEIE | USART_CR3_EIE;
|
||||
@ -2180,11 +2186,11 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower,
|
||||
/* Make sure that the Tx Interrupts are disabled.
|
||||
* USART transmit interrupts:
|
||||
*
|
||||
* Enable Status Meaning Usage
|
||||
* ------------------ --------------- ---------------------------- ----------
|
||||
* USART_CR1_TCIE USART_SR_TC Transmission Complete (used only for RS-485)
|
||||
* USART_CR1_TXEIE USART_SR_TXE Transmit Data Register Empty
|
||||
* USART_CR3_CTSIE USART_SR_CTS CTS flag (not used)
|
||||
* Enable Status Meaning Usage
|
||||
* ---------------- ------------- ---------------------------- ----------
|
||||
* USART_CR1_TCIE USART_SR_TC Transmission Complete (only for RS-485)
|
||||
* USART_CR1_TXEIE USART_SR_TXE Transmit Data Register Empty
|
||||
* USART_CR3_CTSIE USART_SR_CTS CTS flag (not used)
|
||||
*/
|
||||
|
||||
flags = spin_lock_irqsave();
|
||||
@ -2199,6 +2205,7 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower,
|
||||
while (remaining > 0)
|
||||
{
|
||||
/* Copy bytes to the tail of the Tx buffer */
|
||||
|
||||
/* Get a copy of the rxhead and rxtail indices of the Tx buffer */
|
||||
|
||||
txhead = state->txhead;
|
||||
@ -2410,28 +2417,24 @@ static void hciuart_pm_notify(struct pm_callback_s *cb, int domain,
|
||||
case(PM_NORMAL):
|
||||
{
|
||||
/* Logic for PM_NORMAL goes here */
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
case(PM_IDLE):
|
||||
{
|
||||
/* Logic for PM_IDLE goes here */
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
case(PM_STANDBY):
|
||||
{
|
||||
/* Logic for PM_STANDBY goes here */
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
case(PM_SLEEP):
|
||||
{
|
||||
/* Logic for PM_SLEEP goes here */
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
@ -2547,12 +2550,6 @@ const struct btuart_lowerhalf_s *hciuart_instantiate(enum hciuart_devno_e uart)
|
||||
* Performs the low-level, one-time USART initialization. This must be
|
||||
* called before hciuart_instantiate.
|
||||
*
|
||||
* Input Paramters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hciuart_initialize(void)
|
||||
@ -2609,12 +2606,6 @@ void hciuart_initialize(void)
|
||||
*
|
||||
* This function should be called from a timer or other periodic context.
|
||||
*
|
||||
* Input Paramters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_HCIUART_RXDMA
|
||||
@ -2659,7 +2650,9 @@ void stm32_serial_dma_poll(void)
|
||||
#ifdef CONFIG_STM32_HCIUART7_RXDMA
|
||||
if (g_hciuart7_config.state->rxdmastream != NULL)
|
||||
{
|
||||
hciuart_dma_rxcallback(g_hciuart7_config.state->rxdmastream, 0, &g_hciuart7_config);
|
||||
hciuart_dma_rxcallback(g_hciuart7_config.state->rxdmastream,
|
||||
0,
|
||||
&g_hciuart7_config);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -86,12 +86,6 @@ const struct btuart_lowerhalf_s *hciuart_instantiate(enum hciuart_devno_e uart);
|
||||
* Performs the low-level, one-time USART initialization. This must be
|
||||
* called before hciuart_instantiate.
|
||||
*
|
||||
* Input Paramters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hciuart_initialize(void);
|
||||
@ -105,12 +99,6 @@ void hciuart_initialize(void);
|
||||
*
|
||||
* This function should be called from a timer or other periodic context.
|
||||
*
|
||||
* Input Paramters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_HCIUART_RXDMA
|
||||
|
||||
@ -233,7 +233,6 @@
|
||||
APB2EN_ADC12 | APB2EN_CKOUT | APB2EN_TIM0 | APB2EN_TIM1 | \
|
||||
APB2EN_TIM2 | APB2EN_TIM3 | APB2EN_RTC | APB2EN_EIC)
|
||||
|
||||
|
||||
#if STR71X_PLL1OUT_MUL == 12
|
||||
# define PLL1MUL STR71X_RCCUPLL1CR_MUL12
|
||||
#elif STR71X_PLL1OUT_MUL == 16
|
||||
@ -243,7 +242,7 @@
|
||||
#elif STR71X_PLL1OUT_MUL == 24
|
||||
# define PLL1MUL STR71X_RCCUPLL1CR_MUL24
|
||||
#else
|
||||
# error "Unsupporetd value for STR71X_PLL1OUT_MUL"
|
||||
# error "Unsupported value for STR71X_PLL1OUT_MUL"
|
||||
#endif
|
||||
|
||||
#if STR71X_PLL1OUT_DIV == 1
|
||||
@ -309,7 +308,7 @@
|
||||
#elif STR71X_PLL2OUT_MUL == 28
|
||||
# define PLL2MUL STR71X_PCUPPL2CR_MUL28
|
||||
#else
|
||||
# error "Unsupporetd value for STR71X_PLL2OUT_MUL"
|
||||
# error "Unsupported value for STR71X_PLL2OUT_MUL"
|
||||
#endif
|
||||
|
||||
#if STR71X_PLL2OUT_DIV == 1
|
||||
@ -453,7 +452,9 @@ void str71x_prccuinit(void)
|
||||
putreg16(reg16, STR71X_PCU_PLL2CR);
|
||||
|
||||
/* Wait for PLL2 to lock in */
|
||||
// while ((getreg16(STR71X_PCU_PLL2CR) & STR71X_PCUPPL2CR_LOCK) == 0);
|
||||
|
||||
/* while ((getreg16(STR71X_PCU_PLL2CR) & STR71X_PCUPPL2CR_LOCK) == 0); */
|
||||
|
||||
#endif
|
||||
|
||||
/* Select the USB clock source */
|
||||
@ -473,4 +474,3 @@ void str71x_prccuinit(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -85,7 +85,8 @@
|
||||
* it is an option to select that
|
||||
* VIMS power domain shall not
|
||||
* power up during the next wake
|
||||
* up from uLDO (VIMS_MODE=0b10). */
|
||||
* up from uLDO (VIMS_MODE=0b10).
|
||||
*/
|
||||
|
||||
/* Encoded values used for enabling and disabling peripheral modules in the
|
||||
* MCU domain. Encoding:
|
||||
@ -265,7 +266,7 @@ static inline void prcm_gptclock_set(uint32_t clkdiv)
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Name:
|
||||
* Name:
|
||||
*
|
||||
* Description:
|
||||
* Get the clock division factor for the GP-Timer domain.
|
||||
@ -326,7 +327,7 @@ static inline void prcm_load_set(void)
|
||||
static inline bool prcm_load_get(void)
|
||||
{
|
||||
/* Return the load status. */
|
||||
|
||||
|
||||
return ((getreg32(TIVA_PRCM_CLKLOADCTL) & PRCM_CLKLOADCTL_LOADDONE) != 0);
|
||||
}
|
||||
|
||||
@ -395,7 +396,7 @@ static inline void prcm_domain_disable(uint32_t domains)
|
||||
(domains & PRCM_DOMAIN_VIMS) != 0);
|
||||
|
||||
/* Disable the power domains. */
|
||||
|
||||
|
||||
if ((domains & PRCM_DOMAIN_RFCORE) != 0)
|
||||
{
|
||||
putreg32(0, TIVA_PRCM_RFCCLKG);
|
||||
@ -719,7 +720,7 @@ bool prcm_powerdomain_status(uint32_t domains);
|
||||
* system controller in the AON domain a call to this function should always
|
||||
* be followed by a call to prcm_load_set().
|
||||
*
|
||||
* Input Paramters:
|
||||
* Input Parameters:
|
||||
* peripheral - The peripheral to enable. This is an encoded value. See the
|
||||
* PRCRM_PERIPH_* definitions for available encodings.
|
||||
*
|
||||
@ -749,7 +750,7 @@ void prcm_periph_runenable(uint32_t peripheral);
|
||||
* ensure that the peripheral is not accessed in this interval as this might
|
||||
* cause the system to hang.
|
||||
*
|
||||
* Input Paramters:
|
||||
* Input Parameters:
|
||||
* peripheral - The peripheral to enable. This is an encoded value. See the
|
||||
* PRCRM_PERIPH_* definitions for available encodings.
|
||||
*
|
||||
|
||||
@ -908,10 +908,11 @@ static ssize_t hciuart_copytotxfifo(const struct hciuart_config_s *config)
|
||||
{
|
||||
#ifdef CONFIG_TIVA_HCIUART_SW_TXFLOW
|
||||
if (tiva_gpioread(config->cts_gpio))
|
||||
{
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Is the transmit data register empty?
|
||||
*
|
||||
* Transmit data register empty
|
||||
@ -1135,6 +1136,7 @@ static int hciuart_interrupt(int irq, void *context, void *arg)
|
||||
tiva_gpiowrite(config->rts_gpio, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Received data ready... copy data from the Rx FIFO to the Rx
|
||||
* buffer.
|
||||
*/
|
||||
@ -1150,6 +1152,7 @@ static int hciuart_interrupt(int irq, void *context, void *arg)
|
||||
tiva_gpiowrite(config->rts_gpio, false);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Is there anything in the Rx buffer? Has the user registered an
|
||||
* Rx callback function?
|
||||
*/
|
||||
@ -1508,6 +1511,7 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower,
|
||||
while (remaining > 0)
|
||||
{
|
||||
/* Copy bytes to the tail of the Tx buffer */
|
||||
|
||||
/* Get a copy of the rxhead and rxtail indices of the Tx buffer */
|
||||
|
||||
txhead = state->txhead;
|
||||
@ -1675,32 +1679,29 @@ static void hciuart_pm_notify(struct pm_callback_s *cb, int domain,
|
||||
case(PM_NORMAL):
|
||||
{
|
||||
/* Logic for PM_NORMAL goes here */
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
case(PM_IDLE):
|
||||
{
|
||||
/* Logic for PM_IDLE goes here */
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
case(PM_STANDBY):
|
||||
{
|
||||
/* Logic for PM_STANDBY goes here */
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
case(PM_SLEEP):
|
||||
{
|
||||
/* Logic for PM_SLEEP goes here */
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
/* Should not get here */
|
||||
|
||||
break;
|
||||
@ -1813,12 +1814,6 @@ hciuart_instantiate(enum hciuart_devno_e uart)
|
||||
* Performs the low-level, one-time UART initialization. This must be
|
||||
* called before hciuart_instantiate.
|
||||
*
|
||||
* Input Paramters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hciuart_initialize(void)
|
||||
@ -1830,7 +1825,7 @@ void hciuart_initialize(void)
|
||||
|
||||
/* Configure all UARTs */
|
||||
|
||||
for (i = 0; i < sizeof(g_hciuarts)/sizeof(g_hciuarts[0]); i++)
|
||||
for (i = 0; i < sizeof(g_hciuarts) / sizeof(g_hciuarts[0]); i++)
|
||||
{
|
||||
config = g_hciuarts[i];
|
||||
if (config != NULL)
|
||||
|
||||
@ -104,12 +104,6 @@ hciuart_instantiate(enum hciuart_devno_e uart);
|
||||
* Performs the low-level, one-time USART initialization. This must be
|
||||
* called before hciuart_instantiate.
|
||||
*
|
||||
* Input Paramters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void hciuart_initialize(void);
|
||||
@ -123,12 +117,6 @@ void hciuart_initialize(void);
|
||||
*
|
||||
* This function should be called from a timer or other periodic context.
|
||||
*
|
||||
* Input Paramters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_TIVA_HCIUART_RXDMA
|
||||
|
||||
@ -68,6 +68,7 @@
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ***************************************************************/
|
||||
|
||||
/* PLL Settings are based on F_CPU frequency which is defined in the board.h file */
|
||||
|
||||
#if (BOARD_CPU_CLOCK == 8000000)
|
||||
@ -79,7 +80,7 @@
|
||||
# define USB_PLL_PSC ((1 << PLLP2) | (1 << PLLP0))
|
||||
# endif
|
||||
#else
|
||||
# error "Unsuppored CPU clock"
|
||||
# error "Unsupported CPU clock"
|
||||
#endif
|
||||
|
||||
/* Debug ***********************************************************************/
|
||||
@ -214,7 +215,8 @@ struct avr_ep_s
|
||||
{
|
||||
/* Common endpoint fields. This must be the first thing defined in the
|
||||
* structure so that it is possible to simply cast from struct usbdev_ep_s
|
||||
* to struct avr_ep_s. */
|
||||
* to struct avr_ep_s.
|
||||
*/
|
||||
|
||||
struct usbdev_ep_s ep; /* Standard endpoint structure */
|
||||
|
||||
@ -233,7 +235,8 @@ struct avr_usbdev_s
|
||||
{
|
||||
/* Common device fields. This must be the first thing defined in the
|
||||
* structure so that it is possible to simply cast from struct usbdev_s to
|
||||
* struct avr_usbdev_s. */
|
||||
* struct avr_usbdev_s.
|
||||
*/
|
||||
|
||||
struct usbdev_s usbdev;
|
||||
|
||||
@ -277,12 +280,12 @@ static inline void avr_rqenqueue(FAR struct avr_ep_s *privep,
|
||||
static void avr_txready(void);
|
||||
static int avr_fifoready(int timeout);
|
||||
static void avr_ep0send(FAR const uint8_t *buffer, uint16_t buflen);
|
||||
static inline int avr_epNsend(FAR struct avr_ep_s *privep,
|
||||
static inline int avr_ep_nsend(FAR struct avr_ep_s *privep,
|
||||
FAR struct avr_req_s *privreq);
|
||||
static inline int avr_epNrecv(FAR struct avr_ep_s *privep,
|
||||
static inline int avr_ep_nrecv(FAR struct avr_ep_s *privep,
|
||||
FAR struct usbdev_req_s *req);
|
||||
static int avr_epINqueue(FAR struct avr_ep_s *privep);
|
||||
static int avr_epOUTqueue(FAR struct avr_ep_s *privep);
|
||||
static int avr_ep_in_queue(FAR struct avr_ep_s *privep);
|
||||
static int avr_ep_out_queue(FAR struct avr_ep_s *privep);
|
||||
static void avr_reqcomplete(FAR struct avr_ep_s *privep, FAR struct avr_req_s *privreq,
|
||||
int result);
|
||||
static void avr_cancelrequests(FAR struct avr_ep_s *privep, int status);
|
||||
@ -478,12 +481,14 @@ static int avr_fifoready(int timeout)
|
||||
}
|
||||
|
||||
/* Timeing is driven by the start of frame (SOF) interrupt which we
|
||||
* assume here to be at a one millisecond rate. */
|
||||
* assume here to be at a one millisecond rate.
|
||||
*/
|
||||
|
||||
if ((UDINT & (1 << SOFI)) != 0)
|
||||
{
|
||||
/* Clear the SOF interrupt decrement the count of elapsed
|
||||
* milliseconds */
|
||||
* milliseconds
|
||||
*/
|
||||
|
||||
UDINT &= ~(1 << SOFI);
|
||||
|
||||
@ -579,14 +584,14 @@ static void avr_ep0send(FAR const uint8_t *buffer, uint16_t buflen)
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: avr_epNsend
|
||||
* Name: avr_ep_nsend
|
||||
*
|
||||
* Description:
|
||||
* Perform a TX transfer for Endpoint N
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int avr_epNsend(FAR struct avr_ep_s *privep,
|
||||
static inline int avr_ep_nsend(FAR struct avr_ep_s *privep,
|
||||
FAR struct avr_req_s *privreq)
|
||||
{
|
||||
FAR struct usbdev_req_s *req;
|
||||
@ -724,7 +729,8 @@ static inline int avr_epNsend(FAR struct avr_ep_s *privep,
|
||||
{
|
||||
/* If the endpoint simply did not become ready within the timeout,
|
||||
* then handle the remainder of the transfer asynchronously in the
|
||||
* TXINI interrupt handler. */
|
||||
* TXINI interrupt handler.
|
||||
*/
|
||||
|
||||
if (ret == -ETIME)
|
||||
{
|
||||
@ -746,14 +752,14 @@ static inline int avr_epNsend(FAR struct avr_ep_s *privep,
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: avr_epNrecv
|
||||
* Name: avr_ep_nrecv
|
||||
*
|
||||
* Description:
|
||||
* Perform an RX transfer for Endpoint N
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int avr_epNrecv(FAR struct avr_ep_s *privep,
|
||||
static inline int avr_ep_nrecv(FAR struct avr_ep_s *privep,
|
||||
FAR struct usbdev_req_s *req)
|
||||
{
|
||||
FAR uint8_t *buffer;
|
||||
@ -779,7 +785,8 @@ static inline int avr_epNrecv(FAR struct avr_ep_s *privep,
|
||||
while (req->xfrd < req->len)
|
||||
{
|
||||
/* RWAL will be de-asserted when everything has been read from the
|
||||
* receive FIFO */
|
||||
* receive FIFO
|
||||
*/
|
||||
|
||||
if (((UEINTX & (1 << RWAL)) == 0))
|
||||
{
|
||||
@ -828,7 +835,7 @@ static inline int avr_epNrecv(FAR struct avr_ep_s *privep,
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: avr_epINqueue
|
||||
* Name: avr_ep_in_queue
|
||||
*
|
||||
* Description:
|
||||
* This is part of the IN endpoint interrupt handling logic. It is called
|
||||
@ -838,7 +845,7 @@ static inline int avr_epNrecv(FAR struct avr_ep_s *privep,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int avr_epINqueue(FAR struct avr_ep_s *privep)
|
||||
static int avr_ep_in_queue(FAR struct avr_ep_s *privep)
|
||||
{
|
||||
FAR struct avr_req_s *privreq;
|
||||
int ret = OK;
|
||||
@ -867,7 +874,7 @@ static int avr_epINqueue(FAR struct avr_ep_s *privep)
|
||||
{
|
||||
/* Yes.. perform the IN transfer */
|
||||
|
||||
ret = avr_epNsend(privep, privreq);
|
||||
ret = avr_ep_nsend(privep, privreq);
|
||||
|
||||
/* The return value of -ETIME means that the transfer was not
|
||||
* finished within this interrupt. We just need to exit with the
|
||||
@ -885,11 +892,12 @@ static int avr_epINqueue(FAR struct avr_ep_s *privep)
|
||||
avr_reqcomplete(privep, privreq, ret);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: avr_epOUTqueue
|
||||
* Name: avr_ep_out_queue
|
||||
*
|
||||
* Description:
|
||||
* This is part of the OUT endpointeinterrupt handling logic. It is called
|
||||
@ -898,7 +906,7 @@ static int avr_epINqueue(FAR struct avr_ep_s *privep)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int avr_epOUTqueue(FAR struct avr_ep_s *privep)
|
||||
static int avr_ep_out_queue(FAR struct avr_ep_s *privep)
|
||||
{
|
||||
FAR struct avr_req_s *privreq;
|
||||
int ret = OK;
|
||||
@ -915,7 +923,7 @@ static int avr_epOUTqueue(FAR struct avr_ep_s *privep)
|
||||
{
|
||||
/* Yes.. perform the OUT transfer */
|
||||
|
||||
ret = avr_epNrecv(privep, &privreq->req);
|
||||
ret = avr_ep_nrecv(privep, &privreq->req);
|
||||
|
||||
/* The transfer has completed, perhaps with an error. Return the request
|
||||
* to the class driver.
|
||||
@ -924,6 +932,7 @@ static int avr_epOUTqueue(FAR struct avr_ep_s *privep)
|
||||
usbtrace(TRACE_COMPLETE(privep->ep.eplog), privreq->req.xfrd);
|
||||
avr_reqcomplete(privep, privreq, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -939,7 +948,8 @@ static void avr_reqcomplete(FAR struct avr_ep_s *privep, FAR struct avr_req_s *p
|
||||
int result)
|
||||
{
|
||||
/* If endpoint 0, temporarily reflect the state of protocol stalled in the
|
||||
* callback. */
|
||||
* callback.
|
||||
*/
|
||||
|
||||
bool stalled = privep->stalled;
|
||||
if (privep->ep.eplog == AVR_EP0)
|
||||
@ -1212,7 +1222,8 @@ static void avr_usbreset(void)
|
||||
}
|
||||
|
||||
/* Tell the class driver that we are disconnected. The class driver should
|
||||
* then accept any new configurations. */
|
||||
* then accept any new configurations.
|
||||
*/
|
||||
|
||||
if (g_usbdev.driver)
|
||||
{
|
||||
@ -1453,6 +1464,7 @@ static inline void avr_ep0setup(void)
|
||||
{
|
||||
g_usbdev.ep0buf[0] = 0; /* Not stalled */
|
||||
}
|
||||
|
||||
g_usbdev.ep0buf[1] = 0;
|
||||
|
||||
/* And send the response */
|
||||
@ -1469,6 +1481,7 @@ static inline void avr_ep0setup(void)
|
||||
usbtrace(TRACE_INTDECODE(AVR_TRACEINTID_DEVGETSTATUS), 0);
|
||||
|
||||
/* Features: Remote Wakeup=YES; selfpowered=? */
|
||||
|
||||
/* Return self-powered status */
|
||||
|
||||
#ifdef CONFIG_USBDEV_SELFPOWERED
|
||||
@ -1484,6 +1497,7 @@ static inline void avr_ep0setup(void)
|
||||
status |= (1 << USB_FEATURE_REMOTEWAKEUP);
|
||||
}
|
||||
#endif
|
||||
|
||||
g_usbdev.ep0buf[1] = 0;
|
||||
|
||||
/* And send the response */
|
||||
@ -1798,14 +1812,14 @@ static inline void avr_ep0interrupt(void)
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: avr_epNinterrupt
|
||||
* Name: avr_ep_ninterrupt
|
||||
*
|
||||
* Description:
|
||||
* USB endpoint/pipe IN interrupt handler
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void avr_epNinterrupt(void)
|
||||
static inline void avr_ep_ninterrupt(void)
|
||||
{
|
||||
struct avr_ep_s *privep;
|
||||
uint8_t ueint = UEINT & (g_usbdev.epoutset | g_usbdev.epinset);
|
||||
@ -1845,7 +1859,7 @@ static inline void avr_epNinterrupt(void)
|
||||
|
||||
/* Handle the IN request queue */
|
||||
|
||||
avr_epINqueue(privep);
|
||||
avr_ep_in_queue(privep);
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -1862,7 +1876,7 @@ static inline void avr_epNinterrupt(void)
|
||||
|
||||
/* Handle the OUT request queue */
|
||||
|
||||
avr_epOUTqueue(privep);
|
||||
avr_ep_out_queue(privep);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1887,7 +1901,7 @@ static int avr_epinterrupt(int irq, FAR void *context, FAR void *arg)
|
||||
|
||||
/* Handle opther endpoint interrupts (N=1,2,..6 */
|
||||
|
||||
avr_epNinterrupt();
|
||||
avr_ep_ninterrupt();
|
||||
|
||||
usbtrace(TRACE_INTEXIT(AVR_TRACEINTID_EPINT), irq);
|
||||
return OK;
|
||||
@ -1921,6 +1935,7 @@ static void avr_genvbus(void)
|
||||
else if (g_usbdev.connected && !vbus)
|
||||
{
|
||||
/* We were connected, but now we are not */
|
||||
|
||||
/* Cancel all pending and queue requests */
|
||||
|
||||
avr_cancelall(-ENODEV);
|
||||
@ -1930,7 +1945,8 @@ static void avr_genvbus(void)
|
||||
UDCON |= (1 << DETACH);
|
||||
|
||||
/* Disable the clock inputs (the ”Resume Detection” is still active).
|
||||
* This reduces the power consumption. Clear to enable the clock inputs. */
|
||||
* This reduces the power consumption. Clear to enable the clock inputs.
|
||||
*/
|
||||
|
||||
USBCON |= (1 << FRZCLK);
|
||||
|
||||
@ -2201,6 +2217,7 @@ static int avr_epconfigure(FAR struct usbdev_ep_s *ep,
|
||||
uecfg1x |= AVR_EPSIZE_8;
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
usbtrace(TRACE_DEVERROR(AVR_TRACEERR_PKTSIZE), maxpacket);
|
||||
return -EINVAL;
|
||||
@ -2254,6 +2271,7 @@ static int avr_epdisable(FAR struct usbdev_ep_s *ep)
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
usbtrace(TRACE_EPDISABLE, privep->ep.eplog);
|
||||
|
||||
flags = enter_critical_section();
|
||||
@ -2286,6 +2304,7 @@ static FAR struct usbdev_req_s *avr_epallocreq(FAR struct usbdev_ep_s *ep)
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
usbtrace(TRACE_EPALLOCREQ, ((FAR struct avr_ep_s *)ep)->ep.eplog);
|
||||
|
||||
privreq = (FAR struct avr_req_s *)kmm_malloc(sizeof(struct avr_req_s));
|
||||
@ -2448,7 +2467,7 @@ static int avr_epsubmit(FAR struct usbdev_ep_s *ep,
|
||||
{
|
||||
/* No, then start the next IN transfer */
|
||||
|
||||
ret = avr_epINqueue(privep);
|
||||
ret = avr_ep_in_queue(privep);
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -2461,7 +2480,7 @@ static int avr_epsubmit(FAR struct usbdev_ep_s *ep,
|
||||
|
||||
if (avr_fifoready(AVR_TIMEOUT_NONE) == OK)
|
||||
{
|
||||
ret = avr_epOUTqueue(privep);
|
||||
ret = avr_ep_out_queue(privep);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -2496,7 +2515,8 @@ static int avr_epcancel(FAR struct usbdev_ep_s *ep,
|
||||
|
||||
/* FIXME: if the request is the first, then we need to flush the EP otherwise
|
||||
* just remove it from the list but ... all other implementations cancel all
|
||||
* requests ... */
|
||||
* requests ...
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
avr_cancelrequests(privep, -ESHUTDOWN);
|
||||
@ -2534,6 +2554,7 @@ static int avr_epstall(FAR struct usbdev_ep_s *ep, bool resume)
|
||||
UECONX |= (1 << STALLRQ);
|
||||
g_usbdev.stalled = true;
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
return OK;
|
||||
}
|
||||
@ -2592,7 +2613,8 @@ static FAR struct usbdev_ep_s *avr_allocep(FAR struct usbdev_s *dev,
|
||||
|
||||
/* Convert the logical address to a physical OUT endpoint address and
|
||||
* remove all of the candidate endpoints from the bitset except for the
|
||||
* the IN/OUT pair for this logical address. */
|
||||
* the IN/OUT pair for this logical address.
|
||||
*/
|
||||
|
||||
epset &= (1 << epno);
|
||||
}
|
||||
@ -2906,10 +2928,12 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
|
||||
* after the class has bound to us... GEN: This bug is really in the
|
||||
* class driver. It should make the soft connect when it is ready to be
|
||||
* enumerated. I have added that logic to the class drivers but left
|
||||
* this logic here. */
|
||||
* this logic here.
|
||||
*/
|
||||
|
||||
avr_pullup(&g_usbdev.usbdev, true);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@ -87,10 +87,10 @@
|
||||
|
||||
/* The Type of a spinlock.
|
||||
*
|
||||
* RISC-V architecture introuced the concept of exclusive accesses to memory
|
||||
* locations in the form of the Load-Reserved (LR) and Store-Conditional
|
||||
* (SC) instructions. RV64 supports doubleword aligned data only but others
|
||||
* supports word aligned data.
|
||||
* RISC-V architecture (in the standard atomic-instruction extension "A")
|
||||
* supports exclusive accesses to memory locations in the form of the
|
||||
* Load-Reserved (LR) and Store-Conditional (SC) instructions. RV64 supports
|
||||
* doubleword aligned data only but others supports word aligned data.
|
||||
*
|
||||
* RISC-V architecture supports fence instruction to ensure memory ordering
|
||||
*/
|
||||
|
||||
@ -929,7 +929,7 @@ static int hostfs_bind(FAR struct inode *blkdriver, FAR const void *data,
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* The options we suppor are:
|
||||
/* The options we support are:
|
||||
* "fs=whatever", remote dir
|
||||
*/
|
||||
|
||||
|
||||
@ -67,7 +67,7 @@
|
||||
* Equivalent to the standard write() function except that is accepts a
|
||||
* struct file instance instead of a file descriptor. It is functionally
|
||||
* equivalent to write() except that in addition to the differences in
|
||||
* input paramters:
|
||||
* input parameters:
|
||||
*
|
||||
* - It does not modify the errno variable,
|
||||
* - It is not a cancellation point, and
|
||||
|
||||
@ -1075,7 +1075,7 @@ ssize_t nx_read(int fd, FAR void *buf, size_t nbytes);
|
||||
* Equivalent to the standard write() function except that is accepts a
|
||||
* struct file instance instead of a file descriptor. It is functionally
|
||||
* equivalent to write() except that in addition to the differences in
|
||||
* input paramters:
|
||||
* input parameters:
|
||||
*
|
||||
* - It does not modify the errno variable,
|
||||
* - It is not a cancellation point, and
|
||||
|
||||
@ -49,6 +49,7 @@
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* CONFIG_CDCACM
|
||||
* Enable compilation of the USB serial driver
|
||||
* CONFIG_CDCACM_EP0MAXPACKET
|
||||
@ -259,6 +260,7 @@
|
||||
#endif
|
||||
|
||||
/* IOCTL Commands ***********************************************************/
|
||||
|
||||
/* The USB serial driver will support a subset of the TIOC IOCTL commands
|
||||
* defined in include/nuttx/serial/tioctl.h. This subset includes:
|
||||
*
|
||||
@ -368,7 +370,7 @@ int cdcacm_classobject(int minor, FAR struct usbdev_devinfo_s *devinfo,
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) means that the driver was successfully registered. On any
|
||||
* failure, a negated errno value is retured.
|
||||
* failure, a negated errno value is returned.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
@ -53,114 +53,169 @@
|
||||
/** @def BBT_UUID_GAP
|
||||
* @brief Generic Access
|
||||
*/
|
||||
|
||||
#define BT_UUID_GAP 0x1800
|
||||
|
||||
/** @def BBT_UUID_GATT
|
||||
* @brief Generic Attribute
|
||||
*/
|
||||
|
||||
#define BT_UUID_GATT 0x1801
|
||||
|
||||
/** @def BBT_UUID_CTS
|
||||
* @brief Current Time Service
|
||||
*/
|
||||
|
||||
#define BT_UUID_CTS 0x1805
|
||||
|
||||
/** @def BBT_UUID_DIS
|
||||
* @brief Device Information Service
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS 0x180a
|
||||
|
||||
/** @def BBT_UUID_HRS
|
||||
* @brief Heart Rate Service
|
||||
*/
|
||||
|
||||
#define BT_UUID_HRS 0x180d
|
||||
|
||||
/** @def BBT_UUID_BAS
|
||||
* @brief Battery Service
|
||||
*/
|
||||
|
||||
#define BT_UUID_BAS 0x180f
|
||||
|
||||
/** @def BT_UUID_GATT_PRIMARY
|
||||
* @brief GATT Primary Service
|
||||
*/
|
||||
|
||||
#define BT_UUID_GATT_PRIMARY 0x2800
|
||||
|
||||
/** @def BT_UUID_GATT_SECONDARY
|
||||
* @brief GATT Secondary Service
|
||||
*/
|
||||
|
||||
#define BT_UUID_GATT_SECONDARY 0x2801
|
||||
|
||||
/** @def BT_UUID_GATT_INCLUDE
|
||||
* @brief GATT Include Service
|
||||
*/
|
||||
|
||||
#define BT_UUID_GATT_INCLUDE 0x2802
|
||||
|
||||
/** @def BT_UUID_GATT_CHRC
|
||||
* @brief GATT Characteristic
|
||||
*/
|
||||
|
||||
#define BT_UUID_GATT_CHRC 0x2803
|
||||
|
||||
/** @def BT_UUID_GATT_CEP
|
||||
* @brief GATT Characteristic Extended Properties
|
||||
*/
|
||||
|
||||
#define BT_UUID_GATT_CEP 0x2900
|
||||
|
||||
/** @def BT_UUID_GATT_CUD
|
||||
* @brief GATT Characteristic User Description
|
||||
*/
|
||||
|
||||
#define BT_UUID_GATT_CUD 0x2901
|
||||
|
||||
/** @def BT_UUID_GATT_CCC
|
||||
* @brief GATT Client Characteristic Configuration
|
||||
*/
|
||||
|
||||
#define BT_UUID_GATT_CCC 0x2902
|
||||
|
||||
/** @def BT_UUID_GAP_DEVICE_NAME
|
||||
* @brief GAP Characteristic Device Name
|
||||
*/
|
||||
|
||||
#define BT_UUID_GAP_DEVICE_NAME 0x2a00
|
||||
|
||||
/** @def BT_UUID_GAP_APPEARANCE
|
||||
* @brief GAP Characteristic Appearance
|
||||
*/
|
||||
|
||||
#define BT_UUID_GAP_APPEARANCE 0x2a01
|
||||
|
||||
/** @def BT_UUID_BAS_BATTERY_LEVEL
|
||||
* @brief BAS Characteristic Battery Level
|
||||
*/
|
||||
|
||||
#define BT_UUID_BAS_BATTERY_LEVEL 0x2a19
|
||||
|
||||
/** @def BT_UUID_DIS_SYSTEM_ID
|
||||
* @brief DIS Characteristic System ID
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS_SYSTEM_ID 0x2a23
|
||||
|
||||
/** @def BT_UUID_DIS_MODEL_NUMBER_STRING
|
||||
* @brief DIS Characteristic Model Number String
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS_MODEL_NUMBER_STRING 0x2a24
|
||||
|
||||
/** @def BT_UUID_DIS_SERIAL_NUMBER_STRING
|
||||
* @brief DIS Characteristic Serial Number String
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS_SERIAL_NUMBER_STRING 0x2a25
|
||||
|
||||
/** @def BT_UUID_DIS_FIRMWARE_REVISION_STRING
|
||||
* @brief DIS Characteristic Firmware Revision String
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS_FIRMWARE_REVISION_STRING 0x2a26
|
||||
|
||||
/** @def BT_UUID_DIS_HARDWARE_REVISION_STRING
|
||||
* @brief DIS Characteristic Hardware Revision String
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS_HARDWARE_REVISION_STRING 0x2a27
|
||||
|
||||
/** @def BT_UUID_DIS_SOFTWARE_REVISION_STRING
|
||||
* @brief DIS Characteristic Software Revision String
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS_SOFTWARE_REVISION_STRING 0x2a28
|
||||
|
||||
/** @def BT_UUID_DIS_MANUFACTURER_NAME_STRING
|
||||
* @brief DIS Characteristic Manufacturer Name String
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS_MANUFACTURER_NAME_STRING 0x2a29
|
||||
|
||||
/** @def BT_UUID_DIS_PNP_ID
|
||||
* @brief DIS Characteristic PnP ID
|
||||
*/
|
||||
|
||||
#define BT_UUID_DIS_PNP_ID 0x2a50
|
||||
|
||||
/** @def BT_UUID_CTS_CURRENT_TIME
|
||||
* @brief CTS Characteristic Current Time
|
||||
*/
|
||||
|
||||
#define BT_UUID_CTS_CURRENT_TIME 0x2a2b
|
||||
|
||||
/** @def BT_UUID_HR_MEASUREMENT
|
||||
* @brief HRS Characteristic Measurement Interval
|
||||
*/
|
||||
|
||||
#define BT_UUID_HRS_MEASUREMENT 0x2a37
|
||||
|
||||
/** @def BT_UUID_HRS_BODY_SENSOR
|
||||
* @brief HRS Characteristic Body Sensor Location
|
||||
*/
|
||||
|
||||
#define BT_UUID_HRS_BODY_SENSOR 0x2a38
|
||||
|
||||
/** @def BT_UUID_HR_CONTROL_POINT
|
||||
* @brief HRS Characteristic Control Point
|
||||
*/
|
||||
|
||||
#define BT_UUID_HRS_CONTROL_POINT 0x2a39
|
||||
|
||||
/****************************************************************************
|
||||
@ -205,7 +260,7 @@ struct bt_uuid_s
|
||||
* Compares 2 Bluetooth UUIDs, if the types are different both UUIDs are
|
||||
* first converted to 128 bits format before comparing.
|
||||
*
|
||||
* Input Paramters:
|
||||
* Input Parameters:
|
||||
* u1 - First Bluetooth UUID to compare
|
||||
* u2 - Second Bluetooth UUID to compare
|
||||
*
|
||||
|
||||
@ -173,7 +173,7 @@ int pthread_spin_destroy(pthread_spinlock_t *lock)
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero is returned if the lock was successfully acquired. Otherwise one
|
||||
* of the following errno values are retured:
|
||||
* of the following errno values are returned:
|
||||
*
|
||||
* EINVAL - 'lock' does not refer to a valid spinlock object
|
||||
* EDEADLOCK - The caller already holds the spinlock
|
||||
@ -238,7 +238,7 @@ int pthread_spin_lock(pthread_spinlock_t *lock)
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero is returned if the lock was successfully acquired. Otherwise one
|
||||
* of the following errno values are retured:
|
||||
* of the following errno values are returned:
|
||||
*
|
||||
* EINVAL - 'lock' does not refer to a valid spinlock object
|
||||
* EBUSY - The spinlock is held by another thread
|
||||
@ -305,11 +305,11 @@ int pthread_spin_trylock(pthread_spinlock_t *lock)
|
||||
* lock - A reference to the spinlock object to unlock.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero is returned if the lock was successfully acquired. Otherwise one
|
||||
* of the following errno values are retured:
|
||||
* Zero is returned if the lock was successfully released. Otherwise one
|
||||
* of the following errno values are returned:
|
||||
*
|
||||
* EINVAL - 'lock' does not refer to a valid spinlock object
|
||||
* EDEADLOCK - The caller already holds the spinlock
|
||||
* EPERM - The caller does not hold the spinlock or it is not locked
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
@ -190,8 +190,8 @@ ssize_t psock_sendto(FAR struct socket *psock, FAR const void *buf,
|
||||
* tolen The length of the address structure
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, returns the number of characters sent. On any failure, a
|
||||
* negated errno value is returned. One of:
|
||||
* On success, returns the number of characters sent. On error,
|
||||
* -1 is returned, and errno is set appropriately:
|
||||
*
|
||||
* EAGAIN or EWOULDBLOCK
|
||||
* The socket is marked non-blocking and the requested operation
|
||||
|
||||
@ -455,7 +455,7 @@ config RR_INTERVAL
|
||||
default 0
|
||||
---help---
|
||||
The round robin timeslice will be set this number of milliseconds;
|
||||
Round roben scheduling (SCHED_RR) is enabled by setting this
|
||||
Round robin scheduling (SCHED_RR) is enabled by setting this
|
||||
interval to a positive, non-zero value.
|
||||
|
||||
config SCHED_SPORADIC
|
||||
|
||||
@ -56,7 +56,7 @@
|
||||
*
|
||||
* Input Parameters:
|
||||
* ts1 and ts2: The two timespecs to be added
|
||||
* t23: The location to return the result (may be ts1 or ts2)
|
||||
* ts3: The location to return the result (may be ts1 or ts2)
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
|
||||
@ -57,7 +57,7 @@
|
||||
*
|
||||
* Input Parameters:
|
||||
* ts1 and ts2: The two timespecs to be subtracted (ts1 - ts2)
|
||||
* t23: The location to return the result (may be ts1 or ts2)
|
||||
* ts3: The location to return the result (may be ts1 or ts2)
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user