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arch/stm32f0l0g0: Add support for STM32G0B1xx
Adds Kconfig and modifies chip.h for STM32G0B1xx options. Signed-off-by: Tyler Bennett <tbennett@2g-eng.com>
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@ -281,6 +281,39 @@
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \
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defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE)
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 6 /* 16-bit general purpose timers */
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# define STM32_NGTIM32 1 /* TIM2 */
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# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */
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/* One LPTIMER */
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# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */
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# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */
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# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */
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# define STM32_NUSART 6 /* Six USART modules, USART1-6 */
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/* Two LPUART */
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# define STM32_NCAN 1 /* One FDCAN controller */
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBDEV 1 /* One USB full-speed controller */
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# define STM32_NUSBOTG 0 /* No USB OTG */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* (1) ADC1, 12-channels */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 3 /* Three Analog Comparators */
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# define STM32_NCRC 0 /* No CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */
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/* STM32L EnergyLite Line ***************************************************/
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/* STM32L073XX - With LCD
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@ -531,6 +531,86 @@ config ARCH_CHIP_STM32G071RB
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KB
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bool "STM32G0B1KB"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CB
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bool "STM32G0B1CB"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RB
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bool "STM32G0B1RB"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1MB
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bool "STM32G0B1MB"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VB
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bool "STM32G0B1VB"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KC
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bool "STM32G0B1KC"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CC
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bool "STM32G0B1CC"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RC
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bool "STM32G0B1RC"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1MC
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bool "STM32G0B1MC"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VC
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bool "STM32G0B1VC"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1KE
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bool "STM32G0B1KE"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1CE
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bool "STM32G0B1CE"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1RE
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bool "STM32G0B1RE"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1NE
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bool "STM32G0B1NE"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1ME
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bool "STM32G0B1ME"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32G0B1VE
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bool "STM32G0B1VE"
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select STM32F0L0G0_STM32G0
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depends on ARCH_CHIP_STM32G0
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config ARCH_CHIP_STM32L053C8
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bool "STM32L053C8"
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select ARCH_CHIP_STM32L053XX
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