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fix gpio_set/reset for BL602/702/702L

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Cjacker 2023-03-04 14:55:09 +08:00 committed by sakumisu
parent eaab54e4f2
commit 12d9e69f1d
1 changed files with 9 additions and 5 deletions
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14
drivers/lhal/src/bflb_gpio.c
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@ -132,9 +132,11 @@ void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin)
void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin)
{
#if defined(BL702) || defined(BL602)
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
putreg32(regval | 1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
#elif defined(BL702L)
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
putreg32(regval | 1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG138_OFFSET + ((pin >> 5) << 2));
#endif
@ -143,9 +145,11 @@ void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin)
void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin)
{
#if defined(BL702) || defined(BL602)
putreg32(0 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
putreg32(regval & ~(1 << (pin & 0x1f)), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
#elif defined(BL702L)
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
putreg32(regval & ~(1 << (pin & 0x1f)), dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG140_OFFSET + ((pin >> 5) << 2));
#endif
@ -507,4 +511,4 @@ int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
break;
}
return ret;
}
}