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[update] update lhal for bl702l, update bl616 romapi patch

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This commit is contained in:
jzlv 2023-10-19 14:04:18 +08:00
parent ba9d3270a8
commit 27c24dd300
14 changed files with 429 additions and 100 deletions
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8
drivers/lhal/include/bflb_gpio.h
View File

@ -14,12 +14,13 @@
/**
* @brief Gpio pin definitions
*
* BL602 : GPIO0/1/2/7/8/14/15/20/21/22
* BL604 : GPIO0 ~ GPIO5, GPIO7/8/11/12/14/16/17/20/21/22
* BL606 : GPIO0 ~ GPIO22
* BL602 : GPIO0 ~ GPIO5, GPIO7/8/11/12/14/16/17/20/21/22
* BL604 : GPIO0 ~ GPIO22
* BL702 : GPIO0/1/2/7/8/9/14/15/17/23/24/25/26/27/28
* BL704 : GPIO0 ~ GPIO3, GPIO7 ~ GPIO11, GPIO14/15, GPIO17 ~ GPIO28,
* BL706 : GPIO0 ~ GPIO31
* BL702L : GPIO0 ~ GPIO2, GPIO7 ~ GPIO11, GPIO14 ~ GPIO18, GPIO22 ~ GPIO28, GPIO30 ~ GPIO31
* BL704L: GPIO0 ~ GPIO3, GPIO7 ~ GPIO31
* BL606P : GPIO0 ~ GPIO5, GPIO11 ~ GPIO12, GPIO16 ~ GPIO21, GPIO24 ~ GPIO28, GPIO34 ~ GPIO41
* BL616 : GPIO0 ~ GPIO3, GPIO10 ~ GPIO17, GPIO20 ~ GPIO22, GPIO27 ~ GPIO30
* BL618 : GPIO0 ~ GPIO34
@ -104,6 +105,7 @@
#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PWM1 (8 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_KEYSCAN (13 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
#elif defined(BL616)

14
drivers/lhal/include/bflb_ir.h
View File

@ -11,7 +11,6 @@
* @{
*/
#if !defined(BL616)
/** @defgroup IR_TX_MODE ir tx mode definition
* @{
*/
@ -60,9 +59,6 @@
* @}
*/
#endif
#if !defined(BL702L)
/** @defgroup IR_RX_MODE ir rx mode definition
* @{
*/
@ -96,9 +92,7 @@
/**
* @}
*/
#endif
#if !defined(BL616)
/**
* @brief IR TX configuration structure
*
@ -159,9 +153,7 @@ struct bflb_ir_tx_config_s {
uint8_t modu_width_0;
uint16_t pulse_width_unit;
};
#endif
#if !defined(BL702L)
/**
* @brief IR RX configuration structure
*
@ -182,13 +174,11 @@ struct bflb_ir_rx_config_s {
uint16_t end_threshold;
uint16_t fifo_threshold;
};
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(BL616)
/**
* @brief Initialize ir tx.
*
@ -271,9 +261,7 @@ uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev);
*/
void bflb_ir_txfifo_clear(struct bflb_device_s *dev);
#endif
#endif
#if !defined(BL702L)
/**
* @brief Initialize ir rx.
*
@ -348,8 +336,6 @@ uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev);
*/
void bflb_ir_rxint_clear(struct bflb_device_s *dev);
#endif
/**
* @brief Control ir feature.
*

6
drivers/lhal/include/bflb_pwm_v1.h
View File

@ -19,7 +19,11 @@
#define PWM_CH2 2
#define PWM_CH3 3
#define PWM_CH4 4
#if defined(BL702L)
#define PWM_V1_CH_MAX 1
#else
#define PWM_V1_CH_MAX 5
#endif
/**
* @}
*/
@ -186,4 +190,4 @@ int bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd,
* @}
*/
#endif
#endif

31
drivers/lhal/include/bflb_sdio2.h
View File

@ -47,12 +47,23 @@
#define SDIO2_BYTE_MOD_SIZE_MAX (512)
#define SDIO2_MAX_PORT_NUM 16
/* error callback resaon */
#define SDIO2_ERROR_CRC (1)
#define SDIO2_ERROR_ABORT (2)
/* card to host interrupt event */
#define SDIO2_HOST_INT_EVENT_DNLD_RDY (1 << 0)
#define SDIO2_HOST_INT_EVENT_UPLD_RDY (1 << 1)
#define SDIO2_HOST_INT_EVENT_CIS_RDY (1 << 2)
#define SDIO2_HOST_INT_EVENT_IO_RDY (1 << 3)
#if (SDIO2_MAX_PORT_NUM & (SDIO2_MAX_PORT_NUM - 1) != 0)
#error "sdio2 port num error, must be 2^n"
#else
#define SDIO2_MAX_PORT_MASK (SDIO2_MAX_PORT_NUM - 1)
#endif
/* trans desc */
typedef struct
{
uint16_t buff_len;
@ -61,6 +72,17 @@ typedef struct
void *user_arg;
} bflb_sdio2_trans_desc_t;
/* trans callback */
typedef void (*bflb_sdio2_trans_irq_callback_t)(void *arg, bflb_sdio2_trans_desc_t *trans_desc);
/* error callback */
typedef void (*bflb_sdio2_error_irq_callback_t)(void *arg, uint32_t err_code);
#if defined(BL616)
/* reset callback */
typedef void (*bflb_sdio2_reset_irq_callback_t)(void *arg,
bflb_sdio2_trans_desc_t *upld_rest_desc, uint32_t upld_rest_desc_num,
bflb_sdio2_trans_desc_t *dnld_rest_desc, uint32_t dnld_rest_desc_num);
#endif
#ifdef __cplusplus
extern "C" {
#endif
@ -85,9 +107,12 @@ int bflb_sdio2_upld_get_waiting(struct bflb_device_s *dev);
int bflb_sdio2_upld_get_available(struct bflb_device_s *dev);
/* isr callback attach */
int bflb_sdio2_dnld_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg, bflb_sdio2_trans_desc_t *trans_desc), void *arg);
int bflb_sdio2_upld_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg, bflb_sdio2_trans_desc_t *trans_desc), void *arg);
int bflb_sdio2_error_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg, bflb_sdio2_trans_desc_t *trans_desc), void *arg);
int bflb_sdio2_dnld_irq_attach(struct bflb_device_s *dev, bflb_sdio2_trans_irq_callback_t dnld_irq_callback, void *arg);
int bflb_sdio2_upld_irq_attach(struct bflb_device_s *dev, bflb_sdio2_trans_irq_callback_t upld_irq_callback, void *arg);
int bflb_sdio2_error_irq_attach(struct bflb_device_s *dev, bflb_sdio2_error_irq_callback_t error_irq_callback, void *arg);
#if defined(BL616)
int bflb_sdio2_reset_irq_attach(struct bflb_device_s *dev, bflb_sdio2_reset_irq_callback_t reset_irq_callback, void *arg);
#endif
/* trigger host interrupt event */
int bflb_sdio2_trig_host_int(struct bflb_device_s *dev, uint32_t event);

4
drivers/lhal/include/compiler/compiler_ld.h
View File

@ -52,11 +52,11 @@
#endif
#ifndef ATTR_HBN_RAM_SECTION
#define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code")))
#define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_code." ATTR_UNI_SYMBOL)))
#endif
#ifndef ATTR_HBN_RAM_CONST_SECTION
#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_ram_data")))
#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_data." ATTR_UNI_SYMBOL)))
#endif
#define ATTR_FALLTHROUGH() __attribute__((fallthrough))

2
drivers/lhal/src/bflb_emac.c
View File

@ -255,7 +255,6 @@ int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in
if (flags & EMAC_NOCOPY_PACKET) {
DMADesc->Buffer = (uint32_t)(uintptr_t)data_in;
} else {
// memcpy((void *)(uintptr_t)(DMADesc->Buffer), data_in, len);
arch_memcpy_fast((void *)(uintptr_t)(DMADesc->Buffer), data_in, len);
}
@ -305,7 +304,6 @@ int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out)
#endif
#endif
if (data_out) {
// memcpy(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len);
arch_memcpy_fast(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len);
}

15
drivers/lhal/src/bflb_gpio.c
View File

@ -25,6 +25,15 @@ void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset)
}
#endif
#if defined(BL702L)
/* disable muxed to be xtal32k */
if (pin == GPIO_PIN_30) {
*(volatile uint32_t *)(0x4000F000 + 0x38) &= ~(1 << 25);
} else if (pin == GPIO_PIN_31) {
*(volatile uint32_t *)(0x4000F000 + 0x38) &= ~(1 << 26);
}
#endif
#if defined(BL702) || defined(BL602) || defined(BL702L)
uint32_t regval;
uint8_t real_pin;
@ -191,8 +200,7 @@ void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin)
uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
putreg32(regval | 1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
#elif defined(BL702L)
uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
putreg32(regval | 1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG138_OFFSET + ((pin >> 5) << 2));
#endif
@ -204,8 +212,7 @@ void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin)
uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
putreg32(regval & ~(1 << (pin & 0x1f)), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
#elif defined(BL702L)
uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
putreg32(regval & ~(1 << (pin & 0x1f)), dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG140_OFFSET + ((pin >> 5) << 2));
#endif

4
drivers/lhal/src/bflb_platform_dma.c
View File

@ -6,7 +6,7 @@ struct bflb_platform_dma_env_tag dma_env;
void bflb_platform_dma_init(struct bflb_device_s *dev)
{
memset(dma_env.last_dma, 0, sizeof(dma_env.last_dma));
arch_memset(dma_env.last_dma, 0, sizeof(dma_env.last_dma));
// configure the channel priorities
putreg32(0x0C, dev->reg_base + DMA_ARBITRATION_OFFSET);
@ -92,4 +92,4 @@ void bflb_platform_dma_clear_eot(struct bflb_device_s *dev)
if (channel_idx < 5) {
putreg32(1 << (20 + channel_idx), dev->reg_base + DMA_INT_ACK_OFFSET);
}
}
}

178
drivers/lhal/src/bflb_sdio2.c
View File

@ -37,8 +37,11 @@
#include "bflb_sdio2.h"
#include "hardware/sdio2_reg.h"
// #define SDIO2_DRV_DBG(a, ...) printf(a, ##__VA_ARGS__)
#if 0
#define SDIO2_DRV_DBG(a, ...) printf(a, ##__VA_ARGS__)
#else
#define SDIO2_DRV_DBG(a, ...)
#endif
#ifndef BOOTROM
#define SDIO2_DRV_ERR(a, ...) printf("[Error]:" a, ##__VA_ARGS__)
@ -47,31 +50,43 @@ extern void bflb_bootrom_printf(char *fmt, ...);
#define SDIO2_DRV_ERR(a, ...) bflb_bootrom_printf("[Error]:" a, ##__VA_ARGS__)
#endif
#if (SDIO2_MAX_PORT_NUM & (SDIO2_MAX_PORT_NUM - 1) != 0)
#error "sdio2 port num error, must be 2^n"
#else
#define SDIO2_MAX_PORT_MASK (SDIO2_MAX_PORT_NUM - 1)
#if defined(BL602)
uint32_t sdio2_base[] = { 0x4000d000 };
#elif defined(BL616)
uint32_t sdio2_base[] = { 0x2000d000 };
#endif
struct bflb_sdio2_irq_callback {
void (*handler)(void *arg, bflb_sdio2_trans_desc_t *trans_desc);
void *arg;
};
/* isr */
static void bflb_sdio2_isr(int irq, void *arg);
static void bflb_sdio2_reset_irq(int irq, void *arg);
struct bflb_sdio2_irq_callback sdio2_irq_dnld_callback;
struct bflb_sdio2_irq_callback sdio2_irq_upld_callback;
struct bflb_sdio2_irq_callback sdio2_irq_error_callback;
/* dnld irq callback */
static void *sdio2_dnld_irq_callback_arg;
static bflb_sdio2_trans_irq_callback_t sdio2_dnld_irq_callback;
/* upld irq callback */
static void *sdio2_upld_irq_callback_arg;
static bflb_sdio2_trans_irq_callback_t sdio2_upld_irq_callback;
/* error irq callback */
static void *sdio2_error_irq_callback_arg;
static bflb_sdio2_error_irq_callback_t sdio2_error_irq_callback;
#if defined(BL616)
/* reset irq callback */
static void *sdio2_reset_irq_callback_arg;
static bflb_sdio2_reset_irq_callback_t sdio2_reset_irq_callback;
#endif
/* upld/upld max size */
static volatile uint32_t sdio2_upld_size_max, sdio2_dnld_size_max;
/* dnld ring queue */
static volatile bflb_sdio2_trans_desc_t sdio_dnld_port_table[SDIO2_MAX_PORT_NUM];
static volatile uintptr_t sdio_dnld_port_head, sdio_dnld_port_tail;
/* upld ring queue */
static volatile bflb_sdio2_trans_desc_t sdio_upld_port_table[SDIO2_MAX_PORT_NUM];
static volatile uintptr_t sdio_upld_port_head, sdio_upld_port_tail;
static void bflb_sdio2_isr(int irq, void *arg);
int bflb_sdio2_dnld_port_push(struct bflb_device_s *dev, bflb_sdio2_trans_desc_t *trans_desc)
{
uint32_t reg_base = dev->reg_base;
@ -203,7 +218,7 @@ int bflb_sdio2_init(struct bflb_device_s *dev, uint32_t dnld_size_max)
scratch_reg = (scratch_reg << SDIO2_SCRATCH_MAX_SIZE_SHIFT) | SDIO2_SCRATCH_SLAVE_READY_MASK;
putreg8(scratch_reg, reg_base + SDIO2_SCRATCH_OFFSET);
/* clean bitmap */
/* clean bitmap (write invalid) */
putreg16(0, reg_base + SDIO2_RD_BIT_MAP_OFFSET);
putreg16(0, reg_base + SDIO2_WR_BIT_MAP_OFFSET);
@ -227,6 +242,12 @@ int bflb_sdio2_init(struct bflb_device_s *dev, uint32_t dnld_size_max)
bflb_irq_attach(dev->irq_num, bflb_sdio2_isr, dev);
bflb_irq_enable(dev->irq_num);
#if defined(BL616)
#define BL616_IRQ_SDU_SOFT_RST 19
bflb_irq_attach(BL616_IRQ_SDU_SOFT_RST, bflb_sdio2_reset_irq, dev);
bflb_irq_enable(BL616_IRQ_SDU_SOFT_RST);
#endif
return 0;
}
@ -296,27 +317,40 @@ int bflb_sdio2_get_upld_size_max(struct bflb_device_s *dev)
return sdio2_upld_size_max;
}
int bflb_sdio2_dnld_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg, bflb_sdio2_trans_desc_t *trans_desc), void *arg)
int bflb_sdio2_dnld_irq_attach(struct bflb_device_s *dev, bflb_sdio2_trans_irq_callback_t dnld_irq_callback, void *arg)
{
sdio2_irq_dnld_callback.handler = callback;
sdio2_irq_dnld_callback.arg = arg;
sdio2_dnld_irq_callback_arg = arg;
sdio2_dnld_irq_callback = dnld_irq_callback;
return 0;
}
int bflb_sdio2_upld_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg, bflb_sdio2_trans_desc_t *trans_desc), void *arg)
int bflb_sdio2_upld_irq_attach(struct bflb_device_s *dev, bflb_sdio2_trans_irq_callback_t upld_irq_callback, void *arg)
{
sdio2_irq_upld_callback.handler = callback;
sdio2_irq_upld_callback.arg = arg;
sdio2_upld_irq_callback_arg = arg;
sdio2_upld_irq_callback = upld_irq_callback;
return 0;
}
int bflb_sdio2_error_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg, bflb_sdio2_trans_desc_t *trans_desc), void *arg)
int bflb_sdio2_error_irq_attach(struct bflb_device_s *dev, bflb_sdio2_error_irq_callback_t error_irq_callback, void *arg)
{
sdio2_irq_error_callback.handler = callback;
sdio2_irq_error_callback.arg = arg;
sdio2_error_irq_callback_arg = arg;
sdio2_error_irq_callback = error_irq_callback;
return 0;
}
#if defined(BL616)
int bflb_sdio2_reset_irq_attach(struct bflb_device_s *dev, bflb_sdio2_reset_irq_callback_t reset_irq_callback, void *arg)
{
sdio2_reset_irq_callback_arg = arg;
sdio2_reset_irq_callback = reset_irq_callback;
return 0;
}
#endif
int bflb_sdio2_trig_host_int(struct bflb_device_s *dev, uint32_t event)
{
uint32_t reg_base = dev->reg_base;
@ -365,8 +399,8 @@ static void bflb_sdio2_isr(int irq, void *arg)
sdio_upld_port_head += 1;
/* upld done, isr callback */
if (sdio2_irq_upld_callback.handler != NULL) {
sdio2_irq_upld_callback.handler(sdio2_irq_upld_callback.arg, &upld_trans_desc);
if (sdio2_upld_irq_callback != NULL) {
sdio2_upld_irq_callback(sdio2_upld_irq_callback_arg, &upld_trans_desc);
}
}
}
@ -399,8 +433,8 @@ static void bflb_sdio2_isr(int irq, void *arg)
sdio_dnld_port_head += 1;
/* dnld done, isr callback */
if (sdio2_irq_dnld_callback.handler != NULL) {
sdio2_irq_dnld_callback.handler(sdio2_irq_dnld_callback.arg, &trans_desc);
if (sdio2_dnld_irq_callback != NULL) {
sdio2_dnld_irq_callback(sdio2_dnld_irq_callback_arg, &trans_desc);
}
}
}
@ -409,8 +443,8 @@ static void bflb_sdio2_isr(int irq, void *arg)
if (crcerror & SDIO2_CCR_HOST_INT_DnLdCRC_err) {
SDIO2_DRV_ERR("sdio dnld crc error int\r\n");
if (sdio2_irq_error_callback.handler != NULL) {
sdio2_irq_error_callback.handler(sdio2_irq_error_callback.arg, NULL);
if (sdio2_error_irq_callback != NULL) {
sdio2_error_irq_callback(sdio2_error_irq_callback_arg, SDIO2_ERROR_CRC);
}
}
@ -418,5 +452,89 @@ static void bflb_sdio2_isr(int irq, void *arg)
SDIO2_DRV_ERR("sdio abort int\r\n");
putreg8(~SDIO2_CCR_CIC_Abort, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
if (sdio2_error_irq_callback != NULL) {
sdio2_error_irq_callback(sdio2_error_irq_callback_arg, SDIO2_ERROR_ABORT);
}
}
}
#if defined(BL616)
/* sdio2 reset irq (CMD52 write 1<<3 to 0x06) */
static void bflb_sdio2_reset_irq(int irq, void *arg)
{
struct bflb_device_s *dev = (struct bflb_device_s *)arg;
uint32_t reg_base = dev->reg_base;
uint32_t regval = 0;
bflb_irq_clear_pending(BL616_IRQ_SDU_SOFT_RST);
uint32_t dnld_desc_num = 0;
bflb_sdio2_trans_desc_t dnld_desc_s[SDIO2_MAX_PORT_NUM] = { 0 };
uint32_t upld_desc_num = 0;
bflb_sdio2_trans_desc_t upld_desc_s[SDIO2_MAX_PORT_NUM] = { 0 };
/* save dnld desc */
for (; sdio_dnld_port_tail > sdio_dnld_port_head; sdio_dnld_port_head++) {
dnld_desc_s[dnld_desc_num] = sdio_dnld_port_table[sdio_dnld_port_head & SDIO2_MAX_PORT_MASK];
dnld_desc_num += 1;
}
/* save upld desc */
for (; sdio_upld_port_tail > sdio_upld_port_head; sdio_upld_port_head++) {
upld_desc_s[upld_desc_num] = sdio_upld_port_table[sdio_upld_port_head & SDIO2_MAX_PORT_MASK];
upld_desc_num += 1;
}
/* sdio2 reinit */
do {
/* reset port point */
sdio_dnld_port_head = 0;
sdio_dnld_port_tail = 0;
sdio_upld_port_head = 0;
sdio_upld_port_tail = 0;
/* automatic negotiation max len */
uint8_t scratch_reg = sdio2_dnld_size_max / SDIO2_SIZE_CONSULT_MULTIPLE;
scratch_reg = (scratch_reg << SDIO2_SCRATCH_MAX_SIZE_SHIFT) | SDIO2_SCRATCH_SLAVE_READY_MASK;
putreg8(scratch_reg, reg_base + SDIO2_SCRATCH_OFFSET);
/* clean bitmap (write invalid) */
putreg16(0, reg_base + SDIO2_RD_BIT_MAP_OFFSET);
putreg16(0, reg_base + SDIO2_WR_BIT_MAP_OFFSET);
/* toggle SDIO_CCR_CIC_DnLdOvr on WL_SDIO_CCR_CARD_INT_CAUSE */
putreg8(SDIO2_CCR_CIC_DnLdOvr, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
putreg8(0, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
if (1) {
/* multiport */
regval = getreg32(reg_base + SDIO2_CONFIG2_OFFSET);
putreg32(regval | SDIO2_CONFIG2_MSK, reg_base + SDIO2_CONFIG2_OFFSET);
regval = getreg8(reg_base + SDIO2_CONFIG_OFFSET);
putreg8(regval | 0x00000010, reg_base + SDIO2_CONFIG_OFFSET);
}
/* unmask the interrupts */
putreg8(SDIO2_CCR_CIM_MASK, reg_base + SDIO2_CARD_INT_MASK_OFFSET);
/* select interrupt reset mode */
putreg8(0, reg_base + SDIO2_CARD_INT_MODE_OFFSET);
} while (0);
/* reset irq callback */
if (sdio2_reset_irq_callback != NULL) {
sdio2_reset_irq_callback(sdio2_reset_irq_callback_arg,
upld_desc_s, upld_desc_num,
dnld_desc_s, dnld_desc_num);
}
/* automatic negotiation max len (slave ready) */
uint8_t scratch_reg = sdio2_dnld_size_max / SDIO2_SIZE_CONSULT_MULTIPLE;
scratch_reg = (scratch_reg << SDIO2_SCRATCH_MAX_SIZE_SHIFT) | SDIO2_SCRATCH_SLAVE_READY_MASK;
putreg8(scratch_reg, reg_base + SDIO2_SCRATCH_OFFSET);
}
#endif

4
drivers/soc/bl616/std/CMakeLists.txt
View File

@ -17,6 +17,7 @@ sdk_library_add_sources(src/bl616_glb.c)
sdk_library_add_sources(src/bl616_hbn.c)
sdk_library_add_sources(src/bl616_l1c.c)
sdk_library_add_sources(src/bl616_pds.c)
sdk_library_add_sources(src/bl616_aon.c)
endif()
sdk_library_add_sources(src/bl616_clock.c)
sdk_library_add_sources(src/bl616_common.c)
@ -25,7 +26,6 @@ sdk_library_add_sources(src/bl616_sdh.c)
sdk_library_add_sources(src/bl616_tzc_sec.c)
sdk_library_add_sources(src/bl616_psram.c)
sdk_library_add_sources(src/bl616_pm.c)
sdk_library_add_sources(src/bl616_aon.c)
if(CONFIG_RF)
sdk_library_add_sources(src/bl616_mfg_efuse.c)
@ -48,4 +48,4 @@ sdk_add_compile_definitions(-DARCH_RISCV -DBFLB_USE_HAL_DRIVER)
sdk_add_compile_options(-march=${MARCH} -mabi=${MABI} -mtune=${MCPU})
sdk_add_link_options(-march=${MARCH} -mabi=${MABI} -mtune=${MCPU})
sdk_add_compile_definitions(-DCONFIG_IRQ_NUM=80)
sdk_add_compile_definitions(-DCONFIG_IRQ_NUM=80)

34
drivers/soc/bl616/std/src/bl616_aon.c
View File

@ -104,7 +104,6 @@
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
{
uint32_t tmpVal = 0;
@ -118,7 +117,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Power off Main band gap
@ -128,7 +126,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
{
uint32_t tmpVal = 0;
@ -140,7 +137,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Power on XTAL
@ -150,7 +146,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
{
uint32_t tmpVal = 0;
@ -174,7 +169,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Set XTAL cap code
@ -185,7 +179,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
{
uint32_t tmpVal = 0;
@ -199,7 +192,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOu
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Get XTAL cap code
@ -209,7 +201,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOu
* @return Cap code
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
{
uint32_t tmpVal = 0;
@ -218,7 +209,6 @@ uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
}
#endif
/****************************************************************************/ /**
* @brief Power off XTAL
@ -228,7 +218,6 @@ uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
{
uint32_t tmpVal = 0;
@ -240,7 +229,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Power on bandgap system
@ -250,7 +238,6 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
{
uint32_t tmpVal = 0;
@ -264,7 +251,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Power off bandgap system
@ -274,7 +260,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
{
uint32_t tmpVal = 0;
@ -288,7 +273,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Power on LDO15_RF
@ -298,7 +282,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
{
uint32_t tmpVal = 0;
@ -312,7 +295,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Power off LDO15_RF
@ -322,7 +304,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
{
uint32_t tmpVal = 0;
@ -334,7 +315,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief LDO15_RF Output Float
@ -415,7 +395,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Output_LDO15_RF_Ctrl_by_Pd(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
{
uint32_t tmpVal = 0;
@ -429,7 +408,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief power off source follow regular
@ -439,7 +417,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
{
uint32_t tmpVal = 0;
@ -451,7 +428,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief power on mic bias
@ -578,7 +554,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcDis(void)
{
Efuse_Ana_DcdcDis_Type trim;
@ -596,7 +571,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcDis(void)
return ERROR;
}
#endif
/****************************************************************************/ /**
* @brief trim DCDC vout sel
@ -606,7 +580,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcDis(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutSel(void)
{
Efuse_Ana_DcdcVoutSel_Type trim;
@ -624,7 +597,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutSel(void)
return ERROR;
}
#endif
/****************************************************************************/ /**
* @brief trim DCDC vout trim
@ -634,7 +606,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutSel(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutTrim(void)
{
Efuse_Ana_DcdcVoutTrim_Type trim;
@ -652,7 +623,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutTrim(void)
return ERROR;
}
#endif
/****************************************************************************/ /**
* @brief trim LDO11SOC vout
@ -662,7 +632,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutTrim(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Trim_Ldo11socVoutTrim(void)
{
Efuse_Ana_Ldo11socVoutTrim_Type trim;
@ -680,7 +649,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_Ldo11socVoutTrim(void)
return ERROR;
}
#endif
/****************************************************************************/ /**
* @brief trim USB20 rcal code
@ -690,7 +658,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_Ldo11socVoutTrim(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
BL_Err_Type ATTR_TCM_SECTION AON_Trim_Usb20RcalCode(void)
{
Efuse_Ana_Usb20RcalCode_Type trim;
@ -708,7 +675,6 @@ BL_Err_Type ATTR_TCM_SECTION AON_Trim_Usb20RcalCode(void)
return ERROR;
}
#endif
/****************************************************************************/ /**
* @brief DCDC18 Pulldown Output to Groud

5
drivers/soc/bl616/std/src/bl616_ef_cfg.c
View File

@ -33,11 +33,10 @@
*
******************************************************************************
*/
#include "bflb_efuse.h"
#include "bl616_ef_cfg.h"
#include "hardware/ef_data_reg.h"
extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
{
.name = "ldo15",
@ -581,4 +580,4 @@ void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
{
bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
}
}

222
drivers/soc/bl616/std/src/bl616_romapi_patch.c
View File

@ -4137,4 +4137,226 @@ BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)
return SUCCESS;
}
/****************************************************************************/ /**
* @brief LDO15_RF Output Float
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Output_Float_LDO15_RF(void)
{
uint32_t tmpVal=0;
/* ldo15rf pulldown select by aon */
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
/* ldo15rf float output */
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief LDO15_RF Pulldown Output to Groud
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Output_Pulldown_LDO15_RF(void)
{
uint32_t tmpVal=0;
/* ldo15rf pulldown select by aon */
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
/* ldo15rf pulldown output to ground */
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief LDO15_RF Output Pulldown Controlled by PD Signal
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Output_LDO15_RF_Ctrl_by_Pd(void)
{
uint32_t tmpVal=0;
/* output ldo15rf pulldown select by pd signal */
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief power on mic bias
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_MicBias(void)
{
uint32_t tmpVal = 0;
/* power on sfreg */
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
arch_delay_us(10);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief power off mic bias
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_MicBias(void)
{
uint32_t tmpVal = 0;
/* power off sfreg */
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Power off the power can be shut down in PDS0
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
{
uint32_t tmpVal = 0;
/* power off sfreg */
tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
/* gating Clock */
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
tmpVal = tmpVal & (~(1 << 6));
tmpVal = tmpVal & (~(1 << 7));
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Power on the power powered down in PDS0
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
arch_delay_us(20);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
arch_delay_us(60);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
arch_delay_us(20);
/* power on wb */
tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
/* ungating Clock */
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
tmpVal = tmpVal | ((1 << 6));
tmpVal = tmpVal | ((1 << 7));
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief DCDC18 Pulldown Output to Groud
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Output_Pulldown_DCDC18(void)
{
uint32_t tmpVal=0;
tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_1);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_DCDC_PULLDOWN_AON );
BL_WR_REG(AON_BASE, AON_DCDC_TOP_1, tmpVal);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief DCDC18 Output Float
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Output_Float_DCDC18(void)
{
uint32_t tmpVal=0;
tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_1);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_DCDC_PULLDOWN_AON );
BL_WR_REG(AON_BASE, AON_DCDC_TOP_1, tmpVal);
return SUCCESS;
}

2
drivers/soc/bl616/std/startup/system_bl616.c
View File

@ -150,8 +150,10 @@ void SystemInit(void)
/* tspend use positive interrupt */
#ifdef CONFIG_IRQ_USE_VECTOR
CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
CLIC->CLICINT[SDU_SOFT_RST_IRQn].ATTR = 0x3;
#else
CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x2;
CLIC->CLICINT[SDU_SOFT_RST_IRQn].ATTR = 0x2;
#endif
csi_dcache_enable();
csi_icache_enable();