mirror of
https://github.com/bouffalolab/bouffalo_sdk.git
synced 2025-05-09 03:11:58 +08:00
[feat][soc] add missing bl808_ipc.c
This commit is contained in:
jzlv
parent
7b1717a616
commit
a8f8e39a8e
@ -22,6 +22,8 @@ sdk_library_add_sources(src/bl808_tzc_sec.c)
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sdk_library_add_sources(src/bl808_psram_uhs.c)
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sdk_library_add_sources(src/bl808_uhs_phy.c)
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sdk_library_add_sources(src/bl808_ipc.c)
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sdk_library_add_sources(port/bl808_clock.c)
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sdk_add_include_directories(
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738
drivers/soc/bl808/std/src/bl808_ipc.c
Normal file
738
drivers/soc/bl808/std/src/bl808_ipc.c
Normal file
@ -0,0 +1,738 @@
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/**
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******************************************************************************
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* @file bl808_ipc.c
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* @version V1.2
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* @date
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* @brief This file is the standard driver c file
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2018 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#include "bl808_ipc.h"
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#include "bflb_core.h"
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/** @addtogroup BL606P_Peripheral_Driver
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* @{
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*/
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/** @addtogroup IPC
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* @{
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*/
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/** @defgroup IPC_Private_Macros
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* @{
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*/
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#define IPC_LP_OFFSET_IN_M0 0
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#define IPC_D0_OFFSET_IN_M0 16
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#define IPC_M0_OFFSET_IN_LP 0
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#define IPC_D0_OFFSET_IN_LP 16
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#define IPC_M0_OFFSET_IN_D0 0
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#define IPC_LP_OFFSET_IN_D0 16
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/*@} end of group IPC_Private_Macros */
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/** @defgroup IPC_Private_Types
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* @{
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*/
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/*@} end of group IPC_Private_Types */
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/** @defgroup IPC_Private_Variables
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* @{
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*/
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ipcIntCallback *m0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };
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ipcIntCallback *lpIpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };
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ipcIntCallback *d0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };
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/*@} end of group IPC_Private_Variables */
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/** @defgroup IPC_Global_Variables
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* @{
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*/
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/*@} end of group IPC_Global_Variables */
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/** @defgroup IPC_Private_Fun_Declaration
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* @{
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*/
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/*@} end of group IPC_Private_Fun_Declaration */
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/** @defgroup IPC_Private_Functions
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* @{
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*/
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/*@} end of group IPC_Private_Functions */
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/** @defgroup IPC_Public_Functions
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* @{
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*/
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#if defined(CPU_M0) || defined(CPU_LP)
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/****************************************************************************/ /**
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* @brief M0 IPC interrupt init
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*
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* @param onLPTriggerCallBack: Callback when LP trigger
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*
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* @param onD0TriggerCallBack: Callback when D0 trigger
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_M0_Init(ipcIntCallback *onLPTriggerCallBack,
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ipcIntCallback *onD0TriggerCallBack)
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{
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m0IpcIntCbfArra[0] = onLPTriggerCallBack;
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m0IpcIntCbfArra[1] = onD0TriggerCallBack;
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IPC_M0_Int_Unmask_By_Word(0xffffffff);
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#ifndef BFLB_USE_HAL_DRIVER
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bflb_irq_attach(IPC_M0_IRQn, IPC_M0_IRQHandler,NULL);
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#endif
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bflb_irq_enable(IPC_M0_IRQn);
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}
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#endif
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/****************************************************************************/ /**
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* @brief M0 unmask IPC interrupt
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*
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* @param src: M0 IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_M0_Int_Unmask(IPC_Int_Src_Type src)
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{
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uint32_t tmpVal = 0;
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/* Check the parameters */
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CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
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tmpVal = (1 << src);
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BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, tmpVal);
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}
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/****************************************************************************/ /**
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* @brief M0 unmask IPC interrupt by word
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*
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* @param src: IPC interrupt source in word,every bit is interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_M0_Int_Unmask_By_Word(uint32_t src)
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{
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BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, src);
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}
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/****************************************************************************/ /**
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* @brief M0 get IPC interrupt raw status
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*
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* @param None
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*
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* @return IPC interrupt raw status
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*
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*******************************************************************************/
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uint32_t IPC_M0_Get_Int_Raw_Status(void)
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{
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return BL_RD_REG(IPC0_BASE, IPC_CPU0_IPC_IRSRR);
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}
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/****************************************************************************/ /**
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* @brief M0 clear IPC interrupt
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*
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* @param src: M0 IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_M0_Clear_Int(IPC_Int_Src_Type src)
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{
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uint32_t tmpVal = 0;
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/* Check the parameters */
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CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
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tmpVal = (1 << src);
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BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, tmpVal);
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}
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/****************************************************************************/ /**
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* @brief M0 clear IPC interrupt by word
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*
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* @param src: IPC interrupt source in word,every bit is interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_M0_Clear_Int_By_Word(uint32_t src)
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{
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BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, src);
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}
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/****************************************************************************/ /**
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* @brief CPUx trigger IPC interrupt to M0
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*
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* @param src: IPC interrupt source
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*
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* @param cpuxOffset: CPU interrupt offset
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_CPUx_Trigger_M0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)
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{
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uint32_t tmpVal = 0;
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/* Check the parameters */
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CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));
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tmpVal = (1 << (src + cpuxOffset));
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BL_WR_REG(IPC0_BASE, IPC_CPU1_IPC_ISWR, tmpVal);
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}
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/****************************************************************************/ /**
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* @brief LP trigger IPC interrupt to M0
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*
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* @param src: LP IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_LP_Trigger_M0(IPC_Grp_Int_Src_Type src)
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{
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IPC_CPUx_Trigger_M0(src, IPC_LP_OFFSET_IN_M0);
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}
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/****************************************************************************/ /**
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* @brief D0 trigger IPC interrupt to M0
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*
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* @param src: D0 IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_D0_Trigger_M0(IPC_Grp_Int_Src_Type src)
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{
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IPC_CPUx_Trigger_M0(src, IPC_D0_OFFSET_IN_M0);
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}
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#if defined(CPU_M0) || defined(CPU_LP)
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/****************************************************************************/ /**
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* @brief LP IPC interrupt init
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*
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* @param onM0TriggerCallBack: Callback when M0 trigger
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*
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* @param onD0TriggerCallBack: Callback when D0 trigger
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_LP_Init(ipcIntCallback *onM0TriggerCallBack,
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ipcIntCallback *onD0TriggerCallBack)
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{
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lpIpcIntCbfArra[0] = onM0TriggerCallBack;
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lpIpcIntCbfArra[1] = onD0TriggerCallBack;
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IPC_LP_Int_Unmask_By_Word(0xffffffff);
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#ifndef BFLB_USE_HAL_DRIVER
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bflb_irq_attach(IPC_LP_IRQn, IPC_LP_IRQHandler,NULL);
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#endif
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bflb_irq_enable(IPC_LP_IRQn);
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}
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#endif
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/****************************************************************************/ /**
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* @brief LP unmask IPC interrupt
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*
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* @param src: LP IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_LP_Int_Unmask(IPC_Int_Src_Type src)
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{
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uint32_t tmpVal = 0;
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/* Check the parameters */
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CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
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tmpVal = (1 << src);
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BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, tmpVal);
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}
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/****************************************************************************/ /**
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* @brief LP unmask IPC interrupt by word
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*
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* @param src: IPC interrupt source in word,every bit is interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_LP_Int_Unmask_By_Word(uint32_t src)
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{
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BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, src);
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}
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/****************************************************************************/ /**
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* @brief LP get IPC interrupt raw status
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*
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* @param None
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*
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* @return IPC interrupt raw status
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*
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*******************************************************************************/
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uint32_t IPC_LP_Get_Int_Raw_Status(void)
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{
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return BL_RD_REG(IPC1_BASE, IPC_CPU0_IPC_IRSRR);
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}
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/****************************************************************************/ /**
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* @brief LP clear IPC interrupt
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*
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* @param src: LP IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_LP_Clear_Int(IPC_Int_Src_Type src)
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{
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uint32_t tmpVal = 0;
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/* Check the parameters */
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CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
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tmpVal = (1 << src);
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BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, tmpVal);
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}
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/****************************************************************************/ /**
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* @brief LP clear IPC interrupt by word
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*
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* @param src: IPC interrupt source in word,every bit is interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_LP_Clear_Int_By_Word(uint32_t src)
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{
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BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, src);
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}
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/****************************************************************************/ /**
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* @brief CPUx trigger IPC interrupt to LP
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*
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* @param src: IPC interrupt source
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*
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* @param cpuxOffset: CPU interrupt offset
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_CPUx_Trigger_LP(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)
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{
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uint32_t tmpVal = 0;
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/* Check the parameters */
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CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));
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tmpVal = (1 << (src + cpuxOffset));
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BL_WR_REG(IPC1_BASE, IPC_CPU1_IPC_ISWR, tmpVal);
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}
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/****************************************************************************/ /**
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* @brief M0 trigger IPC interrupt to LP
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*
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* @param src: M0 IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_M0_Trigger_LP(IPC_Grp_Int_Src_Type src)
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{
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IPC_CPUx_Trigger_LP(src, IPC_M0_OFFSET_IN_LP);
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}
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/****************************************************************************/ /**
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* @brief D0 trigger IPC interrupt to LP
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*
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* @param src: D0 IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_D0_Trigger_LP(IPC_Grp_Int_Src_Type src)
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{
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IPC_CPUx_Trigger_LP(src, IPC_D0_OFFSET_IN_LP);
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}
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#if defined(CPU_D0) || defined(CPU_D1)
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/****************************************************************************/ /**
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* @brief D0 IPC interrupt init
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*
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* @param onM0TriggerCallBack: Callback when M0 trigger
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*
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* @param onLPTriggerCallBack: Callback when LP trigger
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_D0_Init(ipcIntCallback *onM0TriggerCallBack,
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ipcIntCallback *onLPTriggerCallBack)
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{
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d0IpcIntCbfArra[0] = onM0TriggerCallBack;
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d0IpcIntCbfArra[1] = onLPTriggerCallBack;
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IPC_D0_Int_Unmask_By_Word(0xffffffff);
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#ifndef BFLB_USE_HAL_DRIVER
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bflb_irq_attach(IPC_D0_IRQn, IPC_D0_IRQHandler,NULL);
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#endif
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bflb_irq_enable(IPC_D0_IRQn);
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}
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#endif
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/****************************************************************************/ /**
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* @brief D0 unmask IPC interrupt
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*
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* @param src: D0 IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_D0_Int_Unmask(IPC_Int_Src_Type src)
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{
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uint32_t tmpVal = 0;
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/* Check the parameters */
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CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
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tmpVal = (1 << src);
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BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, tmpVal);
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}
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/****************************************************************************/ /**
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* @brief D0 unmask IPC interrupt by word
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*
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* @param src: D0 IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_D0_Int_Unmask_By_Word(uint32_t src)
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{
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BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, src);
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}
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/****************************************************************************/ /**
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* @brief D0 get IPC interrupt raw status
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*
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* @param None
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*
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* @return IPC interrupt raw status
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*
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*******************************************************************************/
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uint32_t IPC_D0_Get_Int_Raw_Status(void)
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{
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return BL_RD_REG(IPC2_BASE, IPC_CPU0_IPC_IRSRR);
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}
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/****************************************************************************/ /**
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* @brief D0 clear IPC interrupt
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*
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* @param src: D0 IPC interrupt source
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*
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* @return None
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*
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*******************************************************************************/
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void IPC_D0_Clear_Int(IPC_Int_Src_Type src)
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{
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uint32_t tmpVal = 0;
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/* Check the parameters */
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CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
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tmpVal = (1 << src);
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|
||||
BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, tmpVal);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief D0 clear IPC interrupt by word
|
||||
*
|
||||
* @param src: IPC interrupt source in word,every bit is interrupt source
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_D0_Clear_Int_By_Word(uint32_t src)
|
||||
{
|
||||
BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, src);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief CPUx trigger IPC interrupt to D0
|
||||
*
|
||||
* @param src: IPC interrupt source
|
||||
*
|
||||
* @param cpuxOffset: CPU interrupt offset
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_CPUx_Trigger_D0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));
|
||||
|
||||
tmpVal = (1 << (src + cpuxOffset));
|
||||
|
||||
BL_WR_REG(IPC2_BASE, IPC_CPU1_IPC_ISWR, tmpVal);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief M0 trigger IPC interrupt to D0
|
||||
*
|
||||
* @param src: M0 IPC interrupt source
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_M0_Trigger_D0(IPC_Grp_Int_Src_Type src)
|
||||
{
|
||||
IPC_CPUx_Trigger_D0(src, IPC_M0_OFFSET_IN_D0);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief LP trigger IPC interrupt to D0
|
||||
*
|
||||
* @param src: LP IPC interrupt source
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_LP_Trigger_D0(IPC_Grp_Int_Src_Type src)
|
||||
{
|
||||
IPC_CPUx_Trigger_D0(src, IPC_LP_OFFSET_IN_D0);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief M0 trigger IPC interrupt to CPUx
|
||||
*
|
||||
* @param tgtCPU: Target CPU
|
||||
*
|
||||
* @param src: IPC interrupt source
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_M0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)
|
||||
{
|
||||
switch (tgtCPU) {
|
||||
case GLB_CORE_ID_LP:
|
||||
IPC_M0_Trigger_LP(src);
|
||||
break;
|
||||
case GLB_CORE_ID_D0:
|
||||
IPC_M0_Trigger_D0(src);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief LP trigger IPC interrupt to CPUx
|
||||
*
|
||||
* @param tgtCPU: Target CPU
|
||||
*
|
||||
* @param src: IPC interrupt source
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_LP_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)
|
||||
{
|
||||
switch (tgtCPU) {
|
||||
case GLB_CORE_ID_M0:
|
||||
IPC_LP_Trigger_M0(src);
|
||||
break;
|
||||
case GLB_CORE_ID_D0:
|
||||
IPC_LP_Trigger_D0(src);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief D0 trigger IPC interrupt to CPUx
|
||||
*
|
||||
* @param tgtCPU: Target CPU
|
||||
*
|
||||
* @param src: IPC interrupt source
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_D0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)
|
||||
{
|
||||
switch (tgtCPU) {
|
||||
case GLB_CORE_ID_M0:
|
||||
IPC_D0_Trigger_M0(src);
|
||||
break;
|
||||
case GLB_CORE_ID_LP:
|
||||
IPC_D0_Trigger_LP(src);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief D0 trigger IPC interrupt to D1
|
||||
*
|
||||
* @param src: D0 IPC interrupt source
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_Trigger_Target_CPU(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)
|
||||
{
|
||||
GLB_CORE_ID_Type localCPU = GLB_Get_Core_Type();
|
||||
|
||||
switch (localCPU) {
|
||||
case GLB_CORE_ID_M0:
|
||||
IPC_M0_Trigger_CPUx(tgtCPU, src);
|
||||
break;
|
||||
case GLB_CORE_ID_LP:
|
||||
IPC_LP_Trigger_CPUx(tgtCPU, src);
|
||||
break;
|
||||
case GLB_CORE_ID_D0:
|
||||
IPC_D0_Trigger_CPUx(tgtCPU, src);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief D0 trigger IPC interrupt to D1
|
||||
*
|
||||
* @param src: D0 IPC interrupt source
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void IPC_Common_Interrupt_Handler(uint32_t irqStatus, ipcIntCallback *callBack[GLB_CORE_ID_MAX - 1])
|
||||
{
|
||||
uint32_t tmp;
|
||||
uint32_t grp = 0;
|
||||
|
||||
for (grp = 0; grp < GLB_CORE_ID_MAX - 1; grp++) {
|
||||
tmp = (irqStatus >> (16 * grp)) & 0xffff;
|
||||
if (tmp != 0) {
|
||||
if (callBack[grp] != NULL) {
|
||||
callBack[grp](tmp);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief M0 IPC IRQ handler
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
void IPC_M0_IRQHandler(void)
|
||||
{
|
||||
uint32_t irqStatus;
|
||||
irqStatus = IPC_M0_Get_Int_Raw_Status();
|
||||
IPC_Common_Interrupt_Handler(irqStatus, m0IpcIntCbfArra);
|
||||
IPC_M0_Clear_Int_By_Word(irqStatus);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief LP IPC IRQ handler
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
void IPC_LP_IRQHandler(void)
|
||||
{
|
||||
uint32_t irqStatus;
|
||||
irqStatus = IPC_LP_Get_Int_Raw_Status();
|
||||
IPC_Common_Interrupt_Handler(irqStatus, lpIpcIntCbfArra);
|
||||
IPC_LP_Clear_Int_By_Word(irqStatus);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief D0 IPC IRQ handler
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
void IPC_D0_IRQHandler(void)
|
||||
{
|
||||
uint32_t irqStatus;
|
||||
irqStatus = IPC_D0_Get_Int_Raw_Status();
|
||||
IPC_Common_Interrupt_Handler(irqStatus, d0IpcIntCbfArra);
|
||||
IPC_D0_Clear_Int_By_Word(irqStatus);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@} end of group IPC_Public_Functions */
|
||||
|
||||
/*@} end of group IPC */
|
||||
|
||||
/*@} end of group BL606P_Peripheral_Driver */
|
||||
Loading…
x
Reference in New Issue
Block a user