From 0cdff9dbf1f1a3fd2bc86e7834ae66af9719c9d1 Mon Sep 17 00:00:00 2001 From: Dong Heng Date: Mon, 25 Nov 2019 17:05:14 +0800 Subject: [PATCH] fix(esp8266): fix that WDEV time is larger than normal --- components/esp8266/include/esp8266/eagle_soc.h | 2 ++ components/esp8266/source/esp_sleep.c | 14 +++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/components/esp8266/include/esp8266/eagle_soc.h b/components/esp8266/include/esp8266/eagle_soc.h index b7999fe1..abb561c9 100644 --- a/components/esp8266/include/esp8266/eagle_soc.h +++ b/components/esp8266/include/esp8266/eagle_soc.h @@ -143,6 +143,8 @@ #define INT_ENA_WDEV 0x3ff20c18 #define WDEV_TSF0_REACH_INT (BIT(27)) +#define WDEV_COUNT_REG (0x3ff20c00) + //Watch dog reg {{ #define PERIPHS_WDT_BASEADDR 0x60000900 diff --git a/components/esp8266/source/esp_sleep.c b/components/esp8266/source/esp_sleep.c index bd4447cb..0ad58c8a 100644 --- a/components/esp8266/source/esp_sleep.c +++ b/components/esp8266/source/esp_sleep.c @@ -49,6 +49,8 @@ typedef struct pm_soc_clk { uint32_t frc2_enable; uint32_t frc2_cnt; + + uint32_t wdev_cnt; } pm_soc_clk_t; static uint16_t s_lock_cnt = 1; @@ -79,6 +81,8 @@ static inline void save_soc_clk(pm_soc_clk_t *clk) clk->frc2_enable = REG_READ(FRC2_CTL) & FRC2_CNTL_ENABLE; if (clk->frc2_enable) clk->frc2_cnt = REG_READ(FRC2_COUNT); + + clk->wdev_cnt = REG_READ(WDEV_COUNT_REG); } static inline uint32_t min_sleep_us(pm_soc_clk_t *clk) @@ -114,7 +118,15 @@ static inline void update_soc_clk(pm_soc_clk_t *clk, uint32_t us) REG_WRITE(FRC2_LOAD, frc2_cnt); } - WdevTimOffSet += us; + uint32_t wdev_us; + uint32_t wdev_cnt = REG_READ(WDEV_COUNT_REG); + + if (clk->wdev_cnt < wdev_cnt) + wdev_us = us - (wdev_cnt - clk->wdev_cnt); + else + wdev_us = us - (UINT32_MAX - clk->wdev_cnt + wdev_cnt); + + WdevTimOffSet += wdev_us; } static int cpu_is_wait_mode(void)