mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-10-22 08:22:23 +08:00

1. Add libssc.a, simple serial console lib. 2. Add libspiffs.a, SPI file system. 3. Add libwps.a to support WPS. 4. Add libespconn.a, Espressif connection lib. 5. Add libespnow.a to support Espressif ESP-NOW. 6. Add libmesh.a, Espressif mesh. 7. Add libnopoll.a, websocket. 8. Add make_lib.sh in "third_party" folder. 9. Add modem-sleep & light-sleep supported. 10. Update libcirom.a to support float IO. 11. Update gen_misc.sh & gen_misc.bat. 12. Update header files, add comments in doxygen style. 13. Update libsmartconfig.a to version 2.5.2. 14. Update libssl.a. 15. Updates driver (PWM/UART/GPIO/SPI/Hardware timer). 16. Update open source codes of third_party. 17. Modify "ld" files, "dram0 len" should be 0x18000 in RTOS SDK. 18. Remove header files in extra_include, which are already in compile folder. 19. Other APIs sync from non-OS SDK, more details in documentation "20B-ESP8266__RTOS_SDK_API Reference". 20. Other optimization to make the SDK more stable.
283 lines
9.7 KiB
C
283 lines
9.7 KiB
C
/*
|
|
* Copyright (c) 2015, Cameron Rich
|
|
*
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are met:
|
|
*
|
|
* * Redistributions of source code must retain the above copyright notice,
|
|
* this list of conditions and the following disclaimer.
|
|
* * Redistributions in binary form must reproduce the above copyright notice,
|
|
* this list of conditions and the following disclaimer in the documentation
|
|
* and/or other materials provided with the distribution.
|
|
* * Neither the name of the axTLS project nor the names of its contributors
|
|
* may be used to endorse or promote products derived from this software
|
|
* without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
|
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
|
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
|
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
|
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
//#include <string.h>
|
|
//#include "os_port.h"
|
|
#include "ssl/ssl_os_port.h"
|
|
#include "ssl/ssl_crypto.h"
|
|
//#include "crypto.h"
|
|
#include "lwip/mem.h"
|
|
|
|
#define GET_UINT32(n,b,i) \
|
|
{ \
|
|
(n) = ((uint32_t) (b)[(i) ] << 24) \
|
|
| ((uint32_t) (b)[(i) + 1] << 16) \
|
|
| ((uint32_t) (b)[(i) + 2] << 8) \
|
|
| ((uint32_t) (b)[(i) + 3] ); \
|
|
}
|
|
|
|
#define PUT_UINT32(n,b,i) \
|
|
{ \
|
|
(b)[(i) ] = (uint8_t) ((n) >> 24); \
|
|
(b)[(i) + 1] = (uint8_t) ((n) >> 16); \
|
|
(b)[(i) + 2] = (uint8_t) ((n) >> 8); \
|
|
(b)[(i) + 3] = (uint8_t) ((n) ); \
|
|
}
|
|
|
|
static const uint8_t sha256_padding[64] ICACHE_RODATA_ATTR STORE_ATTR =
|
|
{
|
|
0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
|
};
|
|
|
|
/**
|
|
* Initialize the SHA256 context
|
|
*/
|
|
void ICACHE_FLASH_ATTR SHA256_Init(SHA256_CTX *ctx)
|
|
{
|
|
ctx->total[0] = 0;
|
|
ctx->total[1] = 0;
|
|
|
|
ctx->state[0] = 0x6A09E667;
|
|
ctx->state[1] = 0xBB67AE85;
|
|
ctx->state[2] = 0x3C6EF372;
|
|
ctx->state[3] = 0xA54FF53A;
|
|
ctx->state[4] = 0x510E527F;
|
|
ctx->state[5] = 0x9B05688C;
|
|
ctx->state[6] = 0x1F83D9AB;
|
|
ctx->state[7] = 0x5BE0CD19;
|
|
}
|
|
|
|
static void ICACHE_FLASH_ATTR SHA256_Process(const uint8_t digest[64], SHA256_CTX *ctx)
|
|
{
|
|
uint32_t temp1, temp2, W[64];
|
|
uint32_t A, B, C, D, E, F, G, H;
|
|
|
|
GET_UINT32(W[0], digest, 0);
|
|
GET_UINT32(W[1], digest, 4);
|
|
GET_UINT32(W[2], digest, 8);
|
|
GET_UINT32(W[3], digest, 12);
|
|
GET_UINT32(W[4], digest, 16);
|
|
GET_UINT32(W[5], digest, 20);
|
|
GET_UINT32(W[6], digest, 24);
|
|
GET_UINT32(W[7], digest, 28);
|
|
GET_UINT32(W[8], digest, 32);
|
|
GET_UINT32(W[9], digest, 36);
|
|
GET_UINT32(W[10], digest, 40);
|
|
GET_UINT32(W[11], digest, 44);
|
|
GET_UINT32(W[12], digest, 48);
|
|
GET_UINT32(W[13], digest, 52);
|
|
GET_UINT32(W[14], digest, 56);
|
|
GET_UINT32(W[15], digest, 60);
|
|
|
|
#define SHR(x,n) ((x & 0xFFFFFFFF) >> n)
|
|
#define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))
|
|
|
|
#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3))
|
|
#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10))
|
|
|
|
#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))
|
|
#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))
|
|
|
|
#define F0(x,y,z) ((x & y) | (z & (x | y)))
|
|
#define F1(x,y,z) (z ^ (x & (y ^ z)))
|
|
|
|
#define R(t) \
|
|
( \
|
|
W[t] = S1(W[t - 2]) + W[t - 7] + \
|
|
S0(W[t - 15]) + W[t - 16] \
|
|
)
|
|
|
|
#define P(a,b,c,d,e,f,g,h,x,K) \
|
|
{ \
|
|
temp1 = h + S3(e) + F1(e,f,g) + K + x; \
|
|
temp2 = S2(a) + F0(a,b,c); \
|
|
d += temp1; h = temp1 + temp2; \
|
|
}
|
|
|
|
A = ctx->state[0];
|
|
B = ctx->state[1];
|
|
C = ctx->state[2];
|
|
D = ctx->state[3];
|
|
E = ctx->state[4];
|
|
F = ctx->state[5];
|
|
G = ctx->state[6];
|
|
H = ctx->state[7];
|
|
|
|
P(A, B, C, D, E, F, G, H, W[ 0], 0x428A2F98);
|
|
P(H, A, B, C, D, E, F, G, W[ 1], 0x71374491);
|
|
P(G, H, A, B, C, D, E, F, W[ 2], 0xB5C0FBCF);
|
|
P(F, G, H, A, B, C, D, E, W[ 3], 0xE9B5DBA5);
|
|
P(E, F, G, H, A, B, C, D, W[ 4], 0x3956C25B);
|
|
P(D, E, F, G, H, A, B, C, W[ 5], 0x59F111F1);
|
|
P(C, D, E, F, G, H, A, B, W[ 6], 0x923F82A4);
|
|
P(B, C, D, E, F, G, H, A, W[ 7], 0xAB1C5ED5);
|
|
P(A, B, C, D, E, F, G, H, W[ 8], 0xD807AA98);
|
|
P(H, A, B, C, D, E, F, G, W[ 9], 0x12835B01);
|
|
P(G, H, A, B, C, D, E, F, W[10], 0x243185BE);
|
|
P(F, G, H, A, B, C, D, E, W[11], 0x550C7DC3);
|
|
P(E, F, G, H, A, B, C, D, W[12], 0x72BE5D74);
|
|
P(D, E, F, G, H, A, B, C, W[13], 0x80DEB1FE);
|
|
P(C, D, E, F, G, H, A, B, W[14], 0x9BDC06A7);
|
|
P(B, C, D, E, F, G, H, A, W[15], 0xC19BF174);
|
|
P(A, B, C, D, E, F, G, H, R(16), 0xE49B69C1);
|
|
P(H, A, B, C, D, E, F, G, R(17), 0xEFBE4786);
|
|
P(G, H, A, B, C, D, E, F, R(18), 0x0FC19DC6);
|
|
P(F, G, H, A, B, C, D, E, R(19), 0x240CA1CC);
|
|
P(E, F, G, H, A, B, C, D, R(20), 0x2DE92C6F);
|
|
P(D, E, F, G, H, A, B, C, R(21), 0x4A7484AA);
|
|
P(C, D, E, F, G, H, A, B, R(22), 0x5CB0A9DC);
|
|
P(B, C, D, E, F, G, H, A, R(23), 0x76F988DA);
|
|
P(A, B, C, D, E, F, G, H, R(24), 0x983E5152);
|
|
P(H, A, B, C, D, E, F, G, R(25), 0xA831C66D);
|
|
P(G, H, A, B, C, D, E, F, R(26), 0xB00327C8);
|
|
P(F, G, H, A, B, C, D, E, R(27), 0xBF597FC7);
|
|
P(E, F, G, H, A, B, C, D, R(28), 0xC6E00BF3);
|
|
P(D, E, F, G, H, A, B, C, R(29), 0xD5A79147);
|
|
P(C, D, E, F, G, H, A, B, R(30), 0x06CA6351);
|
|
P(B, C, D, E, F, G, H, A, R(31), 0x14292967);
|
|
P(A, B, C, D, E, F, G, H, R(32), 0x27B70A85);
|
|
P(H, A, B, C, D, E, F, G, R(33), 0x2E1B2138);
|
|
P(G, H, A, B, C, D, E, F, R(34), 0x4D2C6DFC);
|
|
P(F, G, H, A, B, C, D, E, R(35), 0x53380D13);
|
|
P(E, F, G, H, A, B, C, D, R(36), 0x650A7354);
|
|
P(D, E, F, G, H, A, B, C, R(37), 0x766A0ABB);
|
|
P(C, D, E, F, G, H, A, B, R(38), 0x81C2C92E);
|
|
P(B, C, D, E, F, G, H, A, R(39), 0x92722C85);
|
|
P(A, B, C, D, E, F, G, H, R(40), 0xA2BFE8A1);
|
|
P(H, A, B, C, D, E, F, G, R(41), 0xA81A664B);
|
|
P(G, H, A, B, C, D, E, F, R(42), 0xC24B8B70);
|
|
P(F, G, H, A, B, C, D, E, R(43), 0xC76C51A3);
|
|
P(E, F, G, H, A, B, C, D, R(44), 0xD192E819);
|
|
P(D, E, F, G, H, A, B, C, R(45), 0xD6990624);
|
|
P(C, D, E, F, G, H, A, B, R(46), 0xF40E3585);
|
|
P(B, C, D, E, F, G, H, A, R(47), 0x106AA070);
|
|
P(A, B, C, D, E, F, G, H, R(48), 0x19A4C116);
|
|
P(H, A, B, C, D, E, F, G, R(49), 0x1E376C08);
|
|
P(G, H, A, B, C, D, E, F, R(50), 0x2748774C);
|
|
P(F, G, H, A, B, C, D, E, R(51), 0x34B0BCB5);
|
|
P(E, F, G, H, A, B, C, D, R(52), 0x391C0CB3);
|
|
P(D, E, F, G, H, A, B, C, R(53), 0x4ED8AA4A);
|
|
P(C, D, E, F, G, H, A, B, R(54), 0x5B9CCA4F);
|
|
P(B, C, D, E, F, G, H, A, R(55), 0x682E6FF3);
|
|
P(A, B, C, D, E, F, G, H, R(56), 0x748F82EE);
|
|
P(H, A, B, C, D, E, F, G, R(57), 0x78A5636F);
|
|
P(G, H, A, B, C, D, E, F, R(58), 0x84C87814);
|
|
P(F, G, H, A, B, C, D, E, R(59), 0x8CC70208);
|
|
P(E, F, G, H, A, B, C, D, R(60), 0x90BEFFFA);
|
|
P(D, E, F, G, H, A, B, C, R(61), 0xA4506CEB);
|
|
P(C, D, E, F, G, H, A, B, R(62), 0xBEF9A3F7);
|
|
P(B, C, D, E, F, G, H, A, R(63), 0xC67178F2);
|
|
|
|
ctx->state[0] += A;
|
|
ctx->state[1] += B;
|
|
ctx->state[2] += C;
|
|
ctx->state[3] += D;
|
|
ctx->state[4] += E;
|
|
ctx->state[5] += F;
|
|
ctx->state[6] += G;
|
|
ctx->state[7] += H;
|
|
}
|
|
|
|
/**
|
|
* Accepts an array of octets as the next portion of the message.
|
|
*/
|
|
void ICACHE_FLASH_ATTR SHA256_Update(SHA256_CTX *ctx, const uint8_t * msg, int len)
|
|
{
|
|
uint32_t left = ctx->total[0] & 0x3F;
|
|
uint32_t fill = 64 - left;
|
|
|
|
ctx->total[0] += len;
|
|
ctx->total[0] &= 0xFFFFFFFF;
|
|
|
|
if (ctx->total[0] < len)
|
|
ctx->total[1]++;
|
|
|
|
if (left && len >= fill)
|
|
{
|
|
memcpy((void *) (ctx->buffer + left), (void *)msg, fill);
|
|
SHA256_Process(ctx->buffer, ctx);
|
|
len -= fill;
|
|
msg += fill;
|
|
left = 0;
|
|
}
|
|
|
|
while (len >= 64)
|
|
{
|
|
SHA256_Process(msg, ctx);
|
|
len -= 64;
|
|
msg += 64;
|
|
}
|
|
|
|
if (len)
|
|
{
|
|
memcpy((void *) (ctx->buffer + left), (void *) msg, len);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Return the 256-bit message digest into the user's array
|
|
*/
|
|
void ICACHE_FLASH_ATTR SHA256_Final(uint8_t *digest, SHA256_CTX *ctx)
|
|
{
|
|
uint32_t last, padn;
|
|
uint32_t high, low;
|
|
uint8_t msglen[8];
|
|
uint8_t *sha256_padding_ram = malloc(64);
|
|
|
|
memcpy(sha256_padding_ram, sha256_padding, 64);
|
|
|
|
high = (ctx->total[0] >> 29)
|
|
| (ctx->total[1] << 3);
|
|
low = (ctx->total[0] << 3);
|
|
|
|
PUT_UINT32(high, msglen, 0);
|
|
PUT_UINT32(low, msglen, 4);
|
|
|
|
last = ctx->total[0] & 0x3F;
|
|
padn = (last < 56) ? (56 - last) : (120 - last);
|
|
|
|
SHA256_Update(ctx, sha256_padding_ram, padn);
|
|
SHA256_Update(ctx, msglen, 8);
|
|
|
|
PUT_UINT32(ctx->state[0], digest, 0);
|
|
PUT_UINT32(ctx->state[1], digest, 4);
|
|
PUT_UINT32(ctx->state[2], digest, 8);
|
|
PUT_UINT32(ctx->state[3], digest, 12);
|
|
PUT_UINT32(ctx->state[4], digest, 16);
|
|
PUT_UINT32(ctx->state[5], digest, 20);
|
|
PUT_UINT32(ctx->state[6], digest, 24);
|
|
PUT_UINT32(ctx->state[7], digest, 28);
|
|
|
|
free(sha256_padding_ram);
|
|
}
|