mirror of
https://github.com/espressif/ESP8266_RTOS_SDK.git
synced 2025-10-21 23:52:28 +08:00
3ca6af5da6
1. Add libssc.a, simple serial console lib. 2. Add libspiffs.a, SPI file system. 3. Add libwps.a to support WPS. 4. Add libespconn.a, Espressif connection lib. 5. Add libespnow.a to support Espressif ESP-NOW. 6. Add libmesh.a, Espressif mesh. 7. Add libnopoll.a, websocket. 8. Add make_lib.sh in "third_party" folder. 9. Add modem-sleep & light-sleep supported. 10. Update libcirom.a to support float IO. 11. Update gen_misc.sh & gen_misc.bat. 12. Update header files, add comments in doxygen style. 13. Update libsmartconfig.a to version 2.5.2. 14. Update libssl.a. 15. Updates driver (PWM/UART/GPIO/SPI/Hardware timer). 16. Update open source codes of third_party. 17. Modify "ld" files, "dram0 len" should be 0x18000 in RTOS SDK. 18. Remove header files in extra_include, which are already in compile folder. 19. Other APIs sync from non-OS SDK, more details in documentation "20B-ESP8266__RTOS_SDK_API Reference". 20. Other optimization to make the SDK more stable.
229 lines
8.7 KiB
C
229 lines
8.7 KiB
C
/*
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* Copyright (c) 2015, Cameron Rich
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* * Neither the name of the axTLS project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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//#include <string.h>
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//#include "os_port.h"
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#include "ssl/ssl_os_port.h"
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#include "ssl/ssl_crypto.h"
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//#include "crypto.h"
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#include "lwip/mem.h"
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#define SHR64(a, n) ((a) >> (n))
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#define ROR64(a, n) (((a) >> (n)) | ((a) << (64 - (n))))
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#define CH(x, y, z) (((x) & (y)) | (~(x) & (z)))
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#define MAJ(x, y, z) (((x) & (y)) | ((x) & (z)) | ((y) & (z)))
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#define SIGMA1(x) (ROR64(x, 28) ^ ROR64(x, 34) ^ ROR64(x, 39))
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#define SIGMA2(x) (ROR64(x, 14) ^ ROR64(x, 18) ^ ROR64(x, 41))
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#define SIGMA3(x) (ROR64(x, 1) ^ ROR64(x, 8) ^ SHR64(x, 7))
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#define SIGMA4(x) (ROR64(x, 19) ^ ROR64(x, 61) ^ SHR64(x, 6))
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#define MIN(x, y) ((x) < (y) ? x : y)
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static const uint8_t padding[128] ICACHE_RODATA_ATTR STORE_ATTR =
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{
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0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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};
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static const uint64_t k[80] ICACHE_RODATA_ATTR STORE_ATTR =
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{
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0x428A2F98D728AE22ULL, 0x7137449123EF65CDULL, 0xB5C0FBCFEC4D3B2FULL, 0xE9B5DBA58189DBBCULL,
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0x3956C25BF348B538ULL, 0x59F111F1B605D019ULL, 0x923F82A4AF194F9BULL, 0xAB1C5ED5DA6D8118ULL,
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0xD807AA98A3030242ULL, 0x12835B0145706FBEULL, 0x243185BE4EE4B28CULL, 0x550C7DC3D5FFB4E2ULL,
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0x72BE5D74F27B896FULL, 0x80DEB1FE3B1696B1ULL, 0x9BDC06A725C71235ULL, 0xC19BF174CF692694ULL,
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0xE49B69C19EF14AD2ULL, 0xEFBE4786384F25E3ULL, 0x0FC19DC68B8CD5B5ULL, 0x240CA1CC77AC9C65ULL,
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0x2DE92C6F592B0275ULL, 0x4A7484AA6EA6E483ULL, 0x5CB0A9DCBD41FBD4ULL, 0x76F988DA831153B5ULL,
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0x983E5152EE66DFABULL, 0xA831C66D2DB43210ULL, 0xB00327C898FB213FULL, 0xBF597FC7BEEF0EE4ULL,
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0xC6E00BF33DA88FC2ULL, 0xD5A79147930AA725ULL, 0x06CA6351E003826FULL, 0x142929670A0E6E70ULL,
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0x27B70A8546D22FFCULL, 0x2E1B21385C26C926ULL, 0x4D2C6DFC5AC42AEDULL, 0x53380D139D95B3DFULL,
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0x650A73548BAF63DEULL, 0x766A0ABB3C77B2A8ULL, 0x81C2C92E47EDAEE6ULL, 0x92722C851482353BULL,
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0xA2BFE8A14CF10364ULL, 0xA81A664BBC423001ULL, 0xC24B8B70D0F89791ULL, 0xC76C51A30654BE30ULL,
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0xD192E819D6EF5218ULL, 0xD69906245565A910ULL, 0xF40E35855771202AULL, 0x106AA07032BBD1B8ULL,
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0x19A4C116B8D2D0C8ULL, 0x1E376C085141AB53ULL, 0x2748774CDF8EEB99ULL, 0x34B0BCB5E19B48A8ULL,
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0x391C0CB3C5C95A63ULL, 0x4ED8AA4AE3418ACBULL, 0x5B9CCA4F7763E373ULL, 0x682E6FF3D6B2B8A3ULL,
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0x748F82EE5DEFB2FCULL, 0x78A5636F43172F60ULL, 0x84C87814A1F0AB72ULL, 0x8CC702081A6439ECULL,
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0x90BEFFFA23631E28ULL, 0xA4506CEBDE82BDE9ULL, 0xBEF9A3F7B2C67915ULL, 0xC67178F2E372532BULL,
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0xCA273ECEEA26619CULL, 0xD186B8C721C0C207ULL, 0xEADA7DD6CDE0EB1EULL, 0xF57D4F7FEE6ED178ULL,
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0x06F067AA72176FBAULL, 0x0A637DC5A2C898A6ULL, 0x113F9804BEF90DAEULL, 0x1B710B35131C471BULL,
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0x28DB77F523047D84ULL, 0x32CAAB7B40C72493ULL, 0x3C9EBE0A15C9BEBCULL, 0x431D67C49C100D4CULL,
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0x4CC5D4BECB3E42B6ULL, 0x597F299CFC657E2AULL, 0x5FCB6FAB3AD6FAECULL, 0x6C44198C4A475817ULL
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};
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/**
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* Initialize the SHA512 context
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*/
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void ICACHE_FLASH_ATTR SHA512_Init(SHA512_CTX *ctx)
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{
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ctx->h_dig.h[0] = 0x6A09E667F3BCC908ULL;
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ctx->h_dig.h[1] = 0xBB67AE8584CAA73BULL;
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ctx->h_dig.h[2] = 0x3C6EF372FE94F82BULL;
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ctx->h_dig.h[3] = 0xA54FF53A5F1D36F1ULL;
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ctx->h_dig.h[4] = 0x510E527FADE682D1ULL;
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ctx->h_dig.h[5] = 0x9B05688C2B3E6C1FULL;
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ctx->h_dig.h[6] = 0x1F83D9ABFB41BD6BULL;
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ctx->h_dig.h[7] = 0x5BE0CD19137E2179ULL;
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ctx->size = 0;
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ctx->totalSize = 0;
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}
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static void ICACHE_FLASH_ATTR SHA512_Process(SHA512_CTX *ctx)
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{
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int t;
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uint64_t temp1;
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uint64_t temp2;
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// Initialize the 8 working registers
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uint64_t a = ctx->h_dig.h[0];
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uint64_t b = ctx->h_dig.h[1];
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uint64_t c = ctx->h_dig.h[2];
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uint64_t d = ctx->h_dig.h[3];
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uint64_t e = ctx->h_dig.h[4];
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uint64_t f = ctx->h_dig.h[5];
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uint64_t g = ctx->h_dig.h[6];
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uint64_t h = ctx->h_dig.h[7];
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// Process message in 16-word blocks
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uint64_t *w = ctx->w_buf.w;
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// Convert from big-endian byte order to host byte order
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for (t = 0; t < 16; t++)
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w[t] = be64toh(w[t]);
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// Prepare the message schedule
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for (t = 16; t < 80; t++)
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w[t] = SIGMA4(w[t - 2]) + w[t - 7] + SIGMA3(w[t - 15]) + w[t - 16];
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// SHA-512 hash computation
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for (t = 0; t < 80; t++)
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{
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// Calculate T1 and T2
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temp1 = h + SIGMA2(e) + CH(e, f, g) + k[t] + w[t];
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temp2 = SIGMA1(a) + MAJ(a, b, c);
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// Update the working registers
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h = g;
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g = f;
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f = e;
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e = d + temp1;
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d = c;
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c = b;
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b = a;
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a = temp1 + temp2;
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}
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// Update the hash value
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ctx->h_dig.h[0] += a;
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ctx->h_dig.h[1] += b;
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ctx->h_dig.h[2] += c;
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ctx->h_dig.h[3] += d;
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ctx->h_dig.h[4] += e;
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ctx->h_dig.h[5] += f;
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ctx->h_dig.h[6] += g;
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ctx->h_dig.h[7] += h;
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}
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/**
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* Accepts an array of octets as the next portion of the message.
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*/
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void ICACHE_FLASH_ATTR SHA512_Update(SHA512_CTX *ctx, const uint8_t * msg, int len)
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{
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// Process the incoming data
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while (len > 0)
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{
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// The buffer can hold at most 128 bytes
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size_t n = MIN(len, 128 - ctx->size);
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// Copy the data to the buffer
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memcpy(ctx->w_buf.buffer + ctx->size, msg, n);
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// Update the SHA-512 ctx
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ctx->size += n;
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ctx->totalSize += n;
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// Advance the data pointer
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msg = (uint8_t *) msg + n;
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// Remaining bytes to process
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len -= n;
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// Process message in 16-word blocks
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if (ctx->size == 128)
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{
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// Transform the 16-word block
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SHA512_Process(ctx);
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// Empty the buffer
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ctx->size = 0;
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}
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}
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}
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/**
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* Return the 512-bit message digest into the user's array
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*/
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void ICACHE_FLASH_ATTR SHA512_Final(uint8_t *digest, SHA512_CTX *ctx)
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{
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int i;
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size_t paddingSize;
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uint64_t totalSize;
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uint8_t *padding_ram = malloc(128);
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memcpy(padding_ram, padding, 128);
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// Length of the original message (before padding)
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totalSize = ctx->totalSize * 8;
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// Pad the message so that its length is congruent to 112 modulo 128
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paddingSize = (ctx->size < 112) ? (112 - ctx->size) :
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(128 + 112 - ctx->size);
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// Append padding
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SHA512_Update(ctx, padding, paddingSize);
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// Append the length of the original message
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ctx->w_buf.w[14] = 0;
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ctx->w_buf.w[15] = be64toh(totalSize);
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// Calculate the message digest
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SHA512_Process(ctx);
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// Convert from host byte order to big-endian byte order
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for (i = 0; i < 8; i++)
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ctx->h_dig.h[i] = be64toh(ctx->h_dig.h[i]);
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// Copy the resulting digest
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if (digest != NULL)
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memcpy(digest, ctx->h_dig.digest, SHA512_SIZE);
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free(padding_ram);
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}
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