Merge branch 'feat/c5_sdio' into 'master'

sdio: supported on c5 Closes IDF-12655 and IDF-12641 See merge request espressif/esp-idf!38652
2025-05-08 21:16:41 +08:00 · 2025-05-01 11:52:21 +08:00 · 2025-05-01 11:52:21 +08:00 · 67e5e59de3
commit 67e5e59de3
parent a16f621ed2 6e2d52c802
43 changed files with 857 additions and 145 deletions
--- a/components/driver/test_apps/components/esp_serial_slave_link/CMakeLists.txt
+++ b/components/driver/test_apps/components/esp_serial_slave_link/CMakeLists.txt
@ -1,16 +1,10 @@
-set(srcs "essl.c")
-
-if(CONFIG_SOC_GPSPI_SUPPORTED)
-    list(APPEND srcs "essl_spi.c")
-endif()
-
-if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED)
-    list(APPEND srcs "essl_sdio.c" "essl_sdio_defs.c")
-endif()
-
-idf_component_register(
-    SRCS "${srcs}"
-    INCLUDE_DIRS "include"
-    PRIV_INCLUDE_DIRS "." "include/esp_serial_slave_link"
-    REQUIRES sdmmc driver
+idf_component_register(SRCS "essl.c"
+                "essl_sdio.c"
+                "essl_spi.c"
+                "essl_sdio_defs.c"
+            INCLUDE_DIRS "include"
+            REQUIRES "sdmmc"
+                "driver"
+            PRIV_INCLUDE_DIRS "."
+                "include/esp_serial_slave_link"
 )
--- a/components/driver/test_apps/components/test_driver_utils/include/test_dualboard_utils.h
+++ b/components/driver/test_apps/components/test_driver_utils/include/test_dualboard_utils.h
@ -45,9 +45,10 @@ void test_prepare_buffer_pool(size_t pool_size, uint32_t flags);
 *
 * @param offset           A random offset
 * @param size             Buffer size
+ * @param alignment        Alignment
 * @param[out] out_buffer  Out buffer
 */
-void test_get_buffer_from_pool(uint32_t offset, size_t size, void **out_buffer);
+void test_get_buffer_from_pool(uint32_t offset, size_t size, size_t alignment, void **out_buffer);

 /**
 * Destroy the pool
--- a/components/driver/test_apps/components/test_driver_utils/test_dualboard_utils.c
+++ b/components/driver/test_apps/components/test_driver_utils/test_dualboard_utils.c
@ -43,10 +43,10 @@ void test_prepare_buffer_pool(size_t pool_size, uint32_t flags)
    test_fill_random_to_buffer(199, s_pool, pool_size);
 }

-void test_get_buffer_from_pool(uint32_t offset, size_t size, void **out_buffer)
+void test_get_buffer_from_pool(uint32_t offset, size_t size, size_t alignment, void **out_buffer)
 {
    //to make sure the out_buffer is within the pool
-    offset = ((offset % (s_pool_size - size)) + 3) & ~3;
+    offset = ((offset % (s_pool_size - size)) + (alignment - 1)) & ~(alignment - 1);
    // TEST_ASSERT(offset + size < (uint32_t)s_pool + s_pool_size)

    *out_buffer = (void *)(s_pool + offset);
--- a/components/esp_driver_sdio/src/sdio_slave.c
+++ b/components/esp_driver_sdio/src/sdio_slave.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -325,11 +325,11 @@ static inline esp_err_t sdio_slave_hw_init(sdio_slave_config_t *config)

 static void recover_pin(int pin, int sdio_func)
 {
-    uint32_t reg = GPIO_PIN_MUX_REG[pin];
-    assert(reg != UINT32_MAX);
+    gpio_io_config_t io_cfg = {};
+    esp_err_t ret = gpio_get_io_config(pin, &io_cfg);
+    assert(ret == ESP_OK);

-    int func = REG_GET_FIELD(reg, MCU_SEL);
-    if (func == sdio_func) {
+    if (io_cfg.fun_sel == sdio_func) {
        gpio_set_direction(pin, GPIO_MODE_INPUT);
        gpio_func_sel(pin, PIN_FUNC_GPIO);
    }
--- a/components/esp_driver_sdio/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_sdio/test_apps/.build-test-rules.yml
@ -1,7 +1,7 @@
 components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc:
  enable:
-    - if: IDF_TARGET == "esp32"
-      reason: always use ESP32 SDMMC as host
+    - if: IDF_TARGET in ["esp32", "esp32p4"]
+      reason: runners use ESP32 / ESP32P4 SDMMC as host
  depends_components:
    - sdmmc
    - esp_driver_sdmmc
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 |
-| ----------------- | ----- |
+| Supported Targets | ESP32 | ESP32-P4 |
+| ----------------- | ----- | -------- |

 # SDIO Cross Chips Test Apps: SDMMC Host App

--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/Kconfig.projbuild
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/Kconfig.projbuild
@ -0,0 +1,15 @@
+menu "SDIO Slave Test Host Configuration"
+    choice TEST_SDIO_SLAVE_TARGET
+        prompt "SDIO Slave Chip"
+        default TEST_SDIO_SLAVE_TARGET_ESP32
+        help
+            SDIO Slave chip target
+
+        config TEST_SDIO_SLAVE_TARGET_ESP32
+            bool "SDIO Slave ESP32"
+        config TEST_SDIO_SLAVE_TARGET_ESP32C6
+            bool "SDIO Slave ESP32C6"
+        config TEST_SDIO_SLAVE_TARGET_ESP32C5
+            bool "SDIO Slave ESP32C5"
+    endchoice
+endmenu
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -32,6 +32,15 @@ static const char *TAG = "test_sdio_sdhost";
 #define TEST_INT_MASK_ALL             0xff
 #define TEST_REG_ADDR_MAX             60
 #define TEST_TIMEOUT_MAX              UINT32_MAX
+#define TEST_WIDTH                    4
+#if CONFIG_TEST_SDIO_SLAVE_TARGET_ESP32C5
+#define TEST_PIN_CLK                  33
+#define TEST_PIN_CMD                  4
+#define TEST_PIN_D0                   32
+#define TEST_PIN_D1                   23
+#define TEST_PIN_D2                   53
+#define TEST_PIN_D3                   5
+#endif

 typedef struct {
    uint32_t host_flags;
@ -48,6 +57,11 @@ static void s_master_init(test_sdio_param_t *host_param, essl_handle_t *out_hand
 {
    sdmmc_host_t host_config = (sdmmc_host_t)SDMMC_HOST_DEFAULT();
    host_config.flags = host_param->host_flags;
+#if CONFIG_TEST_SDIO_SLAVE_TARGET_ESP32C5
+    //On P4-SDMMC + C5 SDIO test runner environment, hardware delay needs to be considered
+    host_config.input_delay_phase = SDMMC_DELAY_PHASE_2;
+#endif
+
    if (host_config.flags & SDMMC_HOST_FLAG_4BIT) {
        ESP_LOGI(TAG, "Probe using SD 4-bit...");
    } else if (host_config.flags & SDMMC_HOST_FLAG_1BIT) {
@ -59,6 +73,16 @@ static void s_master_init(test_sdio_param_t *host_param, essl_handle_t *out_hand
    //init sdmmc host
    TEST_ESP_OK(sdmmc_host_init());
    sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT();
+#if CONFIG_TEST_SDIO_SLAVE_TARGET_ESP32C5
+    slot_config.width = TEST_WIDTH;
+    slot_config.clk = TEST_PIN_CLK;
+    slot_config.cmd = TEST_PIN_CMD;
+    slot_config.d0 = TEST_PIN_D0;
+    slot_config.d1 = TEST_PIN_D1;
+    slot_config.d2 = TEST_PIN_D2;
+    slot_config.d3 = TEST_PIN_D3;
+#endif
+
    TEST_ESP_OK(sdmmc_host_init_slot(SDMMC_HOST_SLOT_1, &slot_config));

    //host init slave
@ -127,7 +151,6 @@ TEST_CASE("SDIO_SDMMC: test interrupt", "[sdio]")

    //tests all 8 interrupts of the slave, in which int 7 is used to terminate the test on the slave.
    for (int i = 0; i < 8; i ++) {
-        esp_rom_printf("to essl_send_slave_intr\n");
        TEST_ESP_OK(essl_send_slave_intr(handle, BIT(i), TEST_TIMEOUT_MAX));
        //the slave should return interrupt with the same bit in 10 ms
        TEST_ESP_OK(essl_wait_int(handle, 10));
@ -223,8 +246,13 @@ TEST_CASE("SDIO_SDMMC: test reset", "[sdio]")
 /*---------------------------------------------------------------
                SDMMC_SDIO: test fixed addr
 ---------------------------------------------------------------*/
-#include "soc/soc.h"
+#if CONFIG_TEST_SDIO_SLAVE_TARGET_ESP32C5
+#define HOST_SLCHOST_CONF_W0_REG        (0x60018000 + 0x6C)
+#elif DR_REG_SLCHOST_BASE
 #define HOST_SLCHOST_CONF_W0_REG        (DR_REG_SLCHOST_BASE + 0x6C)
+#else
+#define HOST_SLCHOST_CONF_W0_REG        0
+#endif

 TEST_CASE("SDIO_SDMMC: test fixed addr", "[sdio]")
 {
@ -318,7 +346,11 @@ static void test_from_host(bool check_data)
        for (int j = 0; j < TEST_TRANS_NUMS; j++) {
            ESP_LOGD(TAG, "j: %d", j);

-            test_get_buffer_from_pool(j, TEST_RX_BUFFER_SIZE, &tx_buf_ptr);
+            size_t alignment = 4;
+#if CONFIG_IDF_TARGET_ESP32P4
+            alignment = 64;
+#endif
+            test_get_buffer_from_pool(j, TEST_RX_BUFFER_SIZE, alignment, &tx_buf_ptr);
            ESP_LOG_BUFFER_HEX_LEVEL(TAG, tx_buf_ptr, TEST_RX_BUFFER_SIZE, TEST_HEX_LOG_LEVEL);
            TEST_ESP_OK(essl_send_packet(handle, tx_buf_ptr, TEST_RX_BUFFER_SIZE, TEST_TIMEOUT_MAX));
        }
@ -383,8 +415,12 @@ static void test_to_host(bool check_data)

            if (check_data) {
                size_t compared_len = 0;
+                size_t alignment = 4;
+#if CONFIG_IDF_TARGET_ESP32P4
+                alignment = 64;
+#endif
                do {
-                    test_get_buffer_from_pool(offset, TEST_RX_BUFFER_SIZE, &tx_buf_ptr);
+                    test_get_buffer_from_pool(offset, TEST_RX_BUFFER_SIZE, alignment, &tx_buf_ptr);
                    TEST_ASSERT_EQUAL_HEX8_ARRAY(tx_buf_ptr, &host_rx_buffer[compared_len], TEST_RX_BUFFER_SIZE);
                    compared_len += TEST_RX_BUFFER_SIZE;
                    offset += TEST_RX_BUFFER_SIZE;
@ -418,6 +454,11 @@ TEST_CASE("SDIO_SDMMC: test to host", "[sdio]")
    test_to_host(true);
 }

+TEST_CASE("SDIO_SDMMC: test to host (Performance)", "[sdio_speed]")
+{
+    test_to_host(false);
+}
+
 TEST_CASE("SDIO_SDMMC: test sleep retention", "[sdio_retention]")
 {
    essl_handle_t handle = NULL;
@ -431,8 +472,3 @@ TEST_CASE("SDIO_SDMMC: test sleep retention", "[sdio_retention]")
    s_send_finish_test(handle);
    s_master_deinit();
 }
-
-TEST_CASE("SDIO_SDMMC: test to host (Performance)", "[sdio_speed]")
-{
-    test_to_host(false);
-}
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/sdkconfig.ci.esp32p4_esp32c5
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/sdkconfig.ci.esp32p4_esp32c5
@ -0,0 +1 @@
+CONFIG_TEST_SDIO_SLAVE_TARGET_ESP32C5=y
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py
@ -29,8 +29,16 @@ esp32_c6_param = [
    ]
 ]

+esp32p4_c5_param = [
+    [
+        f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}',
+        'esp32p4|esp32c5',
+    ]
+]
+
 esp32_param_default = [pytest.param(*param) for param in parameter_expand(esp32_32_param, ['default|default'])]
 c6_param_default = [pytest.param(*param) for param in parameter_expand(esp32_c6_param, ['default|default'])]
+c5_param_default = [pytest.param(*param) for param in parameter_expand(esp32p4_c5_param, ['esp32p4_esp32c5|default'])]

 c6_param_retention = [pytest.param(*param) for param in parameter_expand(esp32_c6_param, ['default|sleep_retention'])]

@ -74,6 +82,19 @@ def test_sdio_esp32_esp32(dut: Tuple[IdfDut, IdfDut]) -> None:
    test_sdio_flow(dut)


+@pytest.mark.sdio_multidev_p4_c5
+@pytest.mark.parametrize(
+    'count',
+    [
+        2,
+    ],
+    indirect=True,
+)
+@pytest.mark.parametrize('app_path, target, config', c5_param_default, indirect=True)
+def test_sdio_esp32p4_esp32c5(dut: Tuple[IdfDut, IdfDut]) -> None:
+    test_sdio_flow(dut)
+
+
 # From host speed tests
 def test_sdio_speed_frhost_flow(dut: Tuple[IdfDut, IdfDut], expected_4b_speed: int, expected_1b_speed: int) -> None:
    dut[1].expect('Press ENTER to see the list of tests')
@ -120,6 +141,19 @@ def test_sdio_speed_frhost_esp32_esp32(dut: Tuple[IdfDut, IdfDut]) -> None:
    test_sdio_speed_frhost_flow(dut, 12200, 4000)


+@pytest.mark.sdio_multidev_p4_c5
+@pytest.mark.parametrize(
+    'count',
+    [
+        2,
+    ],
+    indirect=True,
+)
+@pytest.mark.parametrize('app_path, target, config', c5_param_default, indirect=True)
+def test_sdio_speed_frhost_esp32p4_esp32c5(dut: Tuple[IdfDut, IdfDut]) -> None:
+    test_sdio_speed_frhost_flow(dut, 10000, 4000)
+
+
 # To host speed tests
 def test_sdio_speed_tohost_flow(dut: Tuple[IdfDut, IdfDut], expected_4b_speed: int, expected_1b_speed: int) -> None:
    dut[1].expect('Press ENTER to see the list of tests')
@ -166,6 +200,19 @@ def test_sdio_speed_tohost_esp32_esp32(dut: Tuple[IdfDut, IdfDut]) -> None:
    test_sdio_speed_tohost_flow(dut, 12200, 4000)


+@pytest.mark.sdio_multidev_p4_c5
+@pytest.mark.parametrize(
+    'count',
+    [
+        2,
+    ],
+    indirect=True,
+)
+@pytest.mark.parametrize('app_path, target, config', c5_param_default, indirect=True)
+def test_sdio_speed_tohost_esp32p4_esp32c5(dut: Tuple[IdfDut, IdfDut]) -> None:
+    test_sdio_speed_tohost_flow(dut, 9000, 4000)
+
+
 # Retention tests
 def test_sdio_retention(dut: Tuple[IdfDut, IdfDut]) -> None:
    dut[1].expect('Press ENTER to see the list of tests')
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/README.md
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C6 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 |
+| ----------------- | ----- | -------- | -------- |

 # SDIO Cross Chips Test Apps: SDIO Slave App

--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/Kconfig.projbuild
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/Kconfig.projbuild
@ -0,0 +1,13 @@
+menu "SDIO Slave Test Slave Configuration"
+    choice TEST_SDIO_HOST_TARGET
+        prompt "SDIO Host Chip"
+        default TEST_SDIO_HOST_TARGET_ESP32
+        help
+            SDIO Host chip target
+
+        config TEST_SDIO_HOST_TARGET_ESP32
+            bool "SDIO Host ESP32"
+        config TEST_SDIO_HOST_TARGET_ESP32P4
+            bool "SDIO Host ESP32P4"
+    endchoice
+endmenu
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -218,7 +218,11 @@ static void test_from_host(bool check_data)
            ESP_LOG_BUFFER_HEX_LEVEL(TAG, buf, TEST_RX_BUFFER_SIZE, TEST_HEX_LOG_LEVEL);

            if (check_data) {
-                test_get_buffer_from_pool(j, TEST_RX_BUFFER_SIZE, &tx_buf_ptr);
+                size_t alignment = 4;
+#if CONFIG_TEST_SDIO_HOST_TARGET_ESP32P4
+                alignment = 64;
+#endif
+                test_get_buffer_from_pool(j, TEST_RX_BUFFER_SIZE, alignment, &tx_buf_ptr);
                ESP_LOG_BUFFER_HEX_LEVEL("Expect data", tx_buf_ptr, TEST_RX_BUFFER_SIZE, TEST_HEX_LOG_LEVEL);
                TEST_ASSERT_EQUAL_HEX8_ARRAY(tx_buf_ptr, buf, rcv_len);
            }
@ -279,7 +283,11 @@ static void test_to_host(void)
                TEST_ASSERT_EQUAL(ESP_ERR_TIMEOUT, err);
            } while (QUEUE_FULL());

-            test_get_buffer_from_pool(offset, TEST_RX_BUFFER_SIZE, &tx_buf_ptr);
+            size_t alignment = 4;
+#if CONFIG_TEST_SDIO_HOST_TARGET_ESP32P4
+            alignment = 64;
+#endif
+            test_get_buffer_from_pool(offset, TEST_RX_BUFFER_SIZE, alignment, &tx_buf_ptr);
            TEST_ESP_OK(sdio_slave_send_queue((uint8_t *)tx_buf_ptr, TEST_RX_BUFFER_SIZE, NULL, portMAX_DELAY));

            s_test_slv_ctx.queued_cnt++;
@ -305,6 +313,11 @@ TEST_CASE("SDIO_Slave: test to host", "[sdio]")
    test_to_host();
 }

+TEST_CASE("SDIO_Slave: test to host (Performance)", "[sdio_speed]")
+{
+    test_to_host();
+}
+
 #if SOC_PAU_SUPPORTED
 #include "esp_private/sleep_sys_periph.h"
 #include "esp_private/sleep_retention.h"
@ -329,8 +342,3 @@ TEST_CASE("SDIO_Slave: test sleep retention", "[sdio_retention]")
    TEST_ASSERT_EQUAL_INT32(true, peripheral_domain_pd_allowed());
 }
 #endif
-
-TEST_CASE("SDIO_Slave: test to host (Performance)", "[sdio_speed]")
-{
-    test_to_host();
-}
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.defaults.esp32c5
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.defaults.esp32c5
@ -0,0 +1 @@
+CONFIG_TEST_SDIO_HOST_TARGET_ESP32P4=y
--- a/components/hal/esp32/include/hal/sdio_slave_ll.h
+++ b/components/hal/esp32/include/hal/sdio_slave_ll.h
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -16,14 +16,15 @@

 #pragma once

+#include <sys/queue.h>
+#include <stdbool.h>
 #include "hal/sdio_slave_types.h"
 #include "hal/misc.h"
-#include "soc/slc_struct.h"
-#include "soc/slc_reg.h"
-#include "soc/host_struct.h"
-#include "soc/host_reg.h"
-#include "soc/hinf_struct.h"
-#include "soc/lldesc.h"
+#include "soc/sdio_slc_struct.h"
+#include "soc/sdio_slc_reg.h"
+#include "soc/sdio_slc_host_struct.h"
+#include "soc/sdio_slc_host_reg.h"
+#include "soc/sdio_hinf_struct.h"
 #include "soc/dport_reg.h"

 #ifdef __cplusplus
--- a/components/hal/esp32c5/include/hal/sdio_slave_ll.h
+++ b/components/hal/esp32c5/include/hal/sdio_slave_ll.h
@ -0,0 +1,538 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+// The LL layer for SDIO slave register operations
+// It's strange but `tx_*` regs for host->slave transfers while `rx_*` regs for slave->host transfers
+// To reduce ambiguity, we call (host->slave, tx) transfers receiving and (slave->host, rx) transfers receiving
+
+#pragma once
+
+#include <sys/queue.h>
+#include <stdbool.h>
+#include "hal/sdio_slave_types.h"
+#include "hal/misc.h"
+#include "soc/sdio_slc_struct.h"
+#include "soc/sdio_slc_reg.h"
+#include "soc/sdio_slc_host_struct.h"
+#include "soc/sdio_slc_host_reg.h"
+#include "soc/sdio_hinf_struct.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// Get address of the only SLC registers
+#define sdio_slave_ll_get_slc(ID)   (&SLC)
+/// Get address of the only HOST registers
+#define sdio_slave_ll_get_host(ID)  (&HOST)
+/// Get address of the only HINF registers
+#define sdio_slave_ll_get_hinf(ID)  (&HINF)
+
+/*
+ *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
+ *
+ * --------------------------------------------------------------
+ * | own | EoF | sub_sof | 1'b0   | length [13:0] | size [13:0] |
+ * --------------------------------------------------------------
+ * |            buf_ptr [31:0]                                  |
+ * --------------------------------------------------------------
+ * |            next_desc_ptr [31:0]                            |
+ * --------------------------------------------------------------
+ */
+
+/* this bitfield is start from the LSB!!! */
+typedef struct sdio_slave_ll_desc_s {
+    volatile uint32_t size  : 14,
+             length: 14,
+             offset: 1, /* starting from bit28, h/w reserved 1bit, s/w use it as offset in buffer */
+             sosf  : 1, /* start of sub-frame */
+             eof   : 1, /* end of frame */
+             owner : 1; /* hw or sw */
+    volatile const uint8_t *buf;       /* point to buffer data */
+    union {
+        volatile uint32_t empty;
+        STAILQ_ENTRY(sdio_slave_ll_desc_s) qe;  /* pointing to the next desc */
+    };
+} sdio_slave_ll_desc_t;
+
+/// Mask of general purpose interrupts sending from the host.
+typedef enum {
+    SDIO_SLAVE_LL_SLVINT_0 = BIT(0),    ///< General purpose interrupt bit 0.
+    SDIO_SLAVE_LL_SLVINT_1 = BIT(1),
+    SDIO_SLAVE_LL_SLVINT_2 = BIT(2),
+    SDIO_SLAVE_LL_SLVINT_3 = BIT(3),
+    SDIO_SLAVE_LL_SLVINT_4 = BIT(4),
+    SDIO_SLAVE_LL_SLVINT_5 = BIT(5),
+    SDIO_SLAVE_LL_SLVINT_6 = BIT(6),
+    SDIO_SLAVE_LL_SLVINT_7 = BIT(7),
+} sdio_slave_ll_slvint_t;
+
+/**
+ * @brief Enable the bus clock for the SDIO slave module
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void sdio_slave_ll_enable_bus_clock(bool enable)
+{
+    PCR.sdio_slave_conf.sdio_slave_clk_en = enable;
+}
+
+/**
+ * @brief Reset the SDIO slave module
+ */
+static inline void sdio_slave_ll_reset_register(void)
+{
+    PCR.sdio_slave_conf.sdio_slave_rst_en = 1;
+    PCR.sdio_slave_conf.sdio_slave_rst_en = 0;
+}
+
+/**
+ * Initialize the hardware.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_init(slc_dev_t *slc)
+{
+    slc->slc_slc0int_ena.val = 0;
+
+    slc->slc_conf0.slc0_rx_auto_wrback = 1;
+    slc->slc_conf0.slc0_token_auto_clr = 0;
+    slc->slc_conf0.slc0_rx_loop_test = 0;
+    slc->slc_conf0.slc0_tx_loop_test = 0;
+
+    slc->slc_conf1.slc0_rx_stitch_en = 0;
+    slc->slc_conf1.slc0_tx_stitch_en = 0;
+    slc->slc_conf1.slc0_len_auto_clr = 0;
+
+    slc->slc_rx_dscr_conf.slc0_token_no_replace = 1;
+}
+
+/**
+ * Set the timing for the communication
+ *
+ * @param host Address of the host registers
+ * @param timing Timing configuration to set
+ */
+static inline void sdio_slave_ll_set_timing(host_dev_t *host, sdio_slave_timing_t timing)
+{
+    switch (timing) {
+    case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
+        host->conf.frc_sdio20 = 0x1f;
+        host->conf.frc_sdio11 = 0;
+        host->conf.frc_pos_samp = 0x1f;
+        host->conf.frc_neg_samp = 0;
+        break;
+    case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
+        host->conf.frc_sdio20 = 0x1f;
+        host->conf.frc_sdio11 = 0;
+        host->conf.frc_pos_samp = 0;
+        host->conf.frc_neg_samp = 0x1f;
+        break;
+    case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
+        host->conf.frc_sdio20 = 0;
+        host->conf.frc_sdio11 = 0x1f;
+        host->conf.frc_pos_samp = 0x1f;
+        host->conf.frc_neg_samp = 0;
+        break;
+    case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
+        host->conf.frc_sdio20 = 0;
+        host->conf.frc_sdio11 = 0x1f;
+        host->conf.frc_pos_samp = 0;
+        host->conf.frc_neg_samp = 0x1f;
+        break;
+    }
+}
+
+/**
+ * Set the CCCR, SDIO and Physical Layer version
+ */
+static inline void sdio_slave_ll_init_version(hinf_dev_t *hinf)
+{
+    hinf->cfg_data1.sdio_ver = 0x232;
+}
+
+/**
+ * Set the HS supported bit to be read by the host.
+ *
+ * @param hinf Address of the hinf registers
+ * @param hs true if supported, otherwise false.
+ */
+static inline void sdio_slave_ll_enable_hs(hinf_dev_t *hinf, bool hs)
+{
+    if (hs) {
+        hinf->cfg_data1.highspeed_enable = 1;
+    } else {
+        hinf->cfg_data1.highspeed_enable = 0;
+    }
+}
+
+/**
+ * Set the IO Ready bit to be read by the host.
+ *
+ * @param hinf Address of the hinf registers
+ * @param ready true if ready, otherwise false.
+ */
+static inline void sdio_slave_ll_set_ioready(hinf_dev_t *hinf, bool ready)
+{
+    hinf->cfg_data1.sdio_ioready1 = (ready ? 1 : 0);   //set IO ready to 1 to stop host from using
+}
+
+/*---------------------------------------------------------------------------
+ *                  Send
+ *--------------------------------------------------------------------------*/
+/**
+ * Reset the sending DMA.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_send_reset(slc_dev_t *slc)
+{
+    //reset to flush previous packets
+    slc->slc_conf0.slc0_rx_rst = 1;
+    slc->slc_conf0.slc0_rx_rst = 0;
+}
+
+/**
+ * Start the sending DMA with the given descriptor.
+ *
+ * @param slc Address of the SLC registers
+ * @param desc Descriptor to send
+ */
+static inline void sdio_slave_ll_send_start(slc_dev_t *slc, const sdio_slave_ll_desc_t *desc)
+{
+    slc->slc_slc0rx_link_addr.slc0_rxlink_addr = (uint32_t)desc;
+    slc->slc_slc0rx_link.slc0_rxlink_start = 1;
+}
+
+/**
+ * Write the PKT_LEN register to be written by the host to a certain value.
+ *
+ * @param slc Address of the SLC registers
+ * @param len Length to write
+ */
+static inline void sdio_slave_ll_send_write_len(slc_dev_t *slc, uint32_t len)
+{
+    slc->slc_slc0_len_conf.val = FIELD_TO_VALUE2(SDIO_SLC0_LEN_WDATA, len) | FIELD_TO_VALUE2(SDIO_SLC0_LEN_WR, 1);
+}
+
+/**
+ * Read the value of PKT_LEN register. The register may keep the same until read
+ * by the host.
+ *
+ * @param host Address of the host registers
+ * @return The value of PKT_LEN register.
+ */
+static inline uint32_t sdio_slave_ll_send_read_len(host_dev_t *host)
+{
+    return host->pkt_len.hostslchost_slc0_len;
+}
+
+/**
+ * Enable the rx_done interrupt. (sending)
+ *
+ * @param slc Address of the SLC registers
+ * @param ena true if enable, otherwise false.
+ */
+static inline void sdio_slave_ll_send_part_done_intr_ena(slc_dev_t *slc, bool ena)
+{
+    slc->slc_slc0int_ena.slc0_rx_done_int_ena = (ena ? 1 : 0);
+}
+
+/**
+ * Clear the rx_done interrupt. (sending)
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_send_part_done_clear(slc_dev_t *slc)
+{
+    slc->slc_slc0int_clr.slc0_rx_done_int_clr = 1;
+}
+
+/**
+ * Check whether the hardware is ready for the SW to use rx_done to invoke
+ * the ISR.
+ *
+ * @param slc Address of the SLC registers
+ * @return true if ready, otherwise false.
+ */
+static inline bool sdio_slave_ll_send_invoker_ready(slc_dev_t *slc)
+{
+    return slc->slc_slc0int_raw.slc0_rx_done_int_raw;
+}
+
+/**
+ * Stop the sending DMA.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_send_stop(slc_dev_t *slc)
+{
+    slc->slc_slc0rx_link.slc0_rxlink_stop = 1;
+}
+
+/**
+ * Enable the sending interrupt (rx_eof).
+ *
+ * @param slc Address of the SLC registers
+ * @param ena true to enable, false to disable
+ */
+static inline void sdio_slave_ll_send_intr_ena(slc_dev_t *slc, bool ena)
+{
+    slc->slc_slc0int_ena.slc0_rx_eof_int_ena = (ena ? 1 : 0);
+}
+
+/**
+ * Clear the sending interrupt (rx_eof).
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_send_intr_clr(slc_dev_t *slc)
+{
+    slc->slc_slc0int_clr.slc0_rx_eof_int_clr = 1;
+}
+
+/**
+ * Check whether the sending is done.
+ *
+ * @param slc Address of the SLC registers
+ * @return true if done, otherwise false
+ */
+static inline bool sdio_slave_ll_send_done(slc_dev_t *slc)
+{
+    return slc->slc_slc0int_st.slc0_rx_eof_int_st != 0;
+}
+
+/**
+ * Clear the host interrupt indicating the slave having packet to be read.
+ *
+ * @param host Address of the host registers
+ */
+static inline void sdio_slave_ll_send_hostint_clr(host_dev_t *host)
+{
+    host->slc0host_int_clr.slc0_rx_new_packet_int_clr = 1;
+}
+
+/*---------------------------------------------------------------------------
+ *                  Receive
+ *--------------------------------------------------------------------------*/
+/**
+ * Enable the receiving interrupt.
+ *
+ * @param slc Address of the SLC registers
+ * @param ena
+ */
+static inline void sdio_slave_ll_recv_intr_ena(slc_dev_t *slc, bool ena)
+{
+    slc->slc_slc0int_ena.slc0_tx_done_int_ena = (ena ? 1 : 0);
+}
+
+/**
+ * Start receiving DMA with the given descriptor.
+ *
+ * @param slc Address of the SLC registers
+ * @param desc Descriptor of the receiving buffer.
+ */
+static inline void sdio_slave_ll_recv_start(slc_dev_t *slc, sdio_slave_ll_desc_t *desc)
+{
+    slc->slc_slc0tx_link_addr.slc0_txlink_addr = (uint32_t)desc;
+    slc->slc_slc0tx_link.slc0_txlink_start = 1;
+}
+
+/**
+ * Increase the receiving buffer counter by 1.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_size_inc(slc_dev_t *slc)
+{
+    // fields wdata and inc_more should be written by the same instruction.
+    slc->slc_slc0token1.val = FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WDATA, 1) | FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_INC_MORE, 1);
+}
+
+/**
+ * Reset the receiving buffer.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_size_reset(slc_dev_t *slc)
+{
+    slc->slc_slc0token1.val = FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WDATA, 0) | FIELD_TO_VALUE2(SDIO_SLC0_TOKEN1_WR, 1);
+}
+
+/**
+ * Check whether there is a receiving finished event.
+ *
+ * @param slc Address of the SLC registers
+ * @return
+ */
+static inline bool sdio_slave_ll_recv_done(slc_dev_t *slc)
+{
+    return slc->slc_slc0int_raw.slc0_tx_done_int_raw != 0;
+}
+
+/**
+ * Clear the receiving finished interrupt.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_done_clear(slc_dev_t *slc)
+{
+    slc->slc_slc0int_clr.slc0_tx_done_int_clr = 1;
+}
+
+/**
+ * Restart the DMA. Call after you modified the next pointer of the tail descriptor to the appended
+ * descriptor.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_restart(slc_dev_t *slc)
+{
+    slc->slc_slc0tx_link.slc0_txlink_restart = 1;
+}
+
+/**
+ * Reset the receiving DMA.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_reset(slc_dev_t *slc)
+{
+    slc->slc_conf0.slc0_tx_rst = 1;
+    slc->slc_conf0.slc0_tx_rst = 0;
+}
+
+/**
+ * Stop the receiving DMA.
+ *
+ * @param slc Address of the SLC registers
+ */
+static inline void sdio_slave_ll_recv_stop(slc_dev_t *slc)
+{
+    slc->slc_slc0tx_link.slc0_txlink_stop = 1;
+}
+
+/*---------------------------------------------------------------------------
+ *                  Host
+ *--------------------------------------------------------------------------*/
+/**
+ * Get the address of the shared general purpose register. Internal.
+ *
+ * @param host Address of the host registers
+ * @param pos Position of the register, 0-63 except 24-27.
+ * @return address of the register.
+ */
+static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t *host, int pos)
+{
+    return (intptr_t) & (host->conf_w0) + pos + (pos > 23 ? 4 : 0) + (pos > 31 ? 12 : 0);
+}
+
+/**
+ * Get the value of the shared general purpose register.
+ *
+ * @param host Address of the host registers
+ * @param pos Position of the register, 0-63, except 24-27.
+ * @return value of the register.
+ */
+static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
+{
+    return *(uint8_t *)sdio_slave_ll_host_get_w_reg(host, pos);
+}
+
+/**
+ * Set the value of the shared general purpose register.
+ *
+ * @param host Address of the host registers
+ * @param pos Position of the register, 0-63, except 24-27.
+ * @param reg Value to set.
+ */
+static inline void sdio_slave_ll_host_set_reg(host_dev_t *host, int pos, uint8_t reg)
+{
+    uint32_t *addr = (uint32_t *)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
+    uint32_t shift = (pos % 4) * 8;
+    *addr &= ~(0xff << shift);
+    *addr |= ((uint32_t)reg << shift);
+}
+
+/**
+ * Get the interrupt enable bits for the host.
+ *
+ * @param host Address of the host registers
+ * @return Enabled interrupts
+ */
+static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t *host)
+{
+    return (sdio_slave_hostint_t)host->slc0host_func1_int_ena.val;
+}
+
+/**
+ * Set the interrupt enable bits for the host.
+ *
+ * @param host Address of the host registers
+ * @param mask Mask of interrupts to enable
+ */
+static inline void sdio_slave_ll_host_set_intena(host_dev_t *host, const sdio_slave_hostint_t *mask)
+{
+    host->slc0host_func1_int_ena.val = (*mask);
+}
+
+/**
+ * Clear the interrupt bits for the host.
+ * @param host Address of the host registers
+ * @param mask Mask of interrupts to clear.
+ */
+static inline void sdio_slave_ll_host_intr_clear(host_dev_t *host, const sdio_slave_hostint_t *mask)
+{
+    host->slc0host_int_clr.val = (*mask);
+}
+
+/**
+ * Send general purpose interrupts to the host.
+ * @param slc Address of the SLC registers
+ * @param mask Mask of interrupts to seend to host
+ */
+static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_hostint_t *mask)
+{
+    //use registers in SLC to trigger, rather than write HOST registers directly
+    //other interrupts than tohost interrupts are not supported yet
+    HAL_FORCE_MODIFY_U32_REG_FIELD(slc->slc_slcintvec_tohost, slc0_tohost_intvec, *mask);
+}
+
+/**
+ * Enable some of the slave interrupts (send from host)
+ *
+ * @param slc Address of the SLC registers
+ * @param mask Mask of interrupts to enable, all those set to 0 will be disabled.
+ */
+static inline void sdio_slave_ll_slvint_set_ena(slc_dev_t *slc, const sdio_slave_ll_slvint_t *mask)
+{
+    //other interrupts are not enabled
+    slc->slc_slc0int_ena.val = (slc->slc_slc0int_ena.val & (~0xff)) | ((*mask) & 0xff);
+}
+
+/**
+ * Fetch the slave interrupts (send from host) and clear them.
+ *
+ * @param slc Address of the SLC registers
+ * @param out_slv_int Output of the slave interrupts fetched and cleared.
+ */
+static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_ll_slvint_t *out_slv_int)
+{
+    sdio_slave_ll_slvint_t slv_int = (sdio_slave_ll_slvint_t)(slc->slc_slc0int_st.val & 0xff);
+    *out_slv_int = slv_int;
+    slc->slc_slc0int_clr.val = slv_int;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/hal/esp32c6/include/hal/sdio_slave_ll.h
+++ b/components/hal/esp32c6/include/hal/sdio_slave_ll.h
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -16,14 +16,15 @@

 #pragma once

+#include <sys/queue.h>
+#include <stdbool.h>
 #include "hal/sdio_slave_types.h"
 #include "hal/misc.h"
-#include "soc/slc_struct.h"
-#include "soc/slc_reg.h"
-#include "soc/host_struct.h"
-#include "soc/host_reg.h"
-#include "soc/hinf_struct.h"
-#include "soc/lldesc.h"
+#include "soc/sdio_slc_struct.h"
+#include "soc/sdio_slc_reg.h"
+#include "soc/sdio_slc_host_struct.h"
+#include "soc/sdio_slc_host_reg.h"
+#include "soc/sdio_hinf_struct.h"
 #include "soc/pcr_struct.h"

 #ifdef __cplusplus
--- a/components/hal/sdio_slave_hal.c
+++ b/components/hal/sdio_slave_hal.c
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -8,10 +8,10 @@

 #include <string.h>
 #include <inttypes.h>
-#include "soc/slc_struct.h"
-#include "soc/hinf_struct.h"
+#include "soc/sdio_slc_struct.h"
+#include "soc/sdio_hinf_struct.h"
 #include "hal/sdio_slave_types.h"
-#include "soc/host_struct.h"
+#include "soc/sdio_slc_host_struct.h"
 #include "hal/sdio_slave_hal.h"
 #include "hal/assert.h"
 #include "hal/log.h"
--- a/components/soc/esp32/register/soc/sdio_hinf_reg.h
+++ b/components/soc/esp32/register/soc/sdio_hinf_reg.h
--- a/components/soc/esp32/register/soc/sdio_hinf_struct.h
+++ b/components/soc/esp32/register/soc/sdio_hinf_struct.h
--- a/components/soc/esp32/register/soc/sdio_slc_host_reg.h
+++ b/components/soc/esp32/register/soc/sdio_slc_host_reg.h
--- a/components/soc/esp32/register/soc/sdio_slc_host_struct.h
+++ b/components/soc/esp32/register/soc/sdio_slc_host_struct.h
--- a/components/soc/esp32/register/soc/sdio_slc_reg.h
+++ b/components/soc/esp32/register/soc/sdio_slc_reg.h
--- a/components/soc/esp32/register/soc/sdio_slc_struct.h
+++ b/components/soc/esp32/register/soc/sdio_slc_struct.h
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@ -223,6 +223,10 @@ config SOC_WDT_SUPPORTED
    bool
    default y

+config SOC_SDIO_SLAVE_SUPPORTED
+    bool
+    default y
+
 config SOC_SPI_FLASH_SUPPORTED
    bool
    default y
--- a/components/soc/esp32c5/include/soc/sdio_slave_pins.h
+++ b/components/soc/esp32c5/include/soc/sdio_slave_pins.h
@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD  10
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK  9
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0   8
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1   7
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2   14
+#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3   13
+#define SDIO_SLAVE_SLOT0_FUNC               0
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@ -72,6 +72,7 @@
 #define SOC_CLK_TREE_SUPPORTED          1
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_WDT_SUPPORTED               1
+#define SOC_SDIO_SLAVE_SUPPORTED        1
 #define SOC_SPI_FLASH_SUPPORTED         1     // TODO: [ESP32C5] IDF-8715
 #define SOC_ECDSA_SUPPORTED             1
 #define SOC_RNG_SUPPORTED               1
--- a/components/soc/esp32c5/register/soc/reg_base.h
+++ b/components/soc/esp32c5/register/soc/reg_base.h
@ -34,7 +34,7 @@
 #define DR_REG_PARL_IO_BASE                       0x60015000
 #define DR_REG_HINF_BASE                          0x60016000
 #define DR_REG_SLC_BASE                           0x60017000
-#define DR_REG_SLC_HOST_BASE                      0x60018000
+#define DR_REG_SLCHOST_BASE                       0x60018000
 #define DR_REG_PVT_MONITOR_BASE                   0x60019000
 #define DR_REG_PSRAM_MEM_MONITOR_BASE             0x6001A000

--- a/components/soc/esp32c5/register/soc/sdio_slc_host_reg.h
+++ b/components/soc/esp32c5/register/soc/sdio_slc_host_reg.h
@ -14,7 +14,7 @@ extern "C" {
 /** SDIO_SLC_HOST_FUNC2_0_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_FUNC2_0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x10)
+#define SDIO_SLC_HOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10)
 /** SDIO_SLC_HOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0;
 *  *******Description***********
 */
@ -26,7 +26,7 @@ extern "C" {
 /** SDIO_SLC_HOST_FUNC2_1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_FUNC2_1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x14)
+#define SDIO_SLC_HOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14)
 /** SDIO_SLC_HOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -38,7 +38,7 @@ extern "C" {
 /** SDIO_SLC_HOST_FUNC2_2_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_FUNC2_2_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x20)
+#define SDIO_SLC_HOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20)
 /** SDIO_SLC_HOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1;
 *  *******Description***********
 */
@ -50,7 +50,7 @@ extern "C" {
 /** SDIO_SLC_HOST_GPIO_STATUS0_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_GPIO_STATUS0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x34)
+#define SDIO_SLC_HOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34)
 /** SDIO_SLC_HOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -62,7 +62,7 @@ extern "C" {
 /** SDIO_SLC_HOST_GPIO_STATUS1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_GPIO_STATUS1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x38)
+#define SDIO_SLC_HOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
 /** SDIO_SLC_HOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -74,7 +74,7 @@ extern "C" {
 /** SDIO_SLC_HOST_GPIO_IN0_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_GPIO_IN0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x3c)
+#define SDIO_SLC_HOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3c)
 /** SDIO_SLC_HOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -86,7 +86,7 @@ extern "C" {
 /** SDIO_SLC_HOST_GPIO_IN1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_GPIO_IN1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x40)
+#define SDIO_SLC_HOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40)
 /** SDIO_SLC_HOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -98,7 +98,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x44)
+#define SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
 /** SDIO_SLC_HOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0;
 *  *******Description***********
 */
@ -131,7 +131,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0_HOST_PF_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0_HOST_PF_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x48)
+#define SDIO_SLC_HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
 /** SDIO_SLC_HOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -143,7 +143,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1_HOST_PF_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1_HOST_PF_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x4c)
+#define SDIO_SLC_HOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4c)
 /** SDIO_SLC_HOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -155,7 +155,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x50)
+#define SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
 /** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -342,7 +342,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x54)
+#define SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54)
 /** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -529,7 +529,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_INT_ST_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_INT_ST_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x58)
+#define SDIO_SLC_HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
 /** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -716,7 +716,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_INT_ST_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_INT_ST_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x5c)
+#define SDIO_SLC_HOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5c)
 /** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -903,7 +903,7 @@ extern "C" {
 /** SDIO_SLC_HOST_PKT_LEN_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_PKT_LEN_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x60)
+#define SDIO_SLC_HOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
 /** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0;
 *  *******Description***********
 */
@ -922,7 +922,7 @@ extern "C" {
 /** SDIO_SLC_HOST_STATE_W0_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_STATE_W0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x64)
+#define SDIO_SLC_HOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64)
 /** SDIO_SLC_HOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -955,7 +955,7 @@ extern "C" {
 /** SDIO_SLC_HOST_STATE_W1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_STATE_W1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x68)
+#define SDIO_SLC_HOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68)
 /** SDIO_SLC_HOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -988,7 +988,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W0_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x6c)
+#define SDIO_SLC_HOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6c)
 /** SDIO_SLC_HOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1021,7 +1021,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x70)
+#define SDIO_SLC_HOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70)
 /** SDIO_SLC_HOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1054,7 +1054,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W2_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W2_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x74)
+#define SDIO_SLC_HOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74)
 /** SDIO_SLC_HOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1087,7 +1087,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W3_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W3_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x78)
+#define SDIO_SLC_HOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78)
 /** SDIO_SLC_HOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192;
 *  *******Description***********
 */
@ -1120,7 +1120,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W4_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W4_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x7c)
+#define SDIO_SLC_HOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7c)
 /** SDIO_SLC_HOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255;
 *  *******Description***********
 */
@ -1153,7 +1153,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W5_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W5_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x80)
+#define SDIO_SLC_HOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80)
 /** SDIO_SLC_HOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1186,7 +1186,7 @@ extern "C" {
 /** SDIO_SLC_HOST_WIN_CMD_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_WIN_CMD_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x84)
+#define SDIO_SLC_HOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84)
 /** SDIO_SLC_HOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0;
 *  *******Description***********
 */
@ -1198,7 +1198,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W6_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W6_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x88)
+#define SDIO_SLC_HOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88)
 /** SDIO_SLC_HOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1231,7 +1231,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W7_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W7_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x8c)
+#define SDIO_SLC_HOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8c)
 /** SDIO_SLC_HOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1264,7 +1264,7 @@ extern "C" {
 /** SDIO_SLC_HOST_PKT_LEN0_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_PKT_LEN0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x90)
+#define SDIO_SLC_HOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90)
 /** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0;
 *  *******Description***********
 */
@ -1283,7 +1283,7 @@ extern "C" {
 /** SDIO_SLC_HOST_PKT_LEN1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_PKT_LEN1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x94)
+#define SDIO_SLC_HOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94)
 /** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0;
 *  *******Description***********
 */
@ -1302,7 +1302,7 @@ extern "C" {
 /** SDIO_SLC_HOST_PKT_LEN2_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_PKT_LEN2_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x98)
+#define SDIO_SLC_HOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98)
 /** SDIO_SLC_HOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0;
 *  *******Description***********
 */
@ -1321,7 +1321,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W8_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W8_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x9c)
+#define SDIO_SLC_HOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9c)
 /** SDIO_SLC_HOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1354,7 +1354,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W9_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W9_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xa0)
+#define SDIO_SLC_HOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xa0)
 /** SDIO_SLC_HOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1387,7 +1387,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W10_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W10_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xa4)
+#define SDIO_SLC_HOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xa4)
 /** SDIO_SLC_HOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1420,7 +1420,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W11_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W11_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xa8)
+#define SDIO_SLC_HOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xa8)
 /** SDIO_SLC_HOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1453,7 +1453,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W12_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W12_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xac)
+#define SDIO_SLC_HOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xac)
 /** SDIO_SLC_HOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1486,7 +1486,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W13_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W13_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xb0)
+#define SDIO_SLC_HOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xb0)
 /** SDIO_SLC_HOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1519,7 +1519,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W14_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W14_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xb4)
+#define SDIO_SLC_HOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xb4)
 /** SDIO_SLC_HOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1552,7 +1552,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_W15_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_W15_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xb8)
+#define SDIO_SLC_HOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xb8)
 /** SDIO_SLC_HOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0;
 *  *******Description***********
 */
@ -1585,7 +1585,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CHECK_SUM0_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CHECK_SUM0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xbc)
+#define SDIO_SLC_HOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xbc)
 /** SDIO_SLC_HOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -1597,7 +1597,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CHECK_SUM1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CHECK_SUM1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xc0)
+#define SDIO_SLC_HOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xc0)
 /** SDIO_SLC_HOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319;
 *  *******Description***********
 */
@ -1609,7 +1609,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xc4)
+#define SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xc4)
 /** SDIO_SLC_HOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0;
 *  *******Description***********
 */
@ -1642,7 +1642,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xc8)
+#define SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xc8)
 /** SDIO_SLC_HOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0;
 *  *******Description***********
 */
@ -1661,7 +1661,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xcc)
+#define SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xcc)
 /** SDIO_SLC_HOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0;
 *  *******Description***********
 */
@ -1680,7 +1680,7 @@ extern "C" {
 /** SDIO_SLC_HOST_TOKEN_CON_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_TOKEN_CON_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xd0)
+#define SDIO_SLC_HOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xd0)
 /** SDIO_SLC_HOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -1748,7 +1748,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xd4)
+#define SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd4)
 /** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -1935,7 +1935,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xd8)
+#define SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xd8)
 /** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -2122,7 +2122,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xdc)
+#define SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xdc)
 /** SDIO_SLC_HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -2309,7 +2309,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xe0)
+#define SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe0)
 /** SDIO_SLC_HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -2496,7 +2496,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xe4)
+#define SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe4)
 /** SDIO_SLC_HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -2683,7 +2683,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xe8)
+#define SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xe8)
 /** SDIO_SLC_HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -2870,7 +2870,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xec)
+#define SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xec)
 /** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -3057,7 +3057,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xf0)
+#define SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xf0)
 /** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -3244,7 +3244,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xf4)
+#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf4)
 /** SDIO_SLC_HOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0;
 *  *******Description***********
 */
@ -3256,7 +3256,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xf8)
+#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xf8)
 /** SDIO_SLC_HOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0;
 *  *******Description***********
 */
@ -3268,7 +3268,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG (DR_REG_SDIO_SLC_HOST_BASE + 0xfc)
+#define SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xfc)
 /** SDIO_SLC_HOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -3280,7 +3280,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x100)
+#define SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100)
 /** SDIO_SLC_HOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -3292,7 +3292,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC_APBWIN_CONF_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC_APBWIN_CONF_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x104)
+#define SDIO_SLC_HOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104)
 /** SDIO_SLC_HOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0;
 *  *******Description***********
 */
@ -3318,7 +3318,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x108)
+#define SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108)
 /** SDIO_SLC_HOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0;
 *  *******Description***********
 */
@ -3330,7 +3330,7 @@ extern "C" {
 /** SDIO_SLC_HOST_RDCLR0_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_RDCLR0_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x10c)
+#define SDIO_SLC_HOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10c)
 /** SDIO_SLC_HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68;
 *  *******Description***********
 */
@ -3349,7 +3349,7 @@ extern "C" {
 /** SDIO_SLC_HOST_RDCLR1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_RDCLR1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x110)
+#define SDIO_SLC_HOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110)
 /** SDIO_SLC_HOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480;
 *  *******Description***********
 */
@ -3368,7 +3368,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x114)
+#define SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114)
 /** SDIO_SLC_HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -3555,7 +3555,7 @@ extern "C" {
 /** SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x118)
+#define SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118)
 /** SDIO_SLC_HOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0;
 *  *******Description***********
 */
@ -3742,7 +3742,7 @@ extern "C" {
 /** SDIO_SLC_HOST_DATE_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_DATE_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x178)
+#define SDIO_SLC_HOST_DATE_REG (DR_REG_SLCHOST_BASE + 0x178)
 /** SDIO_SLC_HOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136;
 *  *******Description***********
 */
@ -3754,7 +3754,7 @@ extern "C" {
 /** SDIO_SLC_HOST_ID_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_ID_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x17c)
+#define SDIO_SLC_HOST_ID_REG (DR_REG_SLCHOST_BASE + 0x17c)
 /** SDIO_SLC_HOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536;
 *  *******Description***********
 */
@ -3766,7 +3766,7 @@ extern "C" {
 /** SDIO_SLC_HOST_CONF_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_CONF_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x1f0)
+#define SDIO_SLC_HOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1f0)
 /** SDIO_SLC_HOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0;
 *  *******Description***********
 */
@ -3827,7 +3827,7 @@ extern "C" {
 /** SDIO_SLC_HOST_INF_ST_REG register
 *  *******Description***********
 */
-#define SDIO_SLC_HOST_INF_ST_REG (DR_REG_SDIO_SLC_HOST_BASE + 0x1f4)
+#define SDIO_SLC_HOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1f4)
 /** SDIO_SLC_HOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0;
 *  *******Description***********
 */
--- a/components/soc/esp32c5/sdio_slave_periph.c
+++ b/components/soc/esp32c5/sdio_slave_periph.c
@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "soc/sdio_slave_periph.h"
+#include "soc/sdio_slave_pins.h"
+
+const sdio_slave_slot_info_t sdio_slave_slot_info[1]  = {
+    {
+        .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK,
+        .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD,
+        .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0,
+        .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1,
+        .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2,
+        .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3,
+        .func = SDIO_SLAVE_SLOT0_FUNC,
+    },
+};
--- a/components/soc/esp32c6/register/soc/sdio_hinf_reg.h
+++ b/components/soc/esp32c6/register/soc/sdio_hinf_reg.h
--- a/components/soc/esp32c6/register/soc/sdio_hinf_struct.h
+++ b/components/soc/esp32c6/register/soc/sdio_hinf_struct.h
--- a/components/soc/esp32c6/register/soc/sdio_slc_host_reg.h
+++ b/components/soc/esp32c6/register/soc/sdio_slc_host_reg.h
--- a/components/soc/esp32c6/register/soc/sdio_slc_host_struct.h
+++ b/components/soc/esp32c6/register/soc/sdio_slc_host_struct.h
--- a/components/soc/esp32c6/register/soc/sdio_slc_reg.h
+++ b/components/soc/esp32c6/register/soc/sdio_slc_reg.h
--- a/components/soc/esp32c6/register/soc/sdio_slc_struct.h
+++ b/components/soc/esp32c6/register/soc/sdio_slc_struct.h
--- a/components/soc/include/soc/sdio_slave_periph.h
+++ b/components/soc/include/soc/sdio_slave_periph.h
@ -10,12 +10,12 @@
 #include "soc/soc_caps.h"
 #include "soc/soc_pins.h"
 #if SOC_SDIO_SLAVE_SUPPORTED
-#include "soc/slc_reg.h"
-#include "soc/slc_struct.h"
-#include "soc/host_reg.h"
-#include "soc/host_struct.h"
-#include "soc/hinf_reg.h"
-#include "soc/hinf_struct.h"
+#include "soc/sdio_slc_reg.h"
+#include "soc/sdio_slc_struct.h"
+#include "soc/sdio_slc_host_reg.h"
+#include "soc/sdio_slc_host_struct.h"
+#include "soc/sdio_hinf_reg.h"
+#include "soc/sdio_hinf_struct.h"
 #endif

 #ifdef __cplusplus
--- a/docs/conf_common.py
+++ b/docs/conf_common.py
@ -285,7 +285,7 @@ ESP32C3_DOCS = ['hw-reference/esp32c3/**', 'api-guides/RF_calibration.rst', 'api

 ESP32C2_DOCS = ['api-guides/RF_calibration.rst', 'api-guides/phy.rst']

-ESP32C5_DOCS = ['api-guides/phy.rst']
+ESP32C5_DOCS = ['api-guides/phy.rst', 'api-reference/peripherals/sd_pullup_requirements.rst']

 ESP32C61_DOCS = ['api-guides/phy.rst']

--- a/examples/peripherals/sdio/host/main/Kconfig.projbuild
+++ b/examples/peripherals/sdio/host/main/Kconfig.projbuild
@ -47,6 +47,13 @@ menu "Example Configuration"

            If the example does not work, please try disabling the HS mode.

+    config EXAMPLE_SDIO_HOST_DELAY
+        int "SDIO Host Delay"
+        range 0 5
+        default 0
+        help
+            SDIO Host delay phase
+
    config EXAMPLE_ADJUSTABLE_PIN
        bool
        default EXAMPLE_SDIO_OVER_SPI || SOC_SDMMC_USE_GPIO_MATRIX
@ -55,36 +62,42 @@ menu "Example Configuration"
        int "CMD (MOSI) GPIO number"
        depends on EXAMPLE_ADJUSTABLE_PIN
        range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
+        default 4 if IDF_TARGET_ESP32P4
        default 15

    config EXAMPLE_PIN_CLK
        int "CLK GPIO number"
        depends on EXAMPLE_ADJUSTABLE_PIN
        range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
+        default 33 if IDF_TARGET_ESP32P4
        default 14

    config EXAMPLE_PIN_D0
        int "D0 (MISO) GPIO number"
        depends on EXAMPLE_ADJUSTABLE_PIN
        range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
+        default 32 if IDF_TARGET_ESP32P4
        default 2

    config EXAMPLE_PIN_D1
        int "D1 (INTR) GPIO number"
        depends on EXAMPLE_ADJUSTABLE_PIN
        range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
+        default 23 if IDF_TARGET_ESP32P4
        default 4

    config EXAMPLE_PIN_D2
        int "D2 GPIO number"
        depends on EXAMPLE_ADJUSTABLE_PIN
        range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
+        default 53 if IDF_TARGET_ESP32P4
        default 12

    config EXAMPLE_PIN_D3
        int "D3 (CS) GPIO number"
        depends on EXAMPLE_ADJUSTABLE_PIN
        range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
+        default 5 if IDF_TARGET_ESP32P4
        default 13

    choice EXAMPLE_SLAVE
@ -100,11 +113,11 @@ menu "Example Configuration"
    endchoice

    config EXAMPLE_SLAVE_PWR_NEGTIVE_ACTIVE
-        bool "Slave power control pin is negtive active, otherwise postive active"
+        bool "Slave power control pin is negative active, otherwise positive active"
        depends on !EXAMPLE_SLAVE_NONE
        default n
        help
-            Slave power control pin is negtive active, otherwise postive active
+            Slave power control pin is negative active, otherwise positive active

    config EXAMPLE_NO_INTR_LINE
        bool "The host is not connected to the interrupt line (DAT1) of slave"
--- a/examples/peripherals/sdio/host/main/app_main.c
+++ b/examples/peripherals/sdio/host/main/app_main.c
@ -78,12 +78,12 @@
            - 0 is the register to hold tasks. Bits:
                - 0: the slave should reset.
                - 1: the slave should send interrupts.
-                - 2: the slave should write the shared registers acoording to the value in register 1.
+                - 2: the slave should write the shared registers according to the value in register 1.
            - 1 is the register to hold test value.
            - other registers will be written by the slave for testing.

        - FIFO:
-            The receving FIFO is size of 256 bytes.
+            The receiving FIFO is size of 256 bytes.
            When the host writes something to slave recv FIFO, the slave should return it as is to the sending FIFO.

    The example works as following process:
@ -190,6 +190,7 @@ esp_err_t slave_init(essl_handle_t* handle)
    ESP_LOGI(TAG, "Probe using SD 1-bit...");
    config.flags = SDMMC_HOST_FLAG_1BIT;
 #endif
+    config.input_delay_phase = CONFIG_EXAMPLE_SDIO_HOST_DELAY;

 #ifdef CONFIG_EXAMPLE_SDIO_HIGHSPEED
    config.max_freq_khz = SDMMC_FREQ_HIGHSPEED;
@ -440,7 +441,7 @@ void job_fifo(essl_handle_t handle)
    /* CAUTION: This example shows that we can send random length of packet to the slave.
     * However it takes time of two transactions if the length is not multiples of 4 bytes.
     * e.g. sending 6 bytes is done by sending 4 + 2 bytes each transaction.
-     * Try to avoid unaligned packets if possible to get higher effeciency.
+     * Try to avoid unaligned packets if possible to get higher efficiency.
     */
    for (int i = 0; i < sizeof(packet_len) / sizeof(int); i++) {
        //Prepare data to send. The length can be random, but data should start at the 32-bit boundary.
--- a/examples/peripherals/sdio/host/sdkconfig.defaults.esp32p4
+++ b/examples/peripherals/sdio/host/sdkconfig.defaults.esp32p4
@ -0,0 +1,2 @@
+## On P4-SDMMC + C5 SDIO test runner environment, hardware delay needs to be considered
+CONFIG_EXAMPLE_SDIO_HOST_DELAY=2
--- a/examples/peripherals/sdio/slave/README.md
+++ b/examples/peripherals/sdio/slave/README.md
@ -1,4 +1,4 @@
-| Supported Targets | ESP32 | ESP32-C6 |
-| ----------------- | ----- | -------- |
+| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 |
+| ----------------- | ----- | -------- | -------- |

 See README.md in the parent folder
--- a/tools/ci/idf_pytest/constants.py
+++ b/tools/ci/idf_pytest/constants.py
@ -140,6 +140,7 @@ ENV_MARKERS = {
    'twai_network': 'multiple runners form a TWAI network.',
    'sdio_master_slave': 'Test sdio multi board, esp32+esp32',
    'sdio_multidev_32_c6': 'Test sdio multi board, esp32+esp32c6',
+    'sdio_multidev_p4_c5': 'Test sdio multi board, esp32p4+esp32c5',
    'usj_device': 'Test usb_serial_jtag and usb_serial_jtag is used as serial only (not console)',
    'twai_std': 'twai runner with all twai supported targets connect to usb-can adapter',
    'lp_i2s': 'lp_i2s runner tested with hp_i2s',