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fix: add delay after WDT reset for better stability

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This commit is contained in:
Peter Dragun
2024-12-16 16:17:41 +01:00
parent a6bceb7207
commit 188c162129
4 changed files with 12 additions and 4 deletions
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4
esptool/targets/esp32c3.py
View File

@@ -4,6 +4,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
from time import sleep
from typing import Dict
from .esp32 import ESP32ROM
@@ -255,13 +256,14 @@ class ESP32C3ROM(ESP32ROM):
def hard_reset(self):
if self.uses_usb_jtag_serial():
self.rtc_wdt_reset()
sleep(0.5) # wait for reset to take effect
else:
ESPLoader.hard_reset(self)
def rtc_wdt_reset(self):
print("Hard resetting with RTC WDT...")
self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY) # unlock
self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000) # set WDT timeout
self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000) # set WDT timeout
self.write_reg(
self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
) # enable WDT

4
esptool/targets/esp32p4.py
View File

@@ -4,6 +4,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
from time import sleep
from typing import Dict
from .esp32 import ESP32ROM
@@ -264,7 +265,7 @@ class ESP32P4ROM(ESP32ROM):
def rtc_wdt_reset(self):
print("Hard resetting with RTC WDT...")
self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY) # unlock
self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000) # set WDT timeout
self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000) # set WDT timeout
self.write_reg(
self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
) # enable WDT
@@ -273,6 +274,7 @@ class ESP32P4ROM(ESP32ROM):
def hard_reset(self):
if self.uses_usb_jtag_serial() or self.uses_usb_otg():
self.rtc_wdt_reset()
sleep(0.5) # wait for reset to take effect
else:
ESPLoader.hard_reset(self)

4
esptool/targets/esp32s2.py
View File

@@ -4,6 +4,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
from time import sleep
from typing import Dict
from .esp32 import ESP32ROM
@@ -290,7 +291,7 @@ class ESP32S2ROM(ESP32ROM):
def rtc_wdt_reset(self):
print("Hard resetting with RTC WDT...")
self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY) # unlock
self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000) # set WDT timeout
self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000) # set WDT timeout
self.write_reg(
self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
) # enable WDT
@@ -307,6 +308,7 @@ class ESP32S2ROM(ESP32ROM):
and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
):
self.rtc_wdt_reset()
sleep(0.5) # wait for reset to take effect
return
ESPLoader.hard_reset(self, uses_usb_otg)

4
esptool/targets/esp32s3.py
View File

@@ -4,6 +4,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
import struct
from time import sleep
from typing import Dict
from .esp32 import ESP32ROM
@@ -354,7 +355,7 @@ class ESP32S3ROM(ESP32ROM):
def rtc_wdt_reset(self):
print("Hard resetting with RTC WDT...")
self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY) # unlock
self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 5000) # set WDT timeout
self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000) # set WDT timeout
self.write_reg(
self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
) # enable WDT
@@ -380,6 +381,7 @@ class ESP32S3ROM(ESP32ROM):
and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
):
self.rtc_wdt_reset()
sleep(0.5) # wait for reset to take effect
return
ESPLoader.hard_reset(self, uses_usb_otg)