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fix(ESP32-S3): Correct RTC WDT registers to fix resets during flashing

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This commit is contained in:
radim.karnis
2023-06-01 12:33:23 +02:00
parent f1132e84cb
commit 6fd91afec4
4 changed files with 4 additions and 4 deletions
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2
esptool/targets/esp32s3.py
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@@ -89,7 +89,7 @@ class ESP32S3ROM(ESP32ROM):
RTC_CNTL_SWD_WPROTECT_REG = RTCCNTL_BASE_REG + 0x00B8 RTC_CNTL_SWD_WPROTECT_REG = RTCCNTL_BASE_REG + 0x00B8
RTC_CNTL_SWD_WKEY = 0x8F1D312A RTC_CNTL_SWD_WKEY = 0x8F1D312A
RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0090 RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0098
RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x00B0 RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x00B0
RTC_CNTL_WDT_WKEY = 0x50D83AA1 RTC_CNTL_WDT_WKEY = 0x50D83AA1

2
esptool/targets/stub_flasher/stub_flasher_32s3.json
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esptool/targets/stub_flasher/stub_flasher_32s3beta2.json
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2
flasher_stub/include/soc_support.h
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@@ -324,7 +324,7 @@
#ifdef ESP32S3 #ifdef ESP32S3
#define RTC_CNTL_OPTION1_REG (RTCCNTL_BASE_REG + 0x012C) #define RTC_CNTL_OPTION1_REG (RTCCNTL_BASE_REG + 0x012C)
#define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0090) // RTC_CNTL_RTC_WDTCONFIG0_REG #define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0098) // RTC_CNTL_RTC_WDTCONFIG0_REG
#define RTC_CNTL_WDTWPROTECT_REG (RTCCNTL_BASE_REG + 0x00B0) // RTC_CNTL_RTC_WDTWPROTECT_REG #define RTC_CNTL_WDTWPROTECT_REG (RTCCNTL_BASE_REG + 0x00B0) // RTC_CNTL_RTC_WDTWPROTECT_REG
#define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00B4) #define RTC_CNTL_SWD_CONF_REG (RTCCNTL_BASE_REG + 0x00B4)
#define RTC_CNTL_SWD_WPROTECT_REG (RTCCNTL_BASE_REG + 0x00B8) #define RTC_CNTL_SWD_WPROTECT_REG (RTCCNTL_BASE_REG + 0x00B8)