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feat(espefuse): Adds 3 bit for PSRAM_CAP efuse field

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This commit is contained in:
Konstantin Kondrashov
2024-11-04 17:47:00 +02:00
committed by Radim Karniš
parent 26b676bef7
commit ab2e0bf8d6
4 changed files with 36 additions and 4 deletions
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13
espefuse/efuse/esp32s3/fields.py
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@@ -335,9 +335,22 @@ class EfuseField(base_fields.EfuseFieldBase):
"t_sensor": EfuseTempSensor,
"adc_tp": EfuseAdcPointCalibration,
"wafer": EfuseWafer,
"psram_cap": EfusePsramCap,
}.get(efuse.class_type, EfuseField)(parent, efuse)
class EfusePsramCap(EfuseField):
def get(self, from_read=True):
hi_bits = self.parent["PSRAM_CAP_3"].get(from_read)
assert self.parent["PSRAM_CAP_3"].bit_len == 1
lo_bits = self.parent["PSRAM_CAP"].get(from_read)
assert self.parent["PSRAM_CAP"].bit_len == 2
return (hi_bits << 2) + lo_bits
def save(self, new_value):
raise esptool.FatalError("Burning %s is not supported" % self.name)
class EfuseWafer(EfuseField):
def get(self, from_read=True):
hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read)

10
espefuse/efuse/esp32s3/mem_definition.py
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@@ -159,6 +159,16 @@ class EfuseDefineFields(EfuseFieldsBase):
f.description = "calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI << 3 + WAFER_VERSION_MINOR_LO (read only)"
self.CALC.append(f)
f = Field()
f.name = "PSRAM_CAPACITY"
f.block = 0
f.bit_len = 3
f.type = f"uint:{f.bit_len}"
f.category = "identity"
f.class_type = "psram_cap"
f.description = "calc as = PSRAM_CAP_3 << 2 + PSRAM_CAP (read only)"
self.CALC.append(f)
for efuse in self.ALL_EFUSES:
if efuse is not None:
self.EFUSES.append(efuse)

8
espefuse/efuse_defs/esp32s3.yaml
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@@ -1,4 +1,4 @@
VER_NO: f75f74727101326a187188a23f4a6c70
VER_NO: 7127dd097e72bb90d0b790d460993126
EFUSES:
WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'}
RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'}
@@ -87,7 +87,7 @@ EFUSES:
FLASH_CAP : {show: y, blk : 1, word: 3, pos: 27, len : 3, start: 123, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "8M", 2: "4M"}', desc: Flash capacity, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[29:27]', bloc: 'B15[5:3]'}
FLASH_TEMP : {show: y, blk : 1, word: 3, pos: 30, len : 2, start: 126, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "105C", 2: "85C"}', desc: Flash temperature, rloc: 'EFUSE_RD_MAC_SPI_SYS_3_REG[31:30]', bloc: 'B15[7:6]'}
FLASH_VENDOR : {show: y, blk : 1, word: 4, pos : 0, len : 3, start: 128, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "XMC", 2: "GD", 3: "FM", 4: "TT", 5: "BY"}', desc: Flash vendor, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[2:0]', bloc: 'B16[2:0]'}
PSRAM_CAP : {show: y, blk : 1, word: 4, pos : 3, len : 2, start: 131, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "8M", 2: "2M"}', desc: PSRAM capacity, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[4:3]', bloc: 'B16[4:3]'}
PSRAM_CAP : {show: y, blk : 1, word: 4, pos : 3, len : 2, start: 131, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "8M", 2: "2M", 3: "16M", 4: "4M"}', desc: PSRAM capacity, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[4:3]', bloc: 'B16[4:3]'}
PSRAM_TEMP : {show: y, blk : 1, word: 4, pos : 5, len : 2, start: 133, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "105C", 2: "85C"}', desc: PSRAM temperature, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[6:5]', bloc: 'B16[6:5]'}
PSRAM_VENDOR : {show: y, blk : 1, word: 4, pos : 7, len : 2, start: 135, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict: '{0: "None", 1: "AP_3v3", 2: "AP_1v8"}', desc: PSRAM vendor, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[8:7]', bloc: 'B16[7],B17[0]'}
RESERVED_1_137 : {show: n, blk : 1, word: 4, pos : 9, len : 4, start: 137, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[12:9]', bloc: 'B17[4:1]'}
@@ -96,7 +96,9 @@ EFUSES:
V_RTC_DBIAS20 : {show: y, blk : 1, word: 4, pos: 27, len : 8, start: 155, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 voltage of rtc dbias20, rloc: 'EFUSE_RD_MAC_SPI_SYS_4_REG[31:27]', bloc: 'B19[7:3],B20[2:0]'}
V_DIG_DBIAS20 : {show: y, blk : 1, word: 5, pos : 3, len : 8, start: 163, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 voltage of digital dbias20, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[10:3]', bloc: 'B20[7:3],B21[2:0]'}
DIG_DBIAS_HVT : {show: y, blk : 1, word: 5, pos: 11, len : 5, start: 171, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: BLOCK1 digital dbias when hvt, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[15:11]', bloc: 'B21[7:3]'}
RESERVED_1_176 : {show: n, blk : 1, word: 5, pos: 16, len : 7, start: 176, type : 'uint:7', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[22:16]', bloc: 'B22[6:0]'}
RESERVED_1_176 : {show: n, blk : 1, word: 5, pos: 16, len : 3, start: 176, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[18:16]', bloc: 'B22[2:0]'}
PSRAM_CAP_3 : {show: y, blk : 1, word: 5, pos: 19, len : 1, start: 179, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PSRAM capacity bit 3, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[19]', bloc: 'B22[3]'}
RESERVED_1_180 : {show: n, blk : 1, word: 5, pos: 20, len : 3, start: 180, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[22:20]', bloc: 'B22[6:4]'}
WAFER_VERSION_MINOR_HI : {show: y, blk : 1, word: 5, pos: 23, len : 1, start: 183, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MINOR most significant bit, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[23]', bloc: 'B22[7]'}
WAFER_VERSION_MAJOR : {show: y, blk : 1, word: 5, pos: 24, len : 2, start: 184, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: WAFER_VERSION_MAJOR, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[25:24]', bloc: 'B23[1:0]'}
ADC2_CAL_VOL_ATTEN3 : {show: y, blk : 1, word: 5, pos: 26, len : 6, start: 186, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: ADC2 calibration voltage at atten3, rloc: 'EFUSE_RD_MAC_SPI_SYS_5_REG[31:26]', bloc: 'B23[7:2]'}

9
esptool/targets/esp32s3.py
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@@ -209,7 +209,12 @@ class ESP32S3ROM(ESP32ROM):
def get_psram_cap(self):
num_word = 4
return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 3) & 0x03
psram_cap = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 3) & 0x03
num_word = 5
psram_cap_hi_bit = (
self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 19
) & 0x01
return (psram_cap_hi_bit << 2) | psram_cap
def get_psram_vendor(self):
num_word = 4
@@ -231,6 +236,8 @@ class ESP32S3ROM(ESP32ROM):
0: None,
1: "Embedded PSRAM 8MB",
2: "Embedded PSRAM 2MB",
3: "Embedded PSRAM 16MB",
4: "Embedded PSRAM 4MB",
}.get(self.get_psram_cap(), "Unknown Embedded PSRAM")
if psram is not None:
features += [psram + f" ({self.get_psram_vendor()})"]