mirror of
https://github.com/fernandotcl/TinyEMU.git
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119 lines
4.2 KiB
C
119 lines
4.2 KiB
C
/*
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* RISCV CPU emulator
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*
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* Copyright (c) 2016-2017 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#include <stdlib.h>
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#include "cutils.h"
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#include "iomem.h"
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#define MIP_USIP (1 << 0)
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#define MIP_SSIP (1 << 1)
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#define MIP_HSIP (1 << 2)
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#define MIP_MSIP (1 << 3)
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#define MIP_UTIP (1 << 4)
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#define MIP_STIP (1 << 5)
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#define MIP_HTIP (1 << 6)
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#define MIP_MTIP (1 << 7)
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#define MIP_UEIP (1 << 8)
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#define MIP_SEIP (1 << 9)
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#define MIP_HEIP (1 << 10)
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#define MIP_MEIP (1 << 11)
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typedef struct RISCVCPUState RISCVCPUState;
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typedef struct {
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RISCVCPUState *(*riscv_cpu_init)(PhysMemoryMap *mem_map);
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void (*riscv_cpu_end)(RISCVCPUState *s);
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void (*riscv_cpu_interp)(RISCVCPUState *s, int n_cycles);
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uint64_t (*riscv_cpu_get_cycles)(RISCVCPUState *s);
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void (*riscv_cpu_set_mip)(RISCVCPUState *s, uint32_t mask);
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void (*riscv_cpu_reset_mip)(RISCVCPUState *s, uint32_t mask);
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uint32_t (*riscv_cpu_get_mip)(RISCVCPUState *s);
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BOOL (*riscv_cpu_get_power_down)(RISCVCPUState *s);
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uint32_t (*riscv_cpu_get_misa)(RISCVCPUState *s);
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void (*riscv_cpu_flush_tlb_write_range_ram)(RISCVCPUState *s,
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uint8_t *ram_ptr, size_t ram_size);
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} RISCVCPUClass;
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typedef struct {
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const RISCVCPUClass *class_ptr;
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} RISCVCPUCommonState;
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int riscv_cpu_get_max_xlen(void);
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extern const RISCVCPUClass riscv_cpu_class32;
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extern const RISCVCPUClass riscv_cpu_class64;
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extern const RISCVCPUClass riscv_cpu_class128;
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RISCVCPUState *riscv_cpu_init(PhysMemoryMap *mem_map, int max_xlen);
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static inline void riscv_cpu_end(RISCVCPUState *s)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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c->riscv_cpu_end(s);
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}
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static inline void riscv_cpu_interp(RISCVCPUState *s, int n_cycles)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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c->riscv_cpu_interp(s, n_cycles);
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}
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static inline uint64_t riscv_cpu_get_cycles(RISCVCPUState *s)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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return c->riscv_cpu_get_cycles(s);
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}
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static inline void riscv_cpu_set_mip(RISCVCPUState *s, uint32_t mask)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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c->riscv_cpu_set_mip(s, mask);
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}
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static inline void riscv_cpu_reset_mip(RISCVCPUState *s, uint32_t mask)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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c->riscv_cpu_reset_mip(s, mask);
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}
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static inline uint32_t riscv_cpu_get_mip(RISCVCPUState *s)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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return c->riscv_cpu_get_mip(s);
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}
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static inline BOOL riscv_cpu_get_power_down(RISCVCPUState *s)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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return c->riscv_cpu_get_power_down(s);
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}
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static inline uint32_t riscv_cpu_get_misa(RISCVCPUState *s)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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return c->riscv_cpu_get_misa(s);
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}
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static inline void riscv_cpu_flush_tlb_write_range_ram(RISCVCPUState *s,
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uint8_t *ram_ptr, size_t ram_size)
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{
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const RISCVCPUClass *c = ((RISCVCPUCommonState *)s)->class_ptr;
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c->riscv_cpu_flush_tlb_write_range_ram(s, ram_ptr, ram_size);
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}
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#endif /* RISCV_CPU_H */
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