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152 lines
4.1 KiB
HTML
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<TITLE>gEDA/gaf's gnetlist </TITLE>
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<div id="navrule"></div>
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<h3>
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<A HREF="../index.html">Tools</A> → gnetlist
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</h3>
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</div>
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</div>
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<!--[if lt IE 7.]>
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<script defer type="text/javascript" src="../../pngfix.js"></script>
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<![endif]-->
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<div id="main">
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<CENTER>
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<H2>
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gnetlist<br>
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gEDA/gaf's Netlist Generation
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</H2>
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</CENTER>
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<br>
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<p>
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<H3>
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<A HREF="#whatis">What is gnetlist?</A><BR>
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<A HREF="#look">What does it look like?</A><BR>
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<A HREF="#author">Who is the author of gnetlist?</A><BR>
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<A HREF="#download">Where can I download it?</A><BR>
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</H3>
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<HR>
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<H4>
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<A NAME="whatis"></A>
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What is gnetlist?
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</H4>
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gnetlist is a netlist generation program. It takes as input gEDA/gaf .sch (schematic) file and the required .sym (symbol) files and converts them into netlists.
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<p>
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gnetlist supports writing the following netlist formats:
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<UL>
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<li>Allegro netlist format (-g allegro)</li>
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<li>BAE netlist format (-g bae)</li>
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<li>BOM / BOM2 - Bill of Materials (-g bom and -g bom2)</li>
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<li>Partslist 1,2,3 - More Bill of Materials (-g partslist[1-3])</li>
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<li>DRC - Start of a design rule checker (-g drc)</li>
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<li>DRC2 - A second design rule checker (-g drc2)</li>
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<li>gEDA - native format, mainly used for testing (-g geda)</li>
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<li>Gossip netlist format (-g gossip)</li>
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<li>PADS netlist format (-g pads)</li>
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<li>PCB / PCBboard (-g PCB and -g PCBboard)</li>
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<li>gsch2pcb backend (-g gsch2pcb)</li>
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<li>ProtelII netlist format (-g protelII)</li>
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<li>Spice compatible netlist format (-g spice)</li>
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<li>Enhanced spice compatible netlist format (-g spice-sdb)</li>
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<li>Switcap netlist format (-g switcap)</li>
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<li>Tango netlist format (-g tango)</li>
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<li>Verilog code (-g verilog)</li>
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<li>VHDL code (-g vhdl)</li>
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<li>VIPEC netlist format (-g vipec)</li>
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<li>Bartels Autoengineer netlist format (-g bae)</li>
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<li>GOSSIP system simulation system netlist format (-g gossip)</li>
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<li>MAXASCII netlist format (-g maxascii)</li>
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<li>VHDL-AMS netlist format (-g vams)</li>
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<li>Futurenet2 netlist format (-g futurenet2 )</li>
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<li>SWITCAP switched capacitor simulator netlist format (-g switcap )</li>
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<li>RF Cascade netlist format (-g cascade )</li>
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<li>RACAL-REDAC netlist format (-g redac )</li>
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<li>PCB actions file for forward annotating pin/pad names from schematic to layout (-g pcbpins)</li>
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</UL>
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<p>
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gnetlist supports the hierarchical traversal and various net merging/renaming
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methods. The greatest feature lacking from gnetlist is hierarchical bus support.
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<br>
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<p>
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<H4>
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<A NAME="look"></A>
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What does it look like?
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</H4>
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gnetlist is a text based utility. Any screenshow would be boring.
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<br>
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<p>
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<H4>
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<A NAME="author"></A>
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Who is the author of gnetlist?
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</H4>
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Gnetlist is a community effort with several dozen contributors participating in the gEDA Project.
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The project was originated by Ales Hvezda, and he wrote the original version of gnetlist.
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<br>
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<p>
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<H4>
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<A NAME="download"></A>
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Where can I download it?
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</H4>
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<A HREF="../../download.html">gEDA's download page</A><br>
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