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Merge pull request #3279 from HiFiPhile/dwc2_ep0

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dcd/dwc2: fix enumeration when EP0 size=8
This commit is contained in:
Ha Thach
2025-10-09 21:42:32 +07:00
committed by GitHub
parent 20c8e92f3a 16dd74912f
commit 0fab57b8c1
4 changed files with 138 additions and 70 deletions
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130
hw/bsp/BoardPresets.json
View File

@@ -12,26 +12,20 @@
"BOARD": "${presetName}" "BOARD": "${presetName}"
} }
}, },
{
"name": "default single config",
"hidden": true,
"description": "Configure preset for the ${presetName} board",
"generator": "Ninja",
"binaryDir": "${sourceDir}/build/${presetName}",
"cacheVariables": {
"BOARD": "${presetName}"
}
},
{ {
"name": "adafruit_clue", "name": "adafruit_clue",
"inherits": "default" "inherits": "default"
}, },
{
"name": "adafruit_feather_esp32_v2",
"inherits": "default"
},
{
"name": "adafruit_feather_esp32c6",
"inherits": "default"
},
{
"name": "adafruit_feather_esp32s2",
"inherits": "default"
},
{
"name": "adafruit_feather_esp32s3",
"inherits": "default"
},
{ {
"name": "adafruit_feather_rp2040_usb_host", "name": "adafruit_feather_rp2040_usb_host",
"inherits": "default" "inherits": "default"
@@ -40,14 +34,6 @@
"name": "adafruit_fruit_jam", "name": "adafruit_fruit_jam",
"inherits": "default" "inherits": "default"
}, },
{
"name": "adafruit_magtag_29gray",
"inherits": "default"
},
{
"name": "adafruit_metro_esp32s2",
"inherits": "default"
},
{ {
"name": "adafruit_metro_rp2350", "name": "adafruit_metro_rp2350",
"inherits": "default" "inherits": "default"
@@ -188,42 +174,6 @@
"name": "ek_tm4c123gxl", "name": "ek_tm4c123gxl",
"inherits": "default" "inherits": "default"
}, },
{
"name": "espressif_addax_1",
"inherits": "default"
},
{
"name": "espressif_c3_devkitc",
"inherits": "default"
},
{
"name": "espressif_c6_devkitc",
"inherits": "default"
},
{
"name": "espressif_kaluga_1",
"inherits": "default"
},
{
"name": "espressif_p4_function_ev",
"inherits": "default"
},
{
"name": "espressif_s2_devkitc",
"inherits": "default"
},
{
"name": "espressif_s3_devkitc",
"inherits": "default"
},
{
"name": "espressif_s3_devkitm",
"inherits": "default"
},
{
"name": "espressif_saola_1",
"inherits": "default"
},
{ {
"name": "f1c100s", "name": "f1c100s",
"inherits": "default" "inherits": "default"
@@ -823,6 +773,66 @@
{ {
"name": "xmc4700_relax", "name": "xmc4700_relax",
"inherits": "default" "inherits": "default"
},
{
"name": "adafruit_feather_esp32_v2",
"inherits": "default single config"
},
{
"name": "adafruit_feather_esp32c6",
"inherits": "default single config"
},
{
"name": "adafruit_feather_esp32s2",
"inherits": "default single config"
},
{
"name": "adafruit_feather_esp32s3",
"inherits": "default single config"
},
{
"name": "adafruit_magtag_29gray",
"inherits": "default single config"
},
{
"name": "adafruit_metro_esp32s2",
"inherits": "default single config"
},
{
"name": "espressif_addax_1",
"inherits": "default single config"
},
{
"name": "espressif_c3_devkitc",
"inherits": "default single config"
},
{
"name": "espressif_c6_devkitc",
"inherits": "default single config"
},
{
"name": "espressif_kaluga_1",
"inherits": "default single config"
},
{
"name": "espressif_p4_function_ev",
"inherits": "default single config"
},
{
"name": "espressif_s2_devkitc",
"inherits": "default single config"
},
{
"name": "espressif_s3_devkitc",
"inherits": "default single config"
},
{
"name": "espressif_s3_devkitm",
"inherits": "default single config"
},
{
"name": "espressif_saola_1",
"inherits": "default single config"
} }
], ],
"buildPresets": [ "buildPresets": [

36
src/portable/synopsys/dwc2/dcd_dwc2.c
View File

@@ -168,7 +168,7 @@ static void dma_setup_prepare(uint8_t rhport) {
- All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula): - All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula):
- 13 for setup packets + control words (up to 3 setup packets). - 13 for setup packets + control words (up to 3 setup packets).
- 1 for global NAK (not required/used here). - 1 for global NAK (not required/used here).
- Largest-EPsize/4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4 + 1)" - Largest-EPsize/4 + 1. (FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4 + 1)"
- 2 for each used OUT endpoint - 2 for each used OUT endpoint
Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum
@@ -282,8 +282,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum]; dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
if (dir == TUSB_DIR_IN) { if (dir == TUSB_DIR_IN) {
// Only disable currently enabled non-control endpoint if (!(dep->diepctl & DIEPCTL_EPENA)) {
if ((epnum == 0) || !(dep->diepctl & DIEPCTL_EPENA)) {
dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
} else { } else {
// Stop transmitting packets and NAK IN xfers. // Stop transmitting packets and NAK IN xfers.
@@ -701,12 +700,23 @@ static void handle_bus_reset(uint8_t rhport) {
dcfg.address = 0; dcfg.address = 0;
dwc2->dcfg = dcfg.value; dwc2->dcfg = dcfg.value;
// Fixed both control EP0 size to 64 bytes // 6. Configure maximum packet size for EP0
dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); uint8_t mps = 0;
dwc2->epout[0].ctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); switch (CFG_TUD_ENDPOINT0_SIZE) {
case 8: mps = 3; break;
case 16: mps = 2; break;
case 32: mps = 1; break;
case 64: mps = 0; break;
default: mps = 0; break;
}
xfer_status[0][TUSB_DIR_OUT].max_size = 64; dwc2->epin[0].ctl &= ~DIEPCTL0_MPSIZ_Msk;
xfer_status[0][TUSB_DIR_IN].max_size = 64; dwc2->epout[0].ctl &= ~DOEPCTL0_MPSIZ_Msk;
dwc2->epin[0].ctl |= mps << DIEPCTL0_MPSIZ_Pos;
dwc2->epout[0].ctl |= mps << DOEPCTL0_MPSIZ_Pos;
xfer_status[0][TUSB_DIR_OUT].max_size = CFG_TUD_ENDPOINT0_SIZE;
xfer_status[0][TUSB_DIR_IN].max_size = CFG_TUD_ENDPOINT0_SIZE;
if(dma_device_enabled(dwc2)) { if(dma_device_enabled(dwc2)) {
dma_setup_prepare(rhport); dma_setup_prepare(rhport);
@@ -830,6 +840,11 @@ static void handle_rxflvl_irq(uint8_t rhport) {
static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) {
if (doepint_bm.setup_phase_done) { if (doepint_bm.setup_phase_done) {
// Cleanup previous pending EP0 IN transfer if any
dwc2_dep_t* epin0 = &DWC2_REG(rhport)->epin[0];
if (epin0->diepctl & DIEPCTL_EPENA) {
edpt_disable(rhport, 0x80, false);
}
dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true); dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);
return; return;
} }
@@ -908,6 +923,11 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
dwc2_regs_t* dwc2 = DWC2_REG(rhport); dwc2_regs_t* dwc2 = DWC2_REG(rhport);
if (doepint_bm.setup_phase_done) { if (doepint_bm.setup_phase_done) {
// Cleanup previous pending EP0 IN transfer if any
dwc2_dep_t* epin0 = &DWC2_REG(rhport)->epin[0];
if (epin0->diepctl & DIEPCTL_EPENA) {
edpt_disable(rhport, 0x80, false);
}
dma_setup_prepare(rhport); dma_setup_prepare(rhport);
dcd_dcache_invalidate(_dcd_usbbuf.setup_packet, 8); dcd_dcache_invalidate(_dcd_usbbuf.setup_packet, 8);
dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true); dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);

6
src/portable/synopsys/dwc2/dwc2_type.h
View File

@@ -1847,6 +1847,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth #define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth
/******************** Bit definition for DIEPCTL register ********************/ /******************** Bit definition for DIEPCTL register ********************/
#define DIEPCTL0_MPSIZ_Pos (0U)
#define DIEPCTL0_MPSIZ_Msk (0x3UL << DIEPCTL0_MPSIZ_Pos) // 0x00000003
#define DIEPCTL0_MPSIZ DIEPCTL0_MPSIZ_Msk // Maximum packet size(endpoint 0)
#define DIEPCTL_MPSIZ_Pos (0U) #define DIEPCTL_MPSIZ_Pos (0U)
#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF #define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF
#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size #define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size
@@ -2155,6 +2158,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define EPCTL_EPENA EPCTL_EPENA_Msk // Endpoint enable #define EPCTL_EPENA EPCTL_EPENA_Msk // Endpoint enable
/******************** Bit definition for DOEPCTL register ********************/ /******************** Bit definition for DOEPCTL register ********************/
#define DOEPCTL0_MPSIZ_Pos (0U)
#define DOEPCTL0_MPSIZ_Msk (0x3UL << DOEPCTL0_MPSIZ_Pos) // 0x00000003
#define DOEPCTL0_MPSIZ DOEPCTL0_MPSIZ_Msk // Maximum packet size(endpoint 0)
#define DOEPCTL_MPSIZ_Pos (0U) #define DOEPCTL_MPSIZ_Pos (0U)
#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF #define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF
#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk // Maximum packet size //Bit 1 #define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk // Maximum packet size //Bit 1

36
tools/gen_presets.py
View File

@@ -5,13 +5,20 @@ from pathlib import Path
def main(): def main():
board_list = [] board_list = []
board_list_esp = []
# Find all board.cmake files # Find all board.cmake files, exclude espressif
for root, dirs, files in os.walk("hw/bsp"): for root, dirs, files in os.walk("hw/bsp"):
for file in files: for file in files:
if file == "board.cmake": if file == "board.cmake" and "espressif" not in root:
board_list.append(os.path.basename(root)) board_list.append(os.path.basename(root))
# Find all espressif boards
for root, dirs, files in os.walk("hw/bsp/espressif"):
for file in files:
if file == "board.cmake":
board_list_esp.append(os.path.basename(root))
print('Generating presets for the following boards:') print('Generating presets for the following boards:')
print(board_list) print(board_list)
@@ -29,8 +36,17 @@ def main():
"cacheVariables": { "cacheVariables": {
"CMAKE_DEFAULT_BUILD_TYPE": "RelWithDebInfo", "CMAKE_DEFAULT_BUILD_TYPE": "RelWithDebInfo",
"BOARD": r"${presetName}" "BOARD": r"${presetName}"
}},
{"name": "default single config",
"hidden": True,
"description": r"Configure preset for the ${presetName} board",
"generator": "Ninja",
"binaryDir": r"${sourceDir}/build/${presetName}",
"cacheVariables": {
"BOARD": r"${presetName}"
}}] }}]
# Add non-espressif boards
presets['configurePresets'].extend( presets['configurePresets'].extend(
sorted( sorted(
[ [
@@ -43,6 +59,22 @@ def main():
) )
) )
# Add espressif boards with single config generator
presets['configurePresets'].extend(
sorted(
[
{
'name': board,
'inherits': 'default single config'
}
for board in board_list_esp
], key=lambda x: x['name']
)
)
# Combine all boards
board_list.extend(board_list_esp)
# Build presets # Build presets
# no inheritance since 'name' doesn't support macro expansion # no inheritance since 'name' doesn't support macro expansion
presets['buildPresets'] = sorted( presets['buildPresets'] = sorted(