diff --git a/.idea/debugServers/AT32F423VCT7.xml b/.idea/debugServers/AT32F423VCT7.xml
new file mode 100644
index 000000000..38b3d76ef
--- /dev/null
+++ b/.idea/debugServers/AT32F423VCT7.xml
@@ -0,0 +1,13 @@
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diff --git a/.idea/debugServers/ST_LINK.xml b/.idea/debugServers/ST_LINK.xml
new file mode 100644
index 000000000..7c21d3879
--- /dev/null
+++ b/.idea/debugServers/ST_LINK.xml
@@ -0,0 +1,13 @@
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diff --git a/.idea/debugServers/at32f403acgu7.xml b/.idea/debugServers/at32f403acgu7.xml
new file mode 100644
index 000000000..9df65140f
--- /dev/null
+++ b/.idea/debugServers/at32f403acgu7.xml
@@ -0,0 +1,13 @@
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diff --git a/.idea/debugServers/max32690.xml b/.idea/debugServers/max32690.xml
new file mode 100644
index 000000000..3551f591e
--- /dev/null
+++ b/.idea/debugServers/max32690.xml
@@ -0,0 +1,13 @@
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diff --git a/.idea/debugServers/s3.xml b/.idea/debugServers/s3.xml
new file mode 100644
index 000000000..a03abf744
--- /dev/null
+++ b/.idea/debugServers/s3.xml
@@ -0,0 +1,6 @@
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diff --git a/.idea/debugServers/wch_riscv.xml b/.idea/debugServers/wch_riscv.xml
new file mode 100644
index 000000000..2e147f1b6
--- /dev/null
+++ b/.idea/debugServers/wch_riscv.xml
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diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 1fb93da11..e35d3e6fe 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -168,8 +168,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t ui16) { return
TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t ui16) { return TU_U16_LOW(ui16); }
//------------- Bits -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set (uint32_t value, uint8_t pos) { return value | TU_BIT(pos); }
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_clear(uint32_t value, uint8_t pos) { return value & (~TU_BIT(pos)); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set (uint32_t value, uint8_t pos) { return value | TU_BIT(pos); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_clear(uint32_t value, uint8_t pos) { return value & (~TU_BIT(pos)); }
TU_ATTR_ALWAYS_INLINE static inline bool tu_bit_test (uint32_t value, uint8_t pos) { return (value & TU_BIT(pos)) ? true : false; }
//------------- Min -------------//
diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c
index d7d157149..5ff18ab94 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.c
+++ b/src/portable/synopsys/dwc2/dwc2_common.c
@@ -45,20 +45,26 @@
//
//--------------------------------------------------------------------
static void reset_core(dwc2_regs_t* dwc2) {
+ // The software must check that bit 31 in this register is set to 1 (AHB Master is Idle) before starting any operation
+ while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {
+ }
+
// load gsnpsid (it is not readable after reset is asserted)
- uint32_t gsnpsid = dwc2->gsnpsid;
+ const uint32_t gsnpsid = dwc2->gsnpsid;
// reset core
dwc2->grstctl |= GRSTCTL_CSRST;
if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
- // prior v4.20a CSRST is self-clearing
+ // prior v4.20a: CSRST is self-clearing and the core clears this bit after all the necessary logic is reset in
+ // the core, which can take several clocks, depending on the current state of the core. Once this bit has been
+ // cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay).
while (dwc2->grstctl & GRSTCTL_CSRST) {}
} else {
- // From v4.20a CSRST bit is write only, CSRT_DONE (w1c) is introduced for checking.
- // CSRST must also be explicitly cleared
+ // From v4.20a: CSRST bit is write only. The application must clear this bit after checking the bit 29 of this
+ // register i.e Core Soft Reset Done CSRT_DONE (w1c)
while (!(dwc2->grstctl & GRSTCTL_CSRST_DONE)) {}
- dwc2->grstctl = (dwc2->grstctl & ~GRSTCTL_CSRST) | GRSTCTL_CSRST_DONE;
+ dwc2->grstctl = (dwc2->grstctl & ~GRSTCTL_CSRST) | GRSTCTL_CSRST_DONE;
}
while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE