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sun7i: boot ok on fpga

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This commit is contained in:
Jerry Wang 2012-08-14 15:37:06 +08:00
parent 37fb3db9fd
commit 593d7d57fc
14 changed files with 562 additions and 563 deletions
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10
boot1/core/arm_board/arm_start.S
View File

@ -45,7 +45,7 @@
ldr pc,_undefined_instruction
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_software_interrupt: .word software_interrupt
_irq: .word irq_interrupt
#define INTC_REG_VCTR 0x1c20400
@ -60,13 +60,7 @@ irq_interrupt:
msr cpsr_c, #(ARMV7_FIQ_MASK | ARMV7_IRQ_MASK | ARMV7_SYSTEM_MODE) @; 切换到SYSTEM模式
stmfd sp!, {r0-r12, lr} @; 保存lr_usr和其它用到的寄存器
ldr r0, =INTC_REG_VCTR
ldr r1, [r0]
ldr r0, =eGon2_IRQVectorTable
add r1, r0, r1, lsl #1
ldr r0, [r1] @;/* arg of isr */
mov lr, pc
ldr pc, [r1, #4] @;/* r1保存函数参数，r1+4保存函数地址. r1传递给了r0，实际上用r0传递中断函数参数 */
bl gic_irq_handler
ldmfd sp!, {r0-r12, lr} @; 恢复SYSTEM模式寄存器
msr cpsr_c, #(ARMV7_FIQ_MASK | ARMV7_IRQ_MASK | ARMV7_IRQ_MODE) @; 切换到IRQ模式

12
boot1/core/config.lds
View File

@ -29,16 +29,22 @@ SECTIONS
{
*(EXCLUDE_FILE(standby/*.o drivers/iic/sw_iic.o).rodata)
}
.bss ALIGN(4):
{
_bss_start = .;
*(EXCLUDE_FILE(standby/*.o drivers/iic/sw_iic.o).bss)
_bss_end = .;
}
_bss_end = ( ADDR (.bss) + SIZEOF (.bss) );
.notes ALIGN(4):
{
*(.note.*)
}
_standby_start_lma = .;
_standby_start_lma = ( ADDR (.notes) + SIZEOF (.notes) );
.boot_standby_text 0x400 :
AT ( ADDR (.bss) + SIZEOF (.bss) )
AT ( ADDR (.notes) + SIZEOF (.notes) )
{
_standby_start = .;
standby/*.o(.text .data .rodata .bss)

415
boot1/core/drivers/intc/int_service_entry.c
View File

@ -36,7 +36,7 @@ extern __s32 timer1_int_func(void *arg);
typedef __s32 (* __int_func )(void* /*p_arg*/); /* isr function pointer */
static __s32 esIRQHandler_default( void * pArg );
static int esIRQHandler_default( void * pArg );
typedef struct
{
@ -45,105 +45,115 @@ typedef struct
}__int_func_t;
__int_func_t eGon2_IRQVectorTable[84] =
__int_func_t eGon2_IRQVectorTable[GIC_IRQ_NUM];
/*
************************************************************************************************************
*
* function
*
* 函数名称：
*
* 参数列表：
*
* 返回值 ：
*
* 说明 ：
*
*
************************************************************************************************************
*/
static void gic_distributor_init(void)
{
{ 0, esIRQHandler_default }, //index 0
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default }, //index 9
__u32 cpumask = 0x01010101;
__u32 gic_irqs;
__u32 i;
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default }, //index 19
GICD_CTLR = 0;
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, timer0_int_func }, //timer0 22
{ 0, timer1_int_func }, //timer1 23
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default }, //index 29
/* check GIC hardware configutation */
gic_irqs = ((GICD_TYPE & 0x1f) + 1) * 32;
if (gic_irqs > 1020)
{
gic_irqs = 1020;
}
else if (gic_irqs < GIC_IRQ_NUM)
{
eGon2_printf("GIC parameter config error, only support %d"
" irqs < %d(spec define)!!\n", gic_irqs, GIC_IRQ_NUM);
return ;
}
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default }, //index 39
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default }, //index 49
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default }, //index 59
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default }, //index 69
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default }, //index 79
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default },
{ 0, esIRQHandler_default } //index 83
};
/* set trigger type to be level-triggered, active low */
for (i=0; i<GIC_IRQ_NUM; i+=16)
{
GICD_ICFGR(i>>4) = 0;
}
/* set priority */
for (i=GIC_SRC_SPI(0); i<GIC_IRQ_NUM; i+=4)
{
GICD_SPI_PRIO((i-32)>>2) = 0xa0a0a0a0;
}
/* set processor target */
for (i=32; i<GIC_IRQ_NUM; i+=4)
{
GICD_SPI_ITARG((i-32)>>2) = cpumask;
}
/* disable all interrupts */
for (i=32; i<GIC_IRQ_NUM; i+=32)
{
GICD_ICENABLER(i>>5) = 0xffffffff;
}
/* clear all interrupt active state */
for (i=32; i<GIC_IRQ_NUM; i+=32)
{
GICD_ICACTIVER(i>>5) = 0xffffffff;
}
GICD_CTLR = 1;
return ;
}
/*
************************************************************************************************************
*
* function
*
* 函数名称：
*
* 参数列表：
*
* 返回值 ：
*
* 说明 ：
*
*
************************************************************************************************************
*/
static void gic_cpuif_init(void)
{
__u32 i;
GICC_CTRL = 0;
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
GICD_ICENABLER(0) = 0xffff0000;
GICD_ISENABLER(0) = 0x0000ffff;
/* Set priority on PPI and SGI interrupts */
for (i=0; i<16; i+=4)
{
GICD_SGI_PRIO(i>>2) = 0xa0a0a0a0;
}
for (i=16; i<32; i+=4)
{
GICD_PPI_PRIO((i-16)>>2) = 0xa0a0a0a0;
}
GICC_PMR = 0xf0;
GICC_CTRL = 1;
return ;
}
/*
*********************************************************************************************************
* IRQHandler_default
@ -154,10 +164,12 @@ __int_func_t eGon2_IRQVectorTable[84] =
* Returns : void
*********************************************************************************************************
*/
static __s32 esIRQHandler_default(void * pArg)
static int esIRQHandler_default(void * pArg)
{
eGon2_printf("int not support\n");
while(1);
return 0;
}
/*
@ -172,22 +184,17 @@ static __s32 esIRQHandler_default(void * pArg)
*/
void eGon2_Int_Init(void)
{
//关闭所有中断使能
INTC_REG_ENABLE0 = 0;
INTC_REG_ENABLE1 = 0;
INTC_REG_ENABLE2 = 0;
//打开所有中断mask
INTC_REG_MASK0 = 0;
INTC_REG_MASK1 = 0;
INTC_REG_MASK2 = 0;
//清除所有中断pengding
INTC_REG_FIQ_PENDCLR0 = 0xffffffff;
INTC_REG_FIQ_PENDCLR1 = 0xffffffff;
INTC_REG_FIQ_PENDCLR2 = 0xffffffff;
int i;
INTC_REG_IRQ_PENDCLR0 = 0xffffffff;
INTC_REG_IRQ_PENDCLR1 = 0xffffffff;
INTC_REG_IRQ_PENDCLR2 = 0xffffffff;
for (i=0; i<GIC_IRQ_NUM; i++)
{
eGon2_IRQVectorTable[i].pIsr = esIRQHandler_default;
}
eGon2_IRQVectorTable[GIC_SRC_TIMER0].pIsr = timer0_int_func;
eGon2_IRQVectorTable[GIC_SRC_TIMER1].pIsr = timer1_int_func;
gic_distributor_init();
gic_cpuif_init();
return;
}
@ -203,32 +210,6 @@ void eGon2_Int_Init(void)
*/
void eGon2_Int_Exit(void)
{
//关闭TIMER中断
*(volatile unsigned int *)(0x01c20c00 + 0x00) = 0;
*(volatile unsigned int *)(0x01c20c00 + 0x04) |= 0x043f;
*(volatile unsigned int *)(0x01c20c00 + 0x10) = 0;
*(volatile unsigned int *)(0x01c20c00 + 0x20) = 0;
//关闭DMA中断
*(volatile unsigned int *)(0x01c02000 + 0x00) = 0;
*(volatile unsigned int *)(0x01c02000 + 0x04) = 0xffffffff;
//关闭所有中断使能
INTC_REG_ENABLE0 = 0;
INTC_REG_ENABLE1 = 0;
INTC_REG_ENABLE2 = 0;
//打开所有中断mask
INTC_REG_MASK0 = 0;
INTC_REG_MASK1 = 0;
INTC_REG_MASK2 = 0;
//清除所有中断pengding
INTC_REG_FIQ_PENDCLR0 = 0xffffffff;
INTC_REG_FIQ_PENDCLR1 = 0xffffffff;
INTC_REG_FIQ_PENDCLR2 = 0xffffffff;
INTC_REG_IRQ_PENDCLR0 = 0xffffffff;
INTC_REG_IRQ_PENDCLR1 = 0xffffffff;
INTC_REG_IRQ_PENDCLR2 = 0xffffffff;
return;
}
/*
@ -246,17 +227,14 @@ void eGon2_Int_Exit(void)
__s32 eGon2_InsINT_Func(__u32 irq_no, int *func_addr, void *p_arg)
{
close_sys_int();
if(irq_no < 80)
if (irq_no < GIC_IRQ_NUM)
{
if(eGon2_IRQVectorTable[irq_no].pIsr == esIRQHandler_default) //还没有进行注册
{
eGon2_IRQVectorTable[irq_no].pIsr = (__int_func )func_addr;
eGon2_IRQVectorTable[irq_no].pArg = p_arg;
open_sys_int();
eGon2_IRQVectorTable[irq_no].pIsr = (__int_func )func_addr;
eGon2_IRQVectorTable[irq_no].pArg = p_arg;
open_sys_int();
return 0;
}
}
return 0;
}
open_sys_int();
return -1;
@ -278,17 +256,17 @@ __s32 eGon2_InsINT_Func(__u32 irq_no, int *func_addr, void *p_arg)
__s32 eGon2_UnsInt_Func(__u32 irq_no)
{
close_sys_int();
if(irq_no < 80)
if(irq_no < GIC_IRQ_NUM)
{
if(eGon2_IRQVectorTable[irq_no].pIsr != esIRQHandler_default) //还没有进行注册
{
eGon2_IRQVectorTable[irq_no].pIsr = esIRQHandler_default;
eGon2_IRQVectorTable[irq_no].pArg = 0;
open_sys_int();
if(eGon2_IRQVectorTable[irq_no].pIsr != esIRQHandler_default)
{
eGon2_IRQVectorTable[irq_no].pIsr = (__int_func )esIRQHandler_default;
eGon2_IRQVectorTable[irq_no].pArg = 0;
open_sys_int();
}
return 0;
}
}
return 0;
}
open_sys_int();
return -1;
@ -307,25 +285,19 @@ __s32 eGon2_UnsInt_Func(__u32 irq_no)
*/
__s32 eGon2_EnableInt(__u32 irq_no)
{
if(irq_no < 32)
{
INTC_REG_ENABLE0 |= (1 << irq_no);
INTC_REG_MASK0 &= ~(1 << irq_no);
if(irq_no == INTC_IRQNO_FIQ) /* must clear pending bit when enabled */
INTC_REG_FIQ_PENDCLR0 = (1 << INTC_IRQNO_FIQ);
}
else if(irq_no < 64)
{
irq_no -= 32;
INTC_REG_ENABLE1 |= (1 << irq_no);
INTC_REG_MASK1 &= ~(1 << irq_no);
}
else
{
irq_no -= 64;
INTC_REG_ENABLE2 |= (1 << irq_no);
INTC_REG_MASK2 &= ~(1 << irq_no);
}
__u32 reg_val;
__u32 offset;
if (irq_no >= GIC_IRQ_NUM)
{
eGon2_printf("irq NO.(%d) > GIC_IRQ_NUM(%d) !!\n", irq_no, GIC_IRQ_NUM);
return -1;
}
offset = irq_no >> 5; // 除32
reg_val = GICD_ISENABLER(offset);
reg_val |= 1 << (irq_no & 0x1f);
GICD_ISENABLER(offset) = reg_val;
return 0;
}
@ -344,25 +316,92 @@ __s32 eGon2_EnableInt(__u32 irq_no)
*/
__s32 eGon2_DisableInt(__u32 irq_no)
{
if(irq_no < 32)
{
INTC_REG_ENABLE0 &= ~(1 << irq_no);
INTC_REG_MASK0 |= (1 << irq_no);
}
else if(irq_no < 64)
{
irq_no -= 32;
INTC_REG_ENABLE1 &= ~(1 << irq_no);
INTC_REG_MASK1 |= (1 << irq_no);
}
else
{
irq_no -= 64;
INTC_REG_ENABLE2 &= ~(1 << irq_no);
INTC_REG_MASK2 |= (1 << irq_no);
}
__u32 reg_val;
__u32 offset;
if (irq_no >= GIC_IRQ_NUM)
{
eGon2_printf("irq NO.(%d) > GIC_IRQ_NUM(%d) !!\n", irq_no, GIC_IRQ_NUM);
return -1;
}
offset = irq_no >> 5; // 除32
reg_val = GICD_ISENABLER(offset);
reg_val &= ~(1 << (irq_no & 0x1f));
GICD_ISENABLER(offset) = reg_val;
return 0;
}
void gic_sgi_handler(__u32 id)
{
eGon2_printf("SGI irq %d coming... \n", id);
}
void gic_ppi_handler(__u32 id)
{
eGon2_printf("PPI irq %d coming... \n", id);
}
void gic_spi_handler(__u32 id)
{
if(eGon2_IRQVectorTable[id].pIsr != (__int_func )esIRQHandler_default)
{
eGon2_IRQVectorTable[id].pIsr(eGon2_IRQVectorTable[id].pArg);
}
return ;
}
void gic_clear_pending(u32 idnum)
{
__u32 reg_val;
__u32 offset;
offset = idnum >> 5; // 除32
reg_val = GICD_ICPENDR(offset);
reg_val |= (1 << (idnum & 0x1f));
GICD_ICPENDR(offset) = reg_val;
return ;
}
void gic_irq_handler(void)
{
u32 idnum;
idnum = GICC_IAR;
if (idnum == 1023)
{
eGon2_printf("spurious irq !!\n");
return;
}
if (idnum >= GIC_IRQ_NUM)
{
eGon2_printf("irq NO.(%d) > GIC_IRQ_NUM(%d) !!\n", idnum, GIC_IRQ_NUM-32);
return;
}
if (idnum < 16)
{
gic_sgi_handler(idnum);
}
else if (idnum < 32)
{
gic_ppi_handler(idnum);
}
else
{
gic_spi_handler(idnum);
}
GICC_EOIR = idnum;
GICC_DIR = idnum;
gic_clear_pending(idnum);
return ;
}

35
boot1/core/drivers/timer/sw_timer.c
View File

@ -122,8 +122,8 @@ __s32 eGon2_timer_start(__u32 hd, __s32 delay_time, __s32 auto_restart)
reg_val = (0 << 0) | // 不启动TIMER
(0 << 1) | // 使用单次模式
(1 << 2) | // 使用高频晶振24M
(5 << 4); // 除频系统32，保证当设置时间是1的时候，触发延时1ms
(0 << 2) | // 使用32K，仅限FPGA
(0 << 4); // 仅限FPGA，设置除频率系数为5
reg_val |= (0 << 0) | // 暂时没有start timer
(1 << 1); // 自动更新初始值用于计时
@ -143,18 +143,18 @@ __s32 eGon2_timer_start(__u32 hd, __s32 delay_time, __s32 auto_restart)
delay_time = SW_TIMER_MAX_TICK;
}
tmp->timer_ctl->init_val = delay_time * (24000 / 32); //确保用户输入的数值1就可以代表1ms
tmp->timer_ctl->init_val = delay_time * (32 / 1); //确保用户输入的数值1就可以代表1ms
tmp->timer_ctl->control = reg_val;
CFG_SW_TIMER_INT_CTRL |= (1 << tmp->index); //开启中断
//这里开启中断
if(tmp->index == 0)
{
eGon2_EnableInt(INTC_IRQNO_TIMER0);
eGon2_EnableInt(GIC_SRC_TIMER0);
}
else
{
eGon2_EnableInt(INTC_IRQNO_TIMER1);
eGon2_EnableInt(GIC_SRC_TIMER1);
}
tmp->timer_ctl->control |= 1; //启动timer
@ -195,12 +195,12 @@ __s32 eGon2_timer_stop(__u32 hd)
if(tmp->index == 0)
{
CFG_SW_TIMER_INT_STATS |= 0x01;
eGon2_DisableInt(INTC_IRQNO_TIMER0);
eGon2_DisableInt(GIC_SRC_TIMER0);
}
else
{
CFG_SW_TIMER_INT_STATS |= 0x02;
eGon2_DisableInt(INTC_IRQNO_TIMER1);
eGon2_DisableInt(GIC_SRC_TIMER1);
}
CFG_SW_TIMER_INT_CTRL &= ~(1 << tmp->index); //关闭中断
@ -241,11 +241,11 @@ __s32 eGon2_timer_release(__u32 hd)
CFG_SW_TIMER_INT_CTRL &= ~(1 << tmp->index); //关闭中断
if(tmp->index == 0)
{
eGon2_DisableInt(INTC_IRQNO_TIMER0);
eGon2_DisableInt(GIC_SRC_TIMER0);
}
else
{
eGon2_DisableInt(INTC_IRQNO_TIMER1);
eGon2_DisableInt(GIC_SRC_TIMER1);
}
tmp->used = 0;
@ -278,12 +278,12 @@ __s32 timer0_int_func(void *arg)
return 0;
}
CFG_SW_TIMER_INT_STATS |= 0x01;
eGon2_DisableInt(INTC_IRQNO_TIMER0);
eGon2_DisableInt(GIC_SRC_TIMER0);
timer_int_func[0](timer_port[0].arg);
if(timer_port[0].restart)
{
eGon2_EnableInt(INTC_IRQNO_TIMER0);
eGon2_EnableInt(GIC_SRC_TIMER0);
}
return 0;
@ -313,11 +313,11 @@ __s32 timer1_int_func(void *arg)
return 0;
}
CFG_SW_TIMER_INT_STATS |= 0x02;
eGon2_DisableInt(INTC_IRQNO_TIMER1);
eGon2_DisableInt(GIC_SRC_TIMER1);
timer_int_func[1](timer_port[1].arg);
if(timer_port[1].restart)
{
eGon2_EnableInt(INTC_IRQNO_TIMER1);
eGon2_EnableInt(GIC_SRC_TIMER1);
}
return 0;
@ -386,10 +386,11 @@ void eGon2_watchdog_enable(void)
*/
void eGon2_timer_init(void)
{
// *(volatile unsigned int *)(0x01c20000 + 0x144) |= (1U << 31);
// *(volatile unsigned int *)(0x01c20C00 + 0x80 ) = 1;
// *(volatile unsigned int *)(0x01c20C00 + 0x8C ) = 0x0C;
// *(volatile unsigned int *)(0x01c20C00 + 0x84 ) = 0;
*(volatile unsigned int *)(0x01c20000 + 0x144) |= (1U << 31);
*(volatile unsigned int *)(0x01c20C00 + 0x80 ) = 1;
*(volatile unsigned int *)(0x01c20C00 + 0x8C ) = 0x0C;
*(volatile unsigned int *)(0x01c20C00 + 0x84 ) = 0;
CFG_SW_TIMER_INT_STATS |= 0x03;
}
/*
************************************************************************************************************

3
boot1/core/parameters/parameters.c
View File

@ -52,7 +52,8 @@ __s32 eGon2_dispatch_parameters(__u32 para_name, void *para_addr)
boot_nand_para_t *nand_info = (boot_nand_para_t *)BT1_head.prvt_head.storage_data;
memset( p, 0, sizeof(boot_nand_para_t) );
p->good_block_ratio = nand_info->good_block_ratio;
// p->good_block_ratio = nand_info->good_block_ratio;
p->good_block_ratio = 960;
}
break;

70
boot1/core/standby/int_standby.c
View File

@ -51,27 +51,11 @@ int standby_int_init(void)
asm("msr cpsr_c, r0");
//保存中断寄存器值
addr = (int *)(0x01c20400);
for(i=1;i<36;i++)
{
int_reggroup_value[i] = *(addr + i);
}
//关闭所有中断使能,仅保留POWER中断
INTC_REG_ENABLE0 = 1;
INTC_REG_ENABLE1 = 0;
INTC_REG_ENABLE2 = 0;
//打开所有中断mask
INTC_REG_MASK0 = 0;
INTC_REG_MASK1 = 0;
INTC_REG_MASK2 = 0;
//清除所有中断pengding
INTC_REG_FIQ_PENDCLR0 = 0xffffffff;
INTC_REG_FIQ_PENDCLR1 = 0xffffffff;
INTC_REG_FIQ_PENDCLR2 = 0xffffffff;
INTC_REG_IRQ_PENDCLR0 = 0xffffffff;
INTC_REG_IRQ_PENDCLR1 = 0xffffffff;
INTC_REG_IRQ_PENDCLR2 = 0xffffffff;
// addr = (int *)(0x01c20400);
// for(i=1;i<36;i++)
// {
// int_reggroup_value[i] = *(addr + i);
// }
return 0;
}
@ -97,19 +81,19 @@ int standby_int_init(void)
*/
int standby_int_exit(void)
{
int i;
int *addr;
//保存中断寄存器值
addr = (int *)(0x01c20400);
if(!int_reggroup_value)
{
return -1;
}
for(i=1;i<36;i++)
{
*(addr + i) = int_reggroup_value[i];
}
// int i;
// int *addr;
//
// //保存中断寄存器值
// addr = (int *)(0x01c20400);
// if(!int_reggroup_value)
// {
// return -1;
// }
// for(i=1;i<36;i++)
// {
// *(addr + i) = int_reggroup_value[i];
// }
asm("mrs r0, cpsr");
asm("bic r0, r0, #(0x40|0x80)");
@ -121,15 +105,15 @@ int standby_int_exit(void)
int standby_int_query(void)
{
__u32 reg_val;
reg_val = INTC_REG_IRQ_PENDCLR0;
if(reg_val & 1)
{
INTC_REG_IRQ_PENDCLR0 = reg_val;
return 1;
}
// __u32 reg_val;
//
// reg_val = INTC_REG_IRQ_PENDCLR0;
// if(reg_val & 1)
// {
// INTC_REG_IRQ_PENDCLR0 = reg_val;
//
// return 1;
// }
return 0;
}

1
boot1/core/start/asm_start.S
View File

@ -89,4 +89,3 @@ eGon2_init:
b . @;// infinite loop

3
boot1/core/start/basic_block_device.c
View File

@ -111,7 +111,8 @@ __s32 eGon2_block_phywrite(__u32 start_block, __u32 nblock, void *pbuffer)
__s32 eGon2_block_size(void)
{
return NAND_GetDiskSize();
//return NAND_GetDiskSize();
return 0;
}
void eGon2_block_ratio(void)

2
boot1/core/start/eGon2_start.c
View File

@ -47,7 +47,7 @@ void eGon2_start( void )
/* init enviroment for running app */
// move_RW( );
reposition_boot_standby();
// reposition_boot_standby();
clear_ZI( );
// 做两次调频，第一次先到384M ???

2
boot1/driver/drv_nand/osal-boot/nand_osal_boot1.c
View File

@ -470,7 +470,7 @@ void *NAND_IORemap(unsigned int base_addr, unsigned int size)
*/
int NAND_Print(const char * str, ...)
{
//wlibc_uprintf(str);
wlibc_uprintf(str);
return 0;
}

141
boot1/include/arch/dmac.h
View File

@ -51,147 +51,6 @@
#define DMA_D2 2
#define DMA_D3 3
#define DMA_OFFSET 0x20
#define DMA_HDLER_TYPE_CNT 2
#define DMA_TRANSFER_HALF_INT 0
#define DMA_TRANSFER_END_INT 1
#define DMA_TRANSFER_UNLOOP_MODE 0
#define DMA_TRANSFER_LOOP_MODE 1
//================================
//====== DMA 配置 =========
//================================
/* DMA 基础配置 */
#define DMAC_CFG_CONTINUOUS_ENABLE (0x01) //(0x01<<29)
#define DMAC_CFG_CONTINUOUS_DISABLE (0x00) //(0x01<<29)
//* DMA 时钟 */
#define DMAC_CFG_WAIT_1_DMA_CLOCK (0x00) //(0x00<<26)
#define DMAC_CFG_WAIT_2_DMA_CLOCK (0x01) //(0x01<<26)
#define DMAC_CFG_WAIT_3_DMA_CLOCK (0x02) //(0x02<<26)
#define DMAC_CFG_WAIT_4_DMA_CLOCK (0x03) //(0x03<<26)
#define DMAC_CFG_WAIT_5_DMA_CLOCK (0x04) //(0x04<<26)
#define DMAC_CFG_WAIT_6_DMA_CLOCK (0x05) //(0x05<<26)
#define DMAC_CFG_WAIT_7_DMA_CLOCK (0x06) //(0x06<<26)
#define DMAC_CFG_WAIT_8_DMA_CLOCK (0x07) //(0x07<<26)
/* DMA 传输目的端 配置 */
/* DMA 目的端 传输宽度 */
#define DMAC_CFG_DEST_DATA_WIDTH_8BIT (0x00) //(0x00<<24)
#define DMAC_CFG_DEST_DATA_WIDTH_16BIT (0x01) //(0x01<<24)
#define DMAC_CFG_DEST_DATA_WIDTH_32BIT (0x02) //(0x02<<24)
/* DMA 目的端 突发传输模式 */
#define DMAC_CFG_DEST_1_BURST (0x00) //(0x00<<23)
#define DMAC_CFG_DEST_4_BURST (0x01) //(0x01<<23)
/* DMA 目的端 地址变化模式 */
#define DMAC_CFG_DEST_ADDR_TYPE_LINEAR_MODE (0x00) //(0x00<<21)
#define DMAC_CFG_DEST_ADDR_TYPE_IO_MODE (0x01) //(0x01<<21)
#define DMAC_CFG_DEST_ADDR_TYPE_HPAGE_MODE (0x02) //(0x02<<21)
#define DMAC_CFG_DEST_ADDR_TYPE_VPAGE_MODE (0x03) //(0x03<<21)
/* DMA 传输源端 配置 */
/* DMA 源端 传输宽度 */
#define DMAC_CFG_SRC_DATA_WIDTH_8BIT (0x00) //(0x00<<8)
#define DMAC_CFG_SRC_DATA_WIDTH_16BIT (0x01) //(0x01<<8)
#define DMAC_CFG_SRC_DATA_WIDTH_32BIT (0x02) //(0x02<<8)
/* DMA 源端 突发传输模式 */
#define DMAC_CFG_SRC_1_BURST (0x00) //(0x00<<7)
#define DMAC_CFG_SRC_4_BURST (0x01) //(0x01<<7)
/* DMA 源端 地址变化模式 */
#define DMAC_CFG_SRC_ADDR_TYPE_LINEAR_MODE (0x00) //(0x00<<5)
#define DMAC_CFG_SRC_ADDR_TYPE_IO_MODE (0x01) //(0x01<<5)
#define DMAC_CFG_SRC_ADDR_TYPE_HPAGE_MODE (0x02) //(0x02<<5)
#define DMAC_CFG_SRC_ADDR_TYPE_VPAGE_MODE (0x03) //(0x03<<5)
/* DMA 传输目的端 配置 */
/* DMA 传输目的端 N型DMA 目的选择 */
#define DMAC_CFG_DEST_TYPE_IR (0x00) //(0x00<<16)
#define DMAC_CFG_DEST_TYPE_SPDIF (0x01) //(0x01<<16)
#define DMAC_CFG_DEST_TYPE_IIS (0x02) //(0x02<<16)
#define DMAC_CFG_DEST_TYPE_AC97 (0x03) //(0x03<<16)
#define DMAC_CFG_DEST_TYPE_SPI0 (0x04) //(0x04<<16)
#define DMAC_CFG_DEST_TYPE_SPI1 (0x05) //(0x05<<16)
#define DMAC_CFG_DEST_TYPE_SPI2 (0x06) //(0x06<<16)
#define DMAC_CFG_DEST_TYPE_UART0 (0x08) //(0x08<<16)
#define DMAC_CFG_DEST_TYPE_UART1 (0x09) //(0x09<<16)
#define DMAC_CFG_DEST_TYPE_UART2 (0x0a) //(0x0a<<16)
#define DMAC_CFG_DEST_TYPE_UART3 (0x0b) //(0x0b<<16)
#define DMAC_CFG_DEST_TYPE_AUDIO_DA (0x0c) //(0x0c<<16)
#define DMAC_CFG_DEST_TYPE_NFC_DEBUG (0x0f) //(0x0f<<16)
#define DMAC_CFG_DEST_TYPE_N_SRAM (0x10) //(0x10<<16)
#define DMAC_CFG_DEST_TYPE_N_SDRAM (0x11) //(0x11<<16)
#define DMAC_CFG_DEST_TYPE_UART4 (0x12) //(0x12<<16)
#define DMAC_CFG_DEST_TYPE_UART5 (0x13) //(0x13<<16)
#define DMAC_CFG_DEST_TYPE_UART6 (0x14) //(0x14<<16)
#define DMAC_CFG_DEST_TYPE_UART7 (0x15) //(0x15<<16)
/* DMA 传输目的端 D型DMA 目的选择 */
#define DMAC_CFG_DEST_TYPE_D_SRAM (0x00) //(0x00<<16)
#define DMAC_CFG_DEST_TYPE_D_SDRAM (0x01) //(0x01<<16)
#define DMAC_CFG_DEST_TYPE_TCON0 (0x02) //(0x02<<16)
#define DMAC_CFG_DEST_TYPE_NFC (0x03) //(0x03<<16)
#define DMAC_CFG_DEST_TYPE_USB0 (0x04) //(0x04<<16)
#define DMAC_CFG_DEST_TYPE_USB1 (0x05) //(0x05<<16)
#define DMAC_CFG_DEST_TYPE_SDC1 (0x07) //(0x07<<16)
#define DMAC_CFG_DEST_TYPE_SDC2 (0x08) //(0x08<<16)
#define DMAC_CFG_DEST_TYPE_SDC3 (0x09) //(0x09<<16)
#define DMAC_CFG_DEST_TYPE_MSC (0x0a) //(0x0a<<16)
#define DMAC_CFG_DEST_TYPE_EMAC (0x0b) //(0x0b<<16)
#define DMAC_CFG_DEST_TYPE_SS (0x0d) //(0x0d<<16)
#define DMAC_CFG_DEST_TYPE_USB2 (0x0f) //(0x0f<<16)
#define DMAC_CFG_DEST_TYPE_ATA (0x10) //(0x10<<16)
/* DMA 传输源端 配置 */
/* DMA 传输源端 N型DMA 目的选择 */
#define DMAC_CFG_SRC_TYPE_IR (0x00) //(0x00<<0)
#define DMAC_CFG_SRC_TYPE_SPDIF (0x01) //(0x01<<0)
#define DMAC_CFG_SRC_TYPE_IIS (0x02) //(0x02<<0)
#define DMAC_CFG_SRC_TYPE_AC97 (0x03) //(0x03<<0)
#define DMAC_CFG_SRC_TYPE_SPI0 (0x04) //(0x04<<0)
#define DMAC_CFG_SRC_TYPE_SPI1 (0x05) //(0x05<<0)
#define DMAC_CFG_SRC_TYPE_SPI2 (0x06) //(0x06<<0)
#define DMAC_CFG_SRC_TYPE_UART0 (0x08) //(0x08<<0)
#define DMAC_CFG_SRC_TYPE_UART1 (0x09) //(0x09<<0)
#define DMAC_CFG_SRC_TYPE_UART2 (0x0a) //(0x0a<<0)
#define DMAC_CFG_SRC_TYPE_UART3 (0x0b) //(0x0b<<0)
#define DMAC_CFG_SRC_TYPE_AUDIO (0x0c) //(0x0c<<0)
#define DMAC_CFG_SRC_TYPE_TP (0x0d) //(0x0d<<0)
#define DMAC_CFG_SRC_TYPE_NFC_DEBUG (0x0f) //(0x0f<<0)
#define DMAC_CFG_SRC_TYPE_N_SRAM (0x10) //(0x10<<0)
#define DMAC_CFG_SRC_TYPE_N_SDRAM (0x11) //(0x11<<0)
#define DMAC_CFG_SRC_TYPE_UART4 (0x12) //(0x12<<0)
#define DMAC_CFG_SRC_TYPE_UART5 (0x13) //(0x13<<0)
#define DMAC_CFG_SRC_TYPE_UART6 (0x14) //(0x14<<0)
#define DMAC_CFG_SRC_TYPE_UART7 (0x15) //(0x15<<0)
/* DMA 传输源端 D型DMA 目的选择 */
#define DMAC_CFG_SRC_TYPE_D_SRAM (0x00) //(0x00<<0)
#define DMAC_CFG_SRC_TYPE_D_SDRAM (0x01) //(0x01<<0)
#define DMAC_CFG_SRC_TYPE_TCON0 (0x02) //(0x02<<0)
#define DMAC_CFG_SRC_TYPE_NFC (0x03) //(0x03<<0)
#define DMAC_CFG_SRC_TYPE_USB0 (0x04) //(0x04<<0)
#define DMAC_CFG_SRC_TYPE_USB1 (0x05) //(0x05<<0)
#define DMAC_CFG_SRC_TYPE_SDC1 (0x07) //(0x07<<0)
#define DMAC_CFG_SRC_TYPE_SDC2 (0x08) //(0x08<<0)
#define DMAC_CFG_SRC_TYPE_SDC3 (0x09) //(0x09<<0)
#define DMAC_CFG_SRC_TYPE_MSC (0x0a) //(0x0a<<0)
#define DMAC_CFG_SRC_TYPE_EMAC (0x0c) //(0x0c<<0)
#define DMAC_CFG_SRC_TYPE_SS (0x0e) //(0x0e<<0)
#define DMAC_CFG_SRC_TYPE_USB2 (0x0f) //(0x0f<<0)
#define DMAC_CFG_SRC_TYPE_ATA (0x10) //(0x10<<0)
/* offset */
#define DMAC_REG_o_IRQ_EN 0x00
#define DMAC_REG_o_IRQ_PENDING 0x04

4
boot1/include/arch/hd_scrpt.h
View File

@ -113,6 +113,10 @@
#define TWIC1_REGS_BASE ( REGS_BASE + 0x2B000 ) //twi1
#define TWIC2_REGS_BASE ( REGS_BASE + 0x2B400 ) //twi2
#define ARMV7_SCU_BASE (0x01c80000)
#define ARMV7_GIC_BASE (0x01c81000)
#define ARMV7_CPUIF_BASE (0x01c82000)
#define ARMV7_CPUBIST_BASE (0x01c88000)
#endif // end of #ifndef __SUNII_H_

427
boot1/include/arch/intc.h
View File

@ -23,182 +23,293 @@
* Interrupt controller define
*********************************************************************************************************
*/
#define bINT_CTL(Nb) __REG(INTC_REGS_BASE + (Nb))
/* Offset */
;/* Offset */
#define INTC_REG_o_VCTR 0x00
#define INTC_REG_o_VTBLBADDR 0x04
/* GIC registers */
#define GICD_CTLR __REG(ARMV7_GIC_BASE + 0x0000)
#define GICD_TYPE __REG(ARMV7_GIC_BASE + 0x0004)
#define GICD_IIDR __REG(ARMV7_GIC_BASE + 0x0008)
#define INTC_REG_o_NMI_CTRL 0x0C
#define GICD_IGROUPR __REG(ARMV7_GIC_BASE + 0x0080)
#define INTC_REG_o_IRQ_PENDCLR0 0x10
#define INTC_REG_o_IRQ_PENDCLR1 0x14
#define INTC_REG_o_IRQ_PENDCLR2 0x18
#define GICD_ISENABLER(n) __REG(ARMV7_GIC_BASE + 0x100 + 4 * (n))
#define GICD_ICENABLER(n) __REG(ARMV7_GIC_BASE + 0x180 + 4 * (n))
#define INTC_REG_o_FIQ_PENDCLR0 0x20
#define INTC_REG_o_FIQ_PENDCLR1 0x24
#define INTC_REG_o_FIQ_PENDCLR2 0x28
#define GICD_ISPENDR(n) __REG(ARMV7_GIC_BASE + 0x200 + 4 * (n))
#define GICD_ICPENDR(n) __REG(ARMV7_GIC_BASE + 0x280 + 4 * (n))
#define INTC_REG_o_IRQ_SEL0 0x30
#define INTC_REG_o_IRQ_SEL1 0x34
#define INTC_REG_o_IRQ_SEL2 0x38
#define GICD_ISACTIVER(n) __REG(ARMV7_GIC_BASE + 0x300 + 4 * (n))
#define GICD_ICACTIVER(n) __REG(ARMV7_GIC_BASE + 0x380 + 4 * (n))
#define INTC_REG_o_ENABLE0 0x40
#define INTC_REG_o_ENABLE1 0x44
#define INTC_REG_o_ENABLE2 0x48
#define GICD_SGI_PRIO(n) __REG(ARMV7_GIC_BASE + 0x400 + 4 * (n))
#define GICD_PPI_PRIO(n) __REG(ARMV7_GIC_BASE + 0x410 + 4 * (n))
#define GICD_SPI_PRIO(n) __REG(ARMV7_GIC_BASE + 0x420 + 4 * (n))
#define INTC_REG_o_MASK0 0x50
#define INTC_REG_o_MASK1 0x54
#define INTC_REG_o_MASK2 0x58
#define GICD_SGI_ITARG(n) __REG(ARMV7_GIC_BASE + 0x800 + 4 * (n))
#define GICD_PPI_ITARG(n) __REG(ARMV7_GIC_BASE + 0x810 + 4 * (n))
#define GICD_SPI_ITARG(n) __REG(ARMV7_GIC_BASE + 0x820 + 4 * (n))
#define INTC_REG_o_RESP0 0x60
#define INTC_REG_o_RSEP1 0x64
#define INTC_REG_o_RESP2 0x68
#define GICD_ICFGR(n) __REG(ARMV7_GIC_BASE + 0xc00 + 4 * (n))
#define INTC_REG_o_FF0 0x70
#define INTC_REG_o_FF1 0x74
#define INTC_REG_o_FF2 0x78
#define GICD_SGIR __REG(ARMV7_GIC_BASE + 0xf00) // 0xf00
#define INTC_REG_o_PRIO0 0x80
#define INTC_REG_o_PRIO1 0x84
#define INTC_REG_o_PRIO2 0x88
#define INTC_REG_o_PRIO3 0x8C
#define INTC_REG_o_PRIO4 0x90
#define GICC_CTRL __REG(ARMV7_CPUIF_BASE + 0x000) // 0x8000
#define GICC_PMR __REG(ARMV7_CPUIF_BASE + 0x004) // 0x8004
#define GICC_BPR __REG(ARMV7_CPUIF_BASE + 0x008) // 0x8008
#define GICC_IAR __REG(ARMV7_CPUIF_BASE + 0x00c) // 0x800c
#define GICC_EOIR __REG(ARMV7_CPUIF_BASE + 0x010) // 0x8010
#define GICC_RPR __REG(ARMV7_CPUIF_BASE + 0x014) // 0x8014
#define GICC_HPPIR __REG(ARMV7_CPUIF_BASE + 0x018) // 0x8018
#define GICC_DIR __REG(ARMV7_CPUIF_BASE + 0x1000)// 0x1000
/* registers */
#define INTC_REG_VCTR bINT_CTL( INTC_REG_o_VCTR )
#define INTC_REG_VTBLBADDR bINT_CTL( INTC_REG_o_VTBLBADDR )
/* gic source list */
/* software generated interrupt */
#define GIC_SRC_SGI(_n) (_n)
#define GIC_SRC_SGI0 GIC_SRC_SGI(0 ) // (0 )
#define GIC_SRC_SGI1 GIC_SRC_SGI(1 ) // (1 )
#define GIC_SRC_SGI2 GIC_SRC_SGI(2 ) // (2 )
#define GIC_SRC_SGI3 GIC_SRC_SGI(3 ) // (3 )
#define GIC_SRC_SGI4 GIC_SRC_SGI(4 ) // (4 )
#define GIC_SRC_SGI5 GIC_SRC_SGI(5 ) // (5 )
#define GIC_SRC_SGI6 GIC_SRC_SGI(6 ) // (6 )
#define GIC_SRC_SGI7 GIC_SRC_SGI(7 ) // (7 )
#define GIC_SRC_SGI8 GIC_SRC_SGI(8 ) // (8 )
#define GIC_SRC_SGI9 GIC_SRC_SGI(9 ) // (9 )
#define GIC_SRC_SGI10 GIC_SRC_SGI(10) // (10)
#define GIC_SRC_SGI11 GIC_SRC_SGI(11) // (11)
#define GIC_SRC_SGI12 GIC_SRC_SGI(12) // (12)
#define GIC_SRC_SGI13 GIC_SRC_SGI(13) // (13)
#define GIC_SRC_SGI14 GIC_SRC_SGI(14) // (14)
#define GIC_SRC_SGI15 GIC_SRC_SGI(15) // (15)
/* private peripheral interrupt */
#define GIC_SRC_PPI(_n) (16 + (_n))
#define GIC_SRC_PPI0 GIC_SRC_PPI(0 ) // (16)
#define GIC_SRC_PPI1 GIC_SRC_PPI(1 ) // (17)
#define GIC_SRC_PPI2 GIC_SRC_PPI(2 ) // (18)
#define GIC_SRC_PPI3 GIC_SRC_PPI(3 ) // (19)
#define GIC_SRC_PPI4 GIC_SRC_PPI(4 ) // (20)
#define GIC_SRC_PPI5 GIC_SRC_PPI(5 ) // (21)
#define GIC_SRC_PPI6 GIC_SRC_PPI(6 ) // (22)
#define GIC_SRC_PPI7 GIC_SRC_PPI(7 ) // (23)
#define GIC_SRC_PPI8 GIC_SRC_PPI(8 ) // (24)
#define GIC_SRC_PPI9 GIC_SRC_PPI(9 ) // (25)
#define GIC_SRC_PPI10 GIC_SRC_PPI(10) // (26)
#define GIC_SRC_PPI11 GIC_SRC_PPI(11) // (27)
#define GIC_SRC_PPI12 GIC_SRC_PPI(12) // (28)
#define GIC_SRC_PPI13 GIC_SRC_PPI(13) // (29)
#define GIC_SRC_PPI14 GIC_SRC_PPI(14) // (30)
#define GIC_SRC_PPI15 GIC_SRC_PPI(15) // (31)
/* external peripheral interrupt */
#define INTC_REG_NMI_CTRL bINT_CTL( INTC_REG_o_NMI_CTRL )
#define GIC_SRC_SPI(_n) (32 + (_n))
#define INTC_REG_IRQ_PENDCLR0 bINT_CTL( INTC_REG_o_IRQ_PENDCLR0 )
#define INTC_REG_IRQ_PENDCLR1 bINT_CTL( INTC_REG_o_IRQ_PENDCLR1 )
#define INTC_REG_IRQ_PENDCLR2 bINT_CTL( INTC_REG_o_IRQ_PENDCLR2 )
//#ifndef FPGA_PLATFORM //chip irq mapping
#if 0
#define INTC_REG_FIQ_PENDCLR0 bINT_CTL( INTC_REG_o_FIQ_PENDCLR0 )
#define INTC_REG_FIQ_PENDCLR1 bINT_CTL( INTC_REG_o_FIQ_PENDCLR1 )
#define INTC_REG_FIQ_PENDCLR2 bINT_CTL( INTC_REG_o_FIQ_PENDCLR2 )
#define GIC_SRC_NMI GIC_SRC_SPI(0) // (32)
#define GIC_SRC_UART0 GIC_SRC_SPI(1) // (33)
#define GIC_SRC_UART1 GIC_SRC_SPI(2) // (34)
#define GIC_SRC_UART2 GIC_SRC_SPI(3) // (35)
#define GIC_SRC_UART3 GIC_SRC_SPI(4) // (36)
#define GIC_SRC_CIR0 GIC_SRC_SPI(5) // (37)
#define GIC_SRC_CIR1 GIC_SRC_SPI(6 ) // (38)
#define GIC_SRC_TWI0 GIC_SRC_SPI(7 ) // (39)
#define GIC_SRC_TWI1 GIC_SRC_SPI(8 ) // (40)
#define GIC_SRC_TWI2 GIC_SRC_SPI(9 ) // (41)
#define GIC_SRC_SPI0 GIC_SRC_SPI(10 ) // (42)
#define GIC_SRC_SPI1 GIC_SRC_SPI(11 ) // (43)
#define GIC_SRC_SPI2 GIC_SRC_SPI(12 ) // (44)
#define GIC_SRC_SPDIF GIC_SRC_SPI(13 ) // (45)
#define GIC_SRC_AC97 GIC_SRC_SPI(14 ) // (46)
#define GIC_SRC_TS GIC_SRC_SPI(15 ) // (47)
#define GIC_SRC_IIS GIC_SRC_SPI(16 ) // (48)
#define GIC_SRC_UART4 GIC_SRC_SPI(17 ) // (49)
#define GIC_SRC_UART5 GIC_SRC_SPI(18 ) // (50)
#define GIC_SRC_UART6 GIC_SRC_SPI(19 ) // (51)
#define GIC_SRC_UART7 GIC_SRC_SPI(20 ) // (52)
#define GIC_SRC_KP GIC_SRC_SPI(21 ) // (53)
#define GIC_SRC_TIMER0 GIC_SRC_SPI(22 ) // (54)
#define GIC_SRC_TIMER1 GIC_SRC_SPI(23 ) // (55)
#define GIC_SRC_TIMER2 GIC_SRC_SPI(24 ) // (56)
#define GIC_SRC_TIMER3 GIC_SRC_SPI(25 ) // (57)
#define GIC_SRC_CAN GIC_SRC_SPI(26 ) // (58)
#define GIC_SRC_DMA GIC_SRC_SPI(27 ) // (59)
#define GIC_SRC_PIO_EINT GIC_SRC_SPI(28 ) // (60)
#define GIC_SRC_TP GIC_SRC_SPI(29 ) // (61)
#define GIC_SRC_CODEC GIC_SRC_SPI(30 ) // (62)
#define GIC_SRC_LRADC GIC_SRC_SPI(31 ) // (63)
#define GIC_SRC_MMC0 GIC_SRC_SPI(32 ) // (64)
#define GIC_SRC_MMC1 GIC_SRC_SPI(33 ) // (65)
#define GIC_SRC_MMC2 GIC_SRC_SPI(34 ) // (66)
#define GIC_SRC_MMC3 GIC_SRC_SPI(35 ) // (67)
#define GIC_SRC_MS GIC_SRC_SPI(36 ) // (68)
#define GIC_SRC_NAND GIC_SRC_SPI(37 ) // (69)
#define GIC_SRC_USB0 GIC_SRC_SPI(38 ) // (70)
#define GIC_SRC_USB1 GIC_SRC_SPI(39 ) // (71)
#define GIC_SRC_USB2 GIC_SRC_SPI(40 ) // (72)
#define GIC_SRC_SCR GIC_SRC_SPI(41 ) // (73)
#define GIC_SRC_CSI0 GIC_SRC_SPI(42 ) // (74)
#define GIC_SRC_CSI1 GIC_SRC_SPI(43 ) // (75)
#define GIC_SRC_LCD0 GIC_SRC_SPI(44 ) // (76)
#define GIC_SRC_LCD1 GIC_SRC_SPI(45 ) // (77)
#define GIC_SRC_MP GIC_SRC_SPI(46 ) // (78)
#define GIC_SRC_DEBE0_DEFE0 GIC_SRC_SPI(47 ) // (79)
#define GIC_SRC_DEBE1_DEFE1 GIC_SRC_SPI(48 ) // (80)
#define GIC_SRC_PMU GIC_SRC_SPI(49 ) // (81)
#define GIC_SRC_SPI3 GIC_SRC_SPI(50 ) // (82)
//#define GIC_SRC_ GIC_SRC_SPI(51 ) // (83)
#define GIC_SRC_PATA GIC_SRC_SPI(52 ) // (84)
#define GIC_SRC_VE GIC_SRC_SPI(53 ) // (85)
#define GIC_SRC_SS GIC_SRC_SPI(54 ) // (86)
#define GIC_SRC_EMAC GIC_SRC_SPI(55 ) // (87)
#define GIC_SRC_SATA GIC_SRC_SPI(56 ) // (88)
#define GIC_SRC_GPS GIC_SRC_SPI(57 ) // (89)
#define GIC_SRC_HDMI GIC_SRC_SPI(58 ) // (90)
#define GIC_SRC_TVE01 GIC_SRC_SPI(59 ) // (91)
#define GIC_SRC_ACE GIC_SRC_SPI(60 ) // (92)
#define GIC_SRC_TVD GIC_SRC_SPI(61 ) // (93)
#define GIC_SRC_PS2_0 GIC_SRC_SPI(62 ) // (94)
#define GIC_SRC_PS2_1 GIC_SRC_SPI(63 ) // (95)
#define GIC_SRC_USB3 GIC_SRC_SPI(64 ) // (96)
#define GIC_SRC_USB4 GIC_SRC_SPI(65 ) // (97 )
#define GIC_SRC_PLE_PERFMU GIC_SRC_SPI(66 ) // (98 )
#define GIC_SRC_TIMER4 GIC_SRC_SPI(67 ) // (99 )
#define GIC_SRC_TIMER5 GIC_SRC_SPI(68 ) // (100)
#define GIC_SRC_GPU_GP GIC_SRC_SPI(69 ) // (101)
#define GIC_SRC_GPU_GPMMU GIC_SRC_SPI(70 ) // (102)
#define GIC_SRC_GPU_PP0 GIC_SRC_SPI(71 ) // (103)
#define GIC_SRC_GPU_PPMMU0 GIC_SRC_SPI(72 ) // (104)
#define GIC_SRC_GPU_PMU GIC_SRC_SPI(73 ) // (105)
#define GIC_SRC_GPU_PP1 GIC_SRC_SPI(74 ) // (106)
#define GIC_SRC_GPU_PPMMU1 GIC_SRC_SPI(75 ) // (107)
#define GIC_SRC_GPU_RSV0 GIC_SRC_SPI(76 ) // (108)
#define GIC_SRC_GPU_RSV1 GIC_SRC_SPI(77 ) // (109)
#define GIC_SRC_GPU_RSV2 GIC_SRC_SPI(78 ) // (110)
#define GIC_SRC_GPU_RSV3 GIC_SRC_SPI(79 ) // (111)
#define GIC_SRC_GPU_RSV4 GIC_SRC_SPI(80 ) // (112)
#define GIC_SRC_HSTMR0 GIC_SRC_SPI(81 ) // (113)
#define GIC_SRC_HSTMR1 GIC_SRC_SPI(82 ) // (114)
#define GIC_SRC_HSTMR2 GIC_SRC_SPI(83 ) // (115)
#define GIC_SRC_HSTMR3 GIC_SRC_SPI(84 ) // (116)
#define GIC_SRC_GMAC GIC_SRC_SPI(85 ) // (117)
//#define GIC_SRC_ GIC_SRC_SPI(86 ) // (118)
//#define GIC_SRC_ GIC_SRC_SPI(87 ) // (119)
//#define GIC_SRC_ GIC_SRC_SPI(88 ) // (120)
//#define GIC_SRC_ GIC_SRC_SPI(89 ) // (121)
//#define GIC_SRC_ GIC_SRC_SPI(90 ) // (122)
//#define GIC_SRC_ GIC_SRC_SPI(91 ) // (123)
//#define GIC_SRC_ GIC_SRC_SPI(92 ) // (124)
//#define GIC_SRC_ GIC_SRC_SPI(93 ) // (125)
//#define GIC_SRC_ GIC_SRC_SPI(94 ) // (126)
//#define GIC_SRC_ GIC_SRC_SPI(95 ) // (127)
//#define GIC_SRC_ GIC_SRC_SPI(96 ) // (128)
//#define GIC_SRC_ GIC_SRC_SPI(97 ) // (129)
//
//#define GIC_SRC_ GIC_SRC_SPI(108) // (140)
//#define GIC_SRC_ GIC_SRC_SPI(109) // (141)
//#define GIC_SRC_ GIC_SRC_SPI(110) // (142)
//#define GIC_SRC_ GIC_SRC_SPI(111) // (143)
//#define GIC_SRC_ GIC_SRC_SPI(112) // (144)
//#define GIC_SRC_ GIC_SRC_SPI(113) // (145)
//#define GIC_SRC_ GIC_SRC_SPI(114) // (146)
//#define GIC_SRC_ GIC_SRC_SPI(115) // (147)
//#define GIC_SRC_ GIC_SRC_SPI(116) // (148)
//#define GIC_SRC_ GIC_SRC_SPI(117) // (149)
//#define GIC_SRC_ GIC_SRC_SPI(118) // (150)
//#define GIC_SRC_ GIC_SRC_SPI(119) // (151)
//#define GIC_SRC_ GIC_SRC_SPI(120) // (152)
//#define GIC_SRC_ GIC_SRC_SPI(121) // (153)
//#define GIC_SRC_ GIC_SRC_SPI(122) // (154)
//#define GIC_SRC_ GIC_SRC_SPI(123) // (155)
//#define GIC_SRC_ GIC_SRC_SPI(124) // (156)
#define INTC_REG_IRQ_SEL0 bINT_CTL( INTC_REG_o_IRQ_SEL0 )
#define INTC_REG_IRQ_SEL1 bINT_CTL( INTC_REG_o_IRQ_SEL1 )
#define INTC_REG_IRQ_SEL2 bINT_CTL( INTC_REG_o_IRQ_SEL2 )
#define GIC_IRQ_NUM (GIC_SRC_HSTMR3 + 1)
#define INTC_REG_ENABLE0 bINT_CTL( INTC_REG_o_ENABLE0 )
#define INTC_REG_ENABLE1 bINT_CTL( INTC_REG_o_ENABLE1 )
#define INTC_REG_ENABLE2 bINT_CTL( INTC_REG_o_ENABLE2 )
#else //fpga irq mapping
#define GIC_SRC_NMI GIC_SRC_SPI(0) // (32)
#define GIC_SRC_UART0 GIC_SRC_SPI(1) // (33)
#define GIC_SRC_UART1 GIC_SRC_SPI(1) // (33) not exist in fpga, just for compiling
#define GIC_SRC_UART2 GIC_SRC_SPI(1) // (33) not exist in fpga, just for compiling
#define GIC_SRC_UART3 GIC_SRC_SPI(1) // (33) not exist in fpga, just for compiling
#define GIC_SRC_UART4 GIC_SRC_SPI(1) // (33) not exist in fpga, just for compiling
#define GIC_SRC_UART5 GIC_SRC_SPI(1) // (33) not exist in fpga, just for compiling
#define GIC_SRC_UART6 GIC_SRC_SPI(1) // (33) not exist in fpga, just for compiling
#define GIC_SRC_UART7 GIC_SRC_SPI(1) // (33) not exist in fpga, just for compiling
#define GIC_SRC_TWI0 GIC_SRC_SPI(2) // (34)
#define GIC_SRC_TWI1 GIC_SRC_SPI(2) // (34) not exist in fpga, just for compiling
#define GIC_SRC_TWI2 GIC_SRC_SPI(2) // (34) not exist in fpga, just for compiling
#define GIC_SRC_PIO_EINT GIC_SRC_SPI(2) // (34)
#define GIC_SRC_CIR0 GIC_SRC_SPI(2) // (34)
#define GIC_SRC_CIR1 GIC_SRC_SPI(2) // (34) not exist in fpga, just for compiling
#define GIC_SRC_KP GIC_SRC_SPI(2) // (34)
#define GIC_SRC_CAN GIC_SRC_SPI(2) // (34)
#define GIC_SRC_PS2_0 GIC_SRC_SPI(2) // (34)
#define GIC_SRC_PS2_1 GIC_SRC_SPI(2) // (34) not exist in fpga, just for compiling
#define GIC_SRC_SPDIF GIC_SRC_SPI(3) // (35)
#define GIC_SRC_IIS GIC_SRC_SPI(3) // (35)
#define GIC_SRC_AC97 GIC_SRC_SPI(3) // (35)
#define GIC_SRC_TS GIC_SRC_SPI(3) // (35)
#define GIC_SRC_PLE_PERFMU GIC_SRC_SPI(3) // (35)
#define GIC_SRC_TIMER0 GIC_SRC_SPI(4) // (36)
#define GIC_SRC_TIMER1 GIC_SRC_SPI(5) // (37)
#define GIC_SRC_HSTMR0 GIC_SRC_SPI(5) // (37)
#define GIC_SRC_HSTMR1 GIC_SRC_SPI(5) // (37) not exist in fpga, just for compiling
#define GIC_SRC_HSTMR2 GIC_SRC_SPI(5) // (37) not exist in fpga, just for compiling
#define GIC_SRC_HSTMR3 GIC_SRC_SPI(5) // (37) not exist in fpga, just for compiling
#define GIC_SRC_TIMER2 GIC_SRC_SPI(6) // (38)
#define GIC_SRC_TIMER3 GIC_SRC_SPI(6) // (38) not exist in fpga, just for compiling
#define GIC_SRC_TIMER4 GIC_SRC_SPI(6) // (38) not exist in fpga, just for compiling
#define GIC_SRC_TIMER5 GIC_SRC_SPI(6) // (38) not exist in fpga, just for compiling
#define GIC_SRC_DMA GIC_SRC_SPI(7) // (38)
#define GIC_SRC_TP GIC_SRC_SPI(8) // (40)
#define GIC_SRC_CODEC GIC_SRC_SPI(8) // (40)
#define GIC_SRC_LRADC GIC_SRC_SPI(8) // (40)
#define GIC_SRC_MMC0 GIC_SRC_SPI(9) // (41)
#define GIC_SRC_MMC1 GIC_SRC_SPI(9) // (41) not exist in fpga, just for compiling
#define GIC_SRC_MMC2 GIC_SRC_SPI(10) // (42)
#define GIC_SRC_MMC3 GIC_SRC_SPI(10) // (42) not exist in fpga, just for compiling
#define GIC_SRC_MS GIC_SRC_SPI(10) // (42)
#define GIC_SRC_NAND GIC_SRC_SPI(11) // (43)
#define GIC_SRC_USB0 GIC_SRC_SPI(12) // (44)
#define GIC_SRC_USB1 GIC_SRC_SPI(13) // (45)
#define GIC_SRC_USB2 GIC_SRC_SPI(14) // (46)
#define GIC_SRC_CSI1 GIC_SRC_SPI(14) // (46)
#define GIC_SRC_TVD GIC_SRC_SPI(14) // (46)
#define GIC_SRC_SCR GIC_SRC_SPI(15) // (47)
#define GIC_SRC_SPI0 GIC_SRC_SPI(15) // (47)
#define GIC_SRC_SPI1 GIC_SRC_SPI(15) // (47) not exist in fpga, just for compiling
#define GIC_SRC_SPI2 GIC_SRC_SPI(15) // (47) not exist in fpga, just for compiling
#define GIC_SRC_SPI3 GIC_SRC_SPI(15) // (47) not exist in fpga, just for compiling
#define GIC_SRC_TVE01 GIC_SRC_SPI(15) // (47)
#define GIC_SRC_EMAC GIC_SRC_SPI(15) // (47)
#define GIC_SRC_GMAC GIC_SRC_SPI(15) // (47)
#define GIC_SRC_USB3 GIC_SRC_SPI(15) // (47)
#define GIC_SRC_CSI0 GIC_SRC_SPI(16) // (48)
#define GIC_SRC_USB4 GIC_SRC_SPI(16) // (48)
#define GIC_SRC_LCD0 GIC_SRC_SPI(17) // (49)
#define GIC_SRC_LCD1 GIC_SRC_SPI(18) // (50)
#define GIC_SRC_MP GIC_SRC_SPI(19) // (51)
#define GIC_SRC_DEBE0_DEFE0 GIC_SRC_SPI(20) // (52)
#define GIC_SRC_DEBE1_DEFE1 GIC_SRC_SPI(21) // (53)
#define GIC_SRC_PMU GIC_SRC_SPI(22) // (54)
#define GIC_SRC_SATA GIC_SRC_SPI(22) // (54)
#define GIC_SRC_PATA GIC_SRC_SPI(22) // (54)
#define GIC_SRC_HDMI GIC_SRC_SPI(23) // (55)
#define GIC_SRC_VE GIC_SRC_SPI(24) // (56)
#define GIC_SRC_SS GIC_SRC_SPI(24) // (56)
#define GIC_SRC_GPS GIC_SRC_SPI(24) // (56)
#define GIC_SRC_ACE GIC_SRC_SPI(24) // (56)
#define GIC_SRC_GPU_GP GIC_SRC_SPI(25) // (57)
#define GIC_SRC_GPU_GPMMU GIC_SRC_SPI(26) // (58)
#define GIC_SRC_GPU_PP0 GIC_SRC_SPI(27) // (59)
#define GIC_SRC_GPU_PPMMU0 GIC_SRC_SPI(28) // (60)
#define GIC_SRC_GPU_PMU GIC_SRC_SPI(29) // (61)
#define GIC_SRC_GPU_PP1 GIC_SRC_SPI(30) // (62)
#define GIC_SRC_GPU_PPMMU1 GIC_SRC_SPI(31) // (63)
#define GIC_IRQ_NUM (GIC_SRC_GPU_PPMMU1 + 1)
#define INTC_REG_MASK0 bINT_CTL( INTC_REG_o_MASK0 )
#define INTC_REG_MASK1 bINT_CTL( INTC_REG_o_MASK1 )
#define INTC_REG_MASK2 bINT_CTL( INTC_REG_o_MASK2 )
#define INTC_REG_RESP0 bINT_CTL( INTC_REG_o_RESP0 )
#define INTC_REG_RSEP1 bINT_CTL( INTC_REG_o_RSEP1 )
#define INTC_REG_RESP2 bINT_CTL( INTC_REG_o_RESP2 )
#define INTC_REG_FF0 bINT_CTL( INTC_REG_o_FF0 )
#define INTC_REG_FF1 bINT_CTL( INTC_REG_o_FF1 )
#define INTC_REG_FF2 bINT_CTL( INTC_REG_o_FF2 )
#define INTC_REG_PRIO0 bINT_CTL( INTC_REG_o_PRIO0 )
#define INTC_REG_PRIO1 bINT_CTL( INTC_REG_o_PRIO1 )
#define INTC_REG_PRIO2 bINT_CTL( INTC_REG_o_PRIO2 )
#define INTC_REG_PRIO3 bINT_CTL( INTC_REG_o_PRIO3 )
#define INTC_REG_PRIO4 bINT_CTL( INTC_REG_o_PRIO4 )
#endif //fpga irq mapping
/* mask */
#define INTC_IRQNO_FIQ 0
#define INTC_IRQNO_UART0 1
#define INTC_IRQNO_UART1 2
#define INTC_IRQNO_UART2 3
#define INTC_IRQNO_UART3 4
#define INTC_IRQNO_IR0 5
#define INTC_IRQNO_IR1 6
#define INTC_IRQNO_TWI0 7
#define INTC_IRQNO_TWI1 8
#define INTC_IRQNO_TWI2 9
#define INTC_IRQNO_SPI0 10
#define INTC_IRQNO_SPI1 11
#define INTC_IRQNO_SPI2 12
#define INTC_IRQNO_SPDIF 13
#define INTC_IRQNO_AC97 14
#define INTC_IRQNO_TS 15
#define INTC_IRQNO_IIS 16
#define INTC_IRQNO_UART4 17
#define INTC_IRQNO_UART5 18
#define INTC_IRQNO_UART6 19
#define INTC_IRQNO_UART7 20
#define INTC_IRQNO_KEYPAD 21
#define INTC_IRQNO_TIMER0 22
#define INTC_IRQNO_TIMER1 23
#define INTC_IRQNO_TIMER245 24
#define INTC_IRQNO_TIMER3 25
#define INTC_IRQNO_CAN 26
#define INTC_IRQNO_DMA 27
#define INTC_IRQNO_PIO 28
#define INTC_IRQNO_TP 29
#define INTC_IRQNO_ADDA 30
#define INTC_IRQNO_LRADC 31
#define INTC_IRQNO_SDMMC0 32
#define INTC_IRQNO_SDMMC1 33
#define INTC_IRQNO_SDMMC2 34
#define INTC_IRQNO_SDMMC3 35
#define INTC_IRQNO_MS 36
#define INTC_IRQNO_NAND 37
#define INTC_IRQNO_USB0 38
#define INTC_IRQNO_USB1 39
#define INTC_IRQNO_USB2 40
#define INTC_IRQNO_SCR 41
#define INTC_IRQNO_CSI0 42
#define INTC_IRQNO_CSI1 43
#define INTC_IRQNO_LCD0 44
#define INTC_IRQNO_LCD1 45
#define INTC_IRQNO_MP 46
#define INTC_IRQNO_DE_FE0 47
#define INTC_IRQNO_DE_FE1 48
#define INTC_IRQNO_PMU 49
#define INTC_IRQNO_SPI3 50
#define INTC_IRQNO_TZASC 51
#define INTC_IRQNO_PATA 52
#define INTC_IRQNO_VE 53
#define INTC_IRQNO_SS 54
#define INTC_IRQNO_EMAC 55
#define INTC_IRQNO_SATA 56
#define INTC_IRQNO_GPS 57
#define INTC_IRQNO_HDMI 58
#define INTC_IRQNO_TVE01 59
#define INTC_IRQNO_ACE 60
#define INTC_IRQNO_TVD 61
#define INTC_IRQNO_PS0 62
#define INTC_IRQNO_PS1 63
#define INTC_IRQNO_USB3 64
#define INTC_IRQNO_USB4 65
#define INTC_IRQNO_PLE 66
#define INTC_IRQNO_TIMER4 67
#define INTC_IRQNO_TIMER5 68
#define INTC_IRQNO_GPU_GP 69
#define INTC_IRQNO_GPU_MP 70
#define INTC_IRQNO_GPU_PP0 71
#define INTC_IRQNO_GPU_PPMMU0 72
#define INTC_IRQNO_GPU_PMU 73
#define INTC_IRQNO_GPU_RSV0 74
#define INTC_IRQNO_GPU_RSV1 75
#define INTC_IRQNO_GPU_RSV2 76
#define INTC_IRQNO_GPU_RSV3 77
#define INTC_IRQNO_GPU_RSV4 78
#define INTC_IRQNO_GPU_RSV5 79
#define INTC_IRQNO_GPU_RSV6 80
#endif
#endif /* _INTC_H_ */

BIN
workspace/egon/boot1_nand.bin
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