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https://github.com/hno/allwinner-boot.git
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update dram drv
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zhengjiewen
parent
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commit
cc54a0cb54
@ -1,95 +1,95 @@
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/*
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*********************************************************************************************************
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* File : dram_i.h
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* By : Berg.Xing
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* Date : 2011-06-01
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* Descript: dram csp for AW1623 chipset;
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* Update : date auther ver notes
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* 2011-06-01 Berg 1.0 create file
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* 2011-07-01 Berg 1.1 add extern function description
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* 2011-08-05 Berg 1.2 add CPU_CFIG_REG in timer module
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*********************************************************************************************************
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*/
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#ifndef __DRAM_I_H__
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#define __DRAM_I_H__
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#define DRAMC_PHY_BASE 0x01c01000
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#define DRAMC_MEM_SIZE 0x400
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#define SDR_CCR (DRAMC_PHY_BASE + 0x00)
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#define SDR_DCR (DRAMC_PHY_BASE + 0x04)
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#define SDR_IOCR (DRAMC_PHY_BASE + 0x08)
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#define SDR_CSR (DRAMC_PHY_BASE + 0x0c)
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#define SDR_DRR (DRAMC_PHY_BASE + 0x10)
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#define SDR_TPR0 (DRAMC_PHY_BASE + 0x14)
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#define SDR_TPR1 (DRAMC_PHY_BASE + 0x18)
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#define SDR_TPR2 (DRAMC_PHY_BASE + 0x1c)
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#define SDR_RSLR0 (DRAMC_PHY_BASE + 0x4c)
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#define SDR_RSLR1 (DRAMC_PHY_BASE + 0x50)
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#define SDR_RDQSGR (DRAMC_PHY_BASE + 0x5c)
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#define SDR_ODTCR (DRAMC_PHY_BASE + 0x98)
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#define SDR_DTR0 (DRAMC_PHY_BASE + 0x9c)
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#define SDR_DTR1 (DRAMC_PHY_BASE + 0xa0)
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#define SDR_DTAR (DRAMC_PHY_BASE + 0xa4)
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#define SDR_ZQCR0 (DRAMC_PHY_BASE + 0xa8)
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#define SDR_ZQCR1 (DRAMC_PHY_BASE + 0xac)
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#define SDR_ZQSR (DRAMC_PHY_BASE + 0xb0)
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#define SDR_IDCR (DRAMC_PHY_BASE + 0xb4)
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#define SDR_MR (DRAMC_PHY_BASE + 0x1f0)
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#define SDR_EMR (DRAMC_PHY_BASE + 0x1f4)
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#define SDR_EMR2 (DRAMC_PHY_BASE + 0x1f8)
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#define SDR_EMR3 (DRAMC_PHY_BASE + 0x1fc)
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#define SDR_DLLCR (DRAMC_PHY_BASE + 0x200)
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#define SDR_DLLCR0 (DRAMC_PHY_BASE + 0x204)
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#define SDR_DLLCR1 (DRAMC_PHY_BASE + 0x208)
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#define SDR_DLLCR2 (DRAMC_PHY_BASE + 0x20c)
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#define SDR_DLLCR3 (DRAMC_PHY_BASE + 0x210)
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#define SDR_DLLCR4 (DRAMC_PHY_BASE + 0x214)
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#define SDR_DQTR0 (DRAMC_PHY_BASE + 0x218)
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#define SDR_DQTR1 (DRAMC_PHY_BASE + 0x21c)
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#define SDR_DQTR2 (DRAMC_PHY_BASE + 0x220)
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#define SDR_DQTR3 (DRAMC_PHY_BASE + 0x224)
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#define SDR_DQSTR0 (DRAMC_PHY_BASE + 0x228)
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#define SDR_DQSTR1 (DRAMC_PHY_BASE + 0x22c)
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#define SDR_CR (DRAMC_PHY_BASE + 0x230)
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#define SDR_CFSR (DRAMC_PHY_BASE + 0x234)
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#define SDR_DPCR (DRAMC_PHY_BASE + 0x23c)
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#define SDR_APR (DRAMC_PHY_BASE + 0x240)
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#define SDR_LTR (DRAMC_PHY_BASE + 0x244)
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#define SDR_HPCR (DRAMC_PHY_BASE + 0x250)
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#define SDR_SCSR (DRAMC_PHY_BASE + 0x2e0)
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#define mctl_read_w(n) (*((volatile unsigned int *)(n)))
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#define mctl_write_w(n,c) (*((volatile unsigned int *)(n)) = (c))
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//CCM register for dram
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#define DRAM_CCM_BASE 0x01c20000
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#define DRAM_CCM_MEMSIZE 0x400
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#define DRAM_CCM_SDRAM_PLL_REG (DRAM_CCM_BASE + 0x20)
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#define DRAM_CCM_AHB_GATE_REG (DRAM_CCM_BASE + 0x60)
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#define DRAM_CCM_GPS_CLK_REG (DRAM_CCM_BASE + 0xd0)
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#define DRAM_CCM_SDRAM_CLK_REG (DRAM_CCM_BASE + 0x100)
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//TIMER register for system
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#define DRAM_TIMER_BASE 0x01c20c00
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#define TIMER_CPU_CFG_REG (DRAM_TIMER_BASE + 0x13c)
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extern void DRAMC_clock_output_en(__u32 on);
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extern void DRAMC_set_autorefresh_cycle(__u32 clk);
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extern int DRAMC_scan_readpipe(void);
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extern unsigned DRAMC_get_dram_size(void);
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extern void mctl_delay(__u32 dly);
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extern void mctl_itm_disable(void);
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extern void mctl_itm_enable(void);
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extern void mctl_enable_dll0(void);
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extern void mctl_enable_dllx(void);
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extern void mctl_disable_dll(void);
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#endif //__DRAM_REG_H__
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/*
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*********************************************************************************************************
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* File : dram_i.h
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* By : Berg.Xing
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* Date : 2011-06-01
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* Descript: dram csp for AW1623 chipset;
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* Update : date auther ver notes
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* 2011-06-01 Berg 1.0 create file
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* 2011-07-01 Berg 1.1 add extern function description
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* 2011-08-05 Berg 1.2 add CPU_CFIG_REG in timer module
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*********************************************************************************************************
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*/
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#ifndef __DRAM_I_H__
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#define __DRAM_I_H__
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#define DRAMC_PHY_BASE 0x01c01000
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#define DRAMC_MEM_SIZE 0x400
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#define SDR_CCR (DRAMC_PHY_BASE + 0x00)
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#define SDR_DCR (DRAMC_PHY_BASE + 0x04)
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#define SDR_IOCR (DRAMC_PHY_BASE + 0x08)
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#define SDR_CSR (DRAMC_PHY_BASE + 0x0c)
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#define SDR_DRR (DRAMC_PHY_BASE + 0x10)
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#define SDR_TPR0 (DRAMC_PHY_BASE + 0x14)
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#define SDR_TPR1 (DRAMC_PHY_BASE + 0x18)
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#define SDR_TPR2 (DRAMC_PHY_BASE + 0x1c)
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#define SDR_RSLR0 (DRAMC_PHY_BASE + 0x4c)
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#define SDR_RSLR1 (DRAMC_PHY_BASE + 0x50)
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#define SDR_RDQSGR (DRAMC_PHY_BASE + 0x5c)
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#define SDR_ODTCR (DRAMC_PHY_BASE + 0x98)
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#define SDR_DTR0 (DRAMC_PHY_BASE + 0x9c)
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#define SDR_DTR1 (DRAMC_PHY_BASE + 0xa0)
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#define SDR_DTAR (DRAMC_PHY_BASE + 0xa4)
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#define SDR_ZQCR0 (DRAMC_PHY_BASE + 0xa8)
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#define SDR_ZQCR1 (DRAMC_PHY_BASE + 0xac)
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#define SDR_ZQSR (DRAMC_PHY_BASE + 0xb0)
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#define SDR_IDCR (DRAMC_PHY_BASE + 0xb4)
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#define SDR_MR (DRAMC_PHY_BASE + 0x1f0)
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#define SDR_EMR (DRAMC_PHY_BASE + 0x1f4)
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#define SDR_EMR2 (DRAMC_PHY_BASE + 0x1f8)
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#define SDR_EMR3 (DRAMC_PHY_BASE + 0x1fc)
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#define SDR_DLLCR (DRAMC_PHY_BASE + 0x200)
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#define SDR_DLLCR0 (DRAMC_PHY_BASE + 0x204)
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#define SDR_DLLCR1 (DRAMC_PHY_BASE + 0x208)
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#define SDR_DLLCR2 (DRAMC_PHY_BASE + 0x20c)
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#define SDR_DLLCR3 (DRAMC_PHY_BASE + 0x210)
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#define SDR_DLLCR4 (DRAMC_PHY_BASE + 0x214)
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#define SDR_DQTR0 (DRAMC_PHY_BASE + 0x218)
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#define SDR_DQTR1 (DRAMC_PHY_BASE + 0x21c)
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#define SDR_DQTR2 (DRAMC_PHY_BASE + 0x220)
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#define SDR_DQTR3 (DRAMC_PHY_BASE + 0x224)
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#define SDR_DQSTR0 (DRAMC_PHY_BASE + 0x228)
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#define SDR_DQSTR1 (DRAMC_PHY_BASE + 0x22c)
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#define SDR_CR (DRAMC_PHY_BASE + 0x230)
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#define SDR_CFSR (DRAMC_PHY_BASE + 0x234)
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#define SDR_DPCR (DRAMC_PHY_BASE + 0x23c)
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#define SDR_APR (DRAMC_PHY_BASE + 0x240)
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#define SDR_LTR (DRAMC_PHY_BASE + 0x244)
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#define SDR_HPCR (DRAMC_PHY_BASE + 0x250)
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#define SDR_SCSR (DRAMC_PHY_BASE + 0x2e0)
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#define mctl_read_w(n) (*((volatile unsigned int *)(n)))
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#define mctl_write_w(n,c) (*((volatile unsigned int *)(n)) = (c))
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//CCM register for dram
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#define DRAM_CCM_BASE 0x01c20000
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#define DRAM_CCM_MEMSIZE 0x400
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#define DRAM_CCM_SDRAM_PLL_REG (DRAM_CCM_BASE + 0x20)
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#define DRAM_CCM_AHB_GATE_REG (DRAM_CCM_BASE + 0x60)
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#define DRAM_CCM_GPS_CLK_REG (DRAM_CCM_BASE + 0xd0)
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#define DRAM_CCM_SDRAM_CLK_REG (DRAM_CCM_BASE + 0x100)
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//TIMER register for system
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#define DRAM_TIMER_BASE 0x01c20c00
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#define TIMER_CPU_CFG_REG (DRAM_TIMER_BASE + 0x13c)
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extern void DRAMC_clock_output_en(__u32 on);
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extern void DRAMC_set_autorefresh_cycle(__u32 clk);
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extern int DRAMC_scan_readpipe(void);
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extern unsigned DRAMC_get_dram_size(void);
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extern void mctl_delay(__u32 dly);
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extern void mctl_itm_disable(void);
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extern void mctl_itm_enable(void);
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extern void mctl_enable_dll0(void);
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extern void mctl_enable_dllx(void);
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extern void mctl_disable_dll(void);
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#endif //__DRAM_REG_H__
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File diff suppressed because it is too large
Load Diff
@ -1,71 +1,71 @@
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/*
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*********************************************************************************************************
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* MELIS
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* the Easy Portable/Player Develop Kits
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* DRAM CSP Module
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*
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* (c) Copyright 2006-2010, Berg.Xing China
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* All Rights Reserved
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*
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* File : csp_dram_para.h
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* By : Berg.Xing
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* Version : v1.0
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* Date : 2010-12-2 13:24
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* Descript:
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* Update : date auther ver notes
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* 2010-12-2 13:24 Berg.Xing 1.0 build the file;
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*********************************************************************************************************
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*/
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#ifndef __CSP_DRAM_PARA_H__
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#define __CSP_DRAM_PARA_H__
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#define DRAM_PIN_DEV_ID (0)
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#define DRAM_PIN_LIST ((__u32 *)0)
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#define DRAM_PIN_NUMBER (0)
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#define FPGA_51_TEST
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/*
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#define T_WR 0x9
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#define T_WTR 0x7
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#define T_RTP 0x3
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#define T_RTW 0x6
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#define T_RAS 0xf
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#define T_RRD 0x4
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#define T_RC 0x14
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#define T_RCD 0x5
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#define T_CKE 0x3
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#define T_APD 0x8
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#define T_XP 0x2
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#define T_FAW 0xf
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#define T_XSR 0xc8
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#define T_RP 0x5
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*/
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//==============================================================================
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// dram configuration parameter reference value
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//==============================================================================
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//DDR1_32B DDR1_32B_32Mx16 (DDR 32-bits bus by two 32Mx16 SDRAM chip)
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//DDR1_16B DDR1_16B_32Mx16
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//DDR2_32B DDR2_32B_64Mx16
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//DDR2_16B DDR2_16B_64Mx16
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//DDR3_32B DDR3_32B_128Mx16
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//DDR3_16B DDR3_32B_128Mx16
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//#ifdef DDR2_FPGA_S2C
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//DDR2 64Mx16 (128M Byte)
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#define MCTL_DDR_TYPE 2 //1: DDR, 2: DDR2, 3: DDR3
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#define MCTL_IO_WIDTH 8
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#define MCTL_CHIP_SIZE 1024 //unit in Mb
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#define MCTL_CAS 5
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#define MCTL_BANK_SIZE 8
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#define MCTL_COL_WIDTH 10
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#define MCTL_ROW_WIDTH 14
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#define MCTL_BUS_WIDTH 32
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#define DRAMC_ID 1 //0: DRAMC0, 1: DRAMC1
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//#endif
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#endif //__CSP_DRAM_PARA_H__
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/*
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*********************************************************************************************************
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* MELIS
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* the Easy Portable/Player Develop Kits
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* DRAM CSP Module
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*
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* (c) Copyright 2006-2010, Berg.Xing China
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* All Rights Reserved
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*
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* File : csp_dram_para.h
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* By : Berg.Xing
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* Version : v1.0
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* Date : 2010-12-2 13:24
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* Descript:
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* Update : date auther ver notes
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* 2010-12-2 13:24 Berg.Xing 1.0 build the file;
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*********************************************************************************************************
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*/
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#ifndef __CSP_DRAM_PARA_H__
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#define __CSP_DRAM_PARA_H__
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#define DRAM_PIN_DEV_ID (0)
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#define DRAM_PIN_LIST ((__u32 *)0)
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#define DRAM_PIN_NUMBER (0)
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#define FPGA_51_TEST
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/*
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#define T_WR 0x9
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#define T_WTR 0x7
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#define T_RTP 0x3
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#define T_RTW 0x6
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#define T_RAS 0xf
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#define T_RRD 0x4
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#define T_RC 0x14
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#define T_RCD 0x5
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#define T_CKE 0x3
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#define T_APD 0x8
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#define T_XP 0x2
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#define T_FAW 0xf
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#define T_XSR 0xc8
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#define T_RP 0x5
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*/
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//==============================================================================
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// dram configuration parameter reference value
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//==============================================================================
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//DDR1_32B DDR1_32B_32Mx16 (DDR 32-bits bus by two 32Mx16 SDRAM chip)
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//DDR1_16B DDR1_16B_32Mx16
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//DDR2_32B DDR2_32B_64Mx16
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//DDR2_16B DDR2_16B_64Mx16
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//DDR3_32B DDR3_32B_128Mx16
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//DDR3_16B DDR3_32B_128Mx16
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//#ifdef DDR2_FPGA_S2C
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//DDR2 64Mx16 (128M Byte)
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#define MCTL_DDR_TYPE 2 //1: DDR, 2: DDR2, 3: DDR3
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#define MCTL_IO_WIDTH 8
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#define MCTL_CHIP_SIZE 1024 //unit in Mb
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#define MCTL_CAS 5
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#define MCTL_BANK_SIZE 8
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#define MCTL_COL_WIDTH 10
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#define MCTL_ROW_WIDTH 14
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#define MCTL_BUS_WIDTH 32
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#define DRAMC_ID 1 //0: DRAMC0, 1: DRAMC1
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//#endif
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#endif //__CSP_DRAM_PARA_H__
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