mirror of
https://github.com/hno/allwinner-boot.git
synced 2025-05-09 03:41:18 +08:00
aw1651 boot0 boot from fpga ok
This commit is contained in:
martin_zheng
parent
03c1880b28
commit
e2cfc952ec
@ -76,8 +76,8 @@ void Boot0_C_part( void )
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mmu_system_init(EGON2_DRAM_BASE, 4 * 1024, EGON2_MMU_BASE);
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mmu_enable();
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//dram_size = init_DRAM(BT0_head.boot_head.platform[7]); // ³õʼ»¯DRAM
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dram_size = init_DRAM(1, (void *)BT0_head.prvt_head.dram_para);
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dram_size = init_DRAM(BT0_head.boot_head.platform[7]); // ³õʼ»¯DRAM
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//dram_size = init_DRAM(1, (void *)&BT0_head.prvt_head.dram_para);
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if(dram_size)
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{
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msg("dram size =%d\n", dram_size);
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@ -34,7 +34,7 @@
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#define __init_DRAM_h
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extern __s32 init_DRAM( int type, void *buff );
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extern __s32 init_DRAM( int type );
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Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -1,94 +0,0 @@
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#ifndef _MCTL_HAL_H
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#define _MCTL_HAL_H
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typedef struct __DRAM_PARA
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{
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//normal configuration
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//unsigned int dram_baseaddr; //dram_baseaddr 0x40000000
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unsigned int dram_clk; //dram_clk DDR2: 24 LPDDR2: 120
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unsigned int dram_type; //dram_type DDR2: 2 DDR3: 3 LPDDR2: 6
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//unsigned int dram_cas;
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unsigned int dram_zq;
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unsigned int dram_odt_en;
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//control configuration
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unsigned int dram_para1;
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/******************************************************************************************
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* dram_para1 bit x definition
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* bit 31:28 bank_size: 0: 4 banks 1: 8 banks
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* bit 27:20 row_num: n: n rows
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* bit 19:16 page_size: 2: 2KByte 4: 4KByte 8: 8KByte
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* bit 15:0 dram_size: n: n MByte
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******************************************************************************************/
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unsigned int dram_para2;
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/******************************************************************************************
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* dram_para2 bit x definition
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* bit 15:12 rank_num: 1: 1 rank 2: 2 ranks
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* bit 11:8 ch_num: 1: 1 channel 2: 2 channel
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* bit 7:4 access mode: 0: sequence 1: interleave
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* bit 3:0 bus_width: 0: 16-bit 1: 32-bit
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******************************************************************************************/
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//timing configuration
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unsigned int dram_mr0;
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unsigned int dram_mr1;
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unsigned int dram_mr2;
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unsigned int dram_mr3;
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unsigned int dram_tpr0; //[31:0]tzqcsi
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unsigned int dram_tpr1; //[31:22]texsr [21:12]tdpd [11:2]tzqcl [1:0]tprea
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unsigned int dram_tpr2; //[31:23]trfc [22:15]trefi [14:7]tmrr [6:0]tzqcs
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unsigned int dram_tpr3; //[31:25]trstl [24:19]tras [18:13]trc [12:7]txpdll
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//[6:3]trp [2:0]tmrd
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unsigned int dram_tpr4; //[31:27]tcksre [26:22]tcksrx [21:17]tcke [16:12]tmod
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//[11:8]trtw [7:4]tal [3:0]tcl
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unsigned int dram_tpr5; //[31:28]tcwl [27:24]trcd [23:20]trrd [19:16]trtp
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//[15:12]twr [11:8]twtr [7:4]tckesr [3:1]txp
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unsigned int dram_tpr6; //[31:29]tdqs
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//reserved for future use
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unsigned int dram_tpr7;
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unsigned int dram_tpr8;
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unsigned int dram_tpr9;
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unsigned int dram_tpr10;
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unsigned int dram_tpr11;
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unsigned int dram_tpr12;
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//debug only
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unsigned int dram_tpr13;
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/******************************************************************************************
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* dram_dbg bit x definition [default value]
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* bit 6 DRAM base address [0]: 0: 0x40000000 1: user definition
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* bit 5 2T mode enable [0]: 0: 2T mode disable 1: 2T mode enable
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* bit 4:3 bonding ID [00]: 00: A31 01: A31S
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* 10: A3x PHONE 11: reserved
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* bit 2 bus width lock [1]: 0: auto detect 1: user lock
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* bit 1 channel lock [1]: 0: auto detect 1: user lock
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* bit 0 timing parameters setup [1]: 0: auto detect 1: user definition
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******************************************************************************************/
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}__dram_para_t;
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extern unsigned int DRAMC_init(__dram_para_t *para);
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extern unsigned int DRAMC_init_auto(__dram_para_t *para);
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//extern unsigned int mctl_parameter(__dram_para_t *para);
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extern unsigned int mctl_sys_init(void);
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extern unsigned int mctl_reset_release(void);
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extern unsigned int mctl_dll_init(unsigned int ch_index, __dram_para_t *para);
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extern unsigned int mctl_channel_init(unsigned int ch_index, __dram_para_t *para);
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extern unsigned int mctl_com_init(__dram_para_t *para);
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extern unsigned int mctl_port_cfg(void);
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//extern unsigned int DRAMC_init_EX(__dram_para_t *para);
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extern unsigned int ss_bonding_id(void);
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extern void paraconfig(unsigned int *para, unsigned int mask, unsigned int value);
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#endif //_MCTL_HAL_H
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@ -1,252 +0,0 @@
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#ifndef _MCTL_REG_H
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#define _MCTL_REG_H
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//DRAMC base address definition
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#define MCTL_COM_BASE 0x01c62000
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#define MCTL_CTL_BASE 0x01c63000
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#define MCTL_PHY_BASE 0x01c65000
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#define MCTL_RAM_BASE 0x01c64000
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//#define MCTL_CTL0 0x01c63000
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//#define MCTL_CTL1 0x01c64000
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//#define MCTL_PHY0 0x01c65000
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//#define MCTL_PHY1 0x01c66000
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#define SDR_COM_CR (MCTL_COM_BASE + 0x00)
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#define SDR_COM_CCR (MCTL_COM_BASE + 0x04)
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#define SDR_COM_DBGCR (MCTL_COM_BASE + 0x08)
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#define SDR_COM_DBGCR1 (MCTL_COM_BASE + 0x0c)
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#define SDR_COM_RMCR (MCTL_COM_BASE + 0x10)
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#define SDR_COM_MMCR (MCTL_COM_BASE + 0x30)
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#define SDR_COM_MBAGCR (MCTL_COM_BASE + 0x70)
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#define SDR_COM_MBACR (MCTL_COM_BASE + 0x74)
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#define SDR_COM_MAER (MCTL_COM_BASE + 0x88)
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#define SDR_COM_MDFSCR (MCTL_COM_BASE + 0x100)
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#define SDR_COM_MDFSMER (MCTL_COM_BASE + 0x104)
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#define SDR_COM_MDFSMRMR (MCTL_COM_BASE + 0x108)
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#define SDR_COM_MDFSTR0 (MCTL_COM_BASE + 0x10c)
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#define SDR_COM_MDFSTR1 (MCTL_COM_BASE + 0x110)
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#define SDR_COM_MDFSTR2 (MCTL_COM_BASE + 0x114)
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#define SDR_COM_MDFSTR3 (MCTL_COM_BASE + 0x118)
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#define SDR_COM_MDFSGCR (MCTL_COM_BASE + 0x11c)
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#define SDR_COM_MDFSIVR (MCTL_COM_BASE + 0x13c)
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#define SDR_COM_MDFSTCR (MCTL_COM_BASE + 0x14c)
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#define SDR_SCTL (MCTL_CTL_BASE + 0x04)
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#define SDR_SSTAT (MCTL_CTL_BASE + 0x08)
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#define SDR_MCMD (MCTL_CTL_BASE + 0x40)
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#define SDR_CMDSTAT (MCTL_CTL_BASE + 0x4c)
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#define SDR_CMDSTATEN (MCTL_CTL_BASE + 0x50)
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#define SDR_MRRCFG0 (MCTL_CTL_BASE + 0x60)
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#define SDR_MRRSTAT0 (MCTL_CTL_BASE + 0x64)
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#define SDR_MRRSTAT1 (MCTL_CTL_BASE + 0x68)
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#define SDR_MCFG1 (MCTL_CTL_BASE + 0x7c)
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#define SDR_MCFG (MCTL_CTL_BASE + 0x80)
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#define SDR_PPCFG (MCTL_CTL_BASE + 0x84)
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#define SDR_MSTAT (MCTL_CTL_BASE + 0x88)
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#define SDR_LP2ZQCFG (MCTL_CTL_BASE + 0x8c)
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#define SDR_DTUSTAT (MCTL_CTL_BASE + 0x94)
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#define SDR_DTUNA (MCTL_CTL_BASE + 0x98)
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#define SDR_DTUNE (MCTL_CTL_BASE + 0x9c)
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#define SDR_DTUPRD0 (MCTL_CTL_BASE + 0xa0)
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#define SDR_DTUPRD1 (MCTL_CTL_BASE + 0xa4)
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#define SDR_DTUPRD2 (MCTL_CTL_BASE + 0xa8)
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#define SDR_DTUPRD3 (MCTL_CTL_BASE + 0xac)
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#define SDR_DTUAWDT (MCTL_CTL_BASE + 0xb0)
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#define SDR_TOGCNT1U (MCTL_CTL_BASE + 0xc0)
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#define SDR_TOGCNT100N (MCTL_CTL_BASE + 0xcc)
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#define SDR_TREFI (MCTL_CTL_BASE + 0xd0)
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#define SDR_TMRD (MCTL_CTL_BASE + 0xd4)
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#define SDR_TRFC (MCTL_CTL_BASE + 0xd8)
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#define SDR_TRP (MCTL_CTL_BASE + 0xdc)
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#define SDR_TRTW (MCTL_CTL_BASE + 0xe0)
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#define SDR_TAL (MCTL_CTL_BASE + 0xe4)
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#define SDR_TCL (MCTL_CTL_BASE + 0xe8)
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#define SDR_TCWL (MCTL_CTL_BASE + 0xec)
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#define SDR_TRAS (MCTL_CTL_BASE + 0xf0)
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#define SDR_TRC (MCTL_CTL_BASE + 0xf4)
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#define SDR_TRCD (MCTL_CTL_BASE + 0xf8)
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#define SDR_TRRD (MCTL_CTL_BASE + 0xfc)
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#define SDR_TRTP (MCTL_CTL_BASE + 0x100)
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#define SDR_TWR (MCTL_CTL_BASE + 0x104)
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#define SDR_TWTR (MCTL_CTL_BASE + 0x108)
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#define SDR_TEXSR (MCTL_CTL_BASE + 0x10c)
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#define SDR_TXP (MCTL_CTL_BASE + 0x110)
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#define SDR_TXPDLL (MCTL_CTL_BASE + 0x114)
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#define SDR_TZQCS (MCTL_CTL_BASE + 0x118)
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#define SDR_TZQCSI (MCTL_CTL_BASE + 0x11c)
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#define SDR_TDQS (MCTL_CTL_BASE + 0x120)
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#define SDR_TCKSRE (MCTL_CTL_BASE + 0x124)
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#define SDR_TCKSRX (MCTL_CTL_BASE + 0x128)
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#define SDR_TCKE (MCTL_CTL_BASE + 0x12c)
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#define SDR_TMOD (MCTL_CTL_BASE + 0x130)
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#define SDR_TRSTL (MCTL_CTL_BASE + 0x134)
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#define SDR_TZQCL (MCTL_CTL_BASE + 0x138)
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#define SDR_TMRR (MCTL_CTL_BASE + 0x13c)
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#define SDR_TCKESR (MCTL_CTL_BASE + 0x140)
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#define SDR_TDPD (MCTL_CTL_BASE + 0x144)
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#define SDR_DTUWACTL (MCTL_CTL_BASE + 0x200)
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#define SDR_DTURACTL (MCTL_CTL_BASE + 0x204)
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#define SDR_DTUCFG (MCTL_CTL_BASE + 0x208)
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#define SDR_DTUECTL (MCTL_CTL_BASE + 0x20c)
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#define SDR_DTUWD0 (MCTL_CTL_BASE + 0x210)
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#define SDR_DTUWD1 (MCTL_CTL_BASE + 0x214)
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#define SDR_DTUWD2 (MCTL_CTL_BASE + 0x218)
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#define SDR_DTUWD3 (MCTL_CTL_BASE + 0x21c)
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#define SDR_DTUWDM (MCTL_CTL_BASE + 0x220)
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#define SDR_DTURD0 (MCTL_CTL_BASE + 0x224)
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#define SDR_DTURD1 (MCTL_CTL_BASE + 0x224)
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#define SDR_DTURD2 (MCTL_CTL_BASE + 0x22c)
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#define SDR_DTURD3 (MCTL_CTL_BASE + 0x230)
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#define SDR_DTULFSRWD (MCTL_CTL_BASE + 0x234)
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#define SDR_DTULFSRRD (MCTL_CTL_BASE + 0x238)
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#define SDR_DTUEAF (MCTL_CTL_BASE + 0x23c)
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#define SDR_DFITCTLDLY (MCTL_CTL_BASE + 0x240)
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#define SDR_DFIODTCFG (MCTL_CTL_BASE + 0x244)
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#define SDR_DFIODTCFG1 (MCTL_CTL_BASE + 0x248)
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#define SDR_DFIODTRMAP (MCTL_CTL_BASE + 0x24c)
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#define SDR_DFITPHYWRD (MCTL_CTL_BASE + 0x250)
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#define SDR_DFITPHYWRL (MCTL_CTL_BASE + 0x254)
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#define SDR_DFITRDDEN (MCTL_CTL_BASE + 0x260)
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#define SDR_DFITPHYRDL (MCTL_CTL_BASE + 0x264)
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#define SDR_DFITPHYUPDTYPE0 (MCTL_CTL_BASE + 0x270)
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#define SDR_DFITPHYUPDTYPE1 (MCTL_CTL_BASE + 0x274)
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#define SDR_DFITPHYUPDTYPE2 (MCTL_CTL_BASE + 0x278)
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#define SDR_DFITPHYUPDTYPE3 (MCTL_CTL_BASE + 0x27c)
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#define SDR_DFITCTRLUPDMIN (MCTL_CTL_BASE + 0x280)
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#define SDR_DFITCTRLUPDMAX (MCTL_CTL_BASE + 0x284)
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#define SDR_DFITCTRLUPDDLY (MCTL_CTL_BASE + 0x288)
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#define SDR_DFIUPDCFG (MCTL_CTL_BASE + 0x290)
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#define SDR_DFITREFMSKI (MCTL_CTL_BASE + 0x294)
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#define SDR_DFITCRLUPDI (MCTL_CTL_BASE + 0x298)
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#define SDR_DFITRCFG0 (MCTL_CTL_BASE + 0x2ac)
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#define SDR_DFITRSTAT0 (MCTL_CTL_BASE + 0x2b0)
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#define SDR_DFITRWRLVLEN (MCTL_CTL_BASE + 0x2b4)
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#define SDR_DFITRRDLVLEN (MCTL_CTL_BASE + 0x2b8)
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#define SDR_DFITRRDLVLGATEEN (MCTL_CTL_BASE + 0x2bc)
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#define SDR_DFISTCFG0 (MCTL_CTL_BASE + 0x2c4)
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#define SDR_DFISTCFG1 (MCTL_CTL_BASE + 0x2c8)
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#define SDR_DFITDRAMCLKEN (MCTL_CTL_BASE + 0x2d0)
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#define SDR_DFITDRAMCLKDIS (MCTL_CTL_BASE + 0x2d4)
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#define SDR_DFILPCFG0 (MCTL_CTL_BASE + 0x2f0)
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#define SDR_PIR (MCTL_PHY_BASE + 0x04)
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#define SDR_PGCR (MCTL_PHY_BASE + 0x08)
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#define SDR_PGSR (MCTL_PHY_BASE + 0x0c)
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#define SDR_DLLGCR (MCTL_PHY_BASE + 0x10)
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#define SDR_ACDLLCR (MCTL_PHY_BASE + 0x14)
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#define SDR_PTR0 (MCTL_PHY_BASE + 0x18)
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#define SDR_PTR1 (MCTL_PHY_BASE + 0x1c)
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#define SDR_PTR2 (MCTL_PHY_BASE + 0x20)
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#define SDR_ACIOCR (MCTL_PHY_BASE + 0x24)
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#define SDR_DXCCR (MCTL_PHY_BASE + 0x28)
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#define SDR_DSGCR (MCTL_PHY_BASE + 0x2c)
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#define SDR_DCR (MCTL_PHY_BASE + 0x30)
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#define SDR_DTPR0 (MCTL_PHY_BASE + 0x34)
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#define SDR_DTPR1 (MCTL_PHY_BASE + 0x38)
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#define SDR_DTPR2 (MCTL_PHY_BASE + 0x3c)
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#define SDR_MR0 (MCTL_PHY_BASE + 0x40)
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#define SDR_MR1 (MCTL_PHY_BASE + 0x44)
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#define SDR_MR2 (MCTL_PHY_BASE + 0x48)
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#define SDR_MR3 (MCTL_PHY_BASE + 0x4c)
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#define SDR_ODTCR (MCTL_PHY_BASE + 0x50)
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#define SDR_DTAR (MCTL_PHY_BASE + 0x54)
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#define SDR_DTDT0 (MCTL_PHY_BASE + 0x58)
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#define SDR_DTDT1 (MCTL_PHY_BASE + 0x5c)
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#define SDR_DCUAR (MCTL_PHY_BASE + 0xc0)
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#define SDR_DCUDR (MCTL_PHY_BASE + 0xc4)
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#define SDR_DCURR (MCTL_PHY_BASE + 0xc8)
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#define SDR_DCULR (MCTL_PHY_BASE + 0xcc)
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#define SDR_DCUGCR (MCTL_PHY_BASE + 0xd0)
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#define SDR_DCUTPR (MCTL_PHY_BASE + 0xd4)
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#define SDR_DCUSR0 (MCTL_PHY_BASE + 0xd8)
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#define SDR_DCUSR1 (MCTL_PHY_BASE + 0xdc)
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#define SDR_BISTRR (MCTL_PHY_BASE + 0x100)
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#define SDR_BISTMSKR0 (MCTL_PHY_BASE + 0x104)
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#define SDR_BISTMSKR1 (MCTL_PHY_BASE + 0x108)
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#define SDR_BISTWCR (MCTL_PHY_BASE + 0x10c)
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#define SDR_BISTLSR (MCTL_PHY_BASE + 0x110)
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#define SDR_BISTAR0 (MCTL_PHY_BASE + 0x114)
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#define SDR_BISTAR1 (MCTL_PHY_BASE + 0x118)
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#define SDR_BISTAR2 (MCTL_PHY_BASE + 0x11c)
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#define SDR_BISTUDPR (MCTL_PHY_BASE + 0x120)
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#define SDR_BISTGSR (MCTL_PHY_BASE + 0x124)
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#define SDR_BISTWER (MCTL_PHY_BASE + 0x128)
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#define SDR_BISTBER0 (MCTL_PHY_BASE + 0x12c)
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#define SDR_BISTBER1 (MCTL_PHY_BASE + 0x130)
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#define SDR_BISTBER2 (MCTL_PHY_BASE + 0x134)
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#define SDR_BISTWCSR (MCTL_PHY_BASE + 0x138)
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#define SDR_BISTFWR0 (MCTL_PHY_BASE + 0x13c)
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#define SDR_BISTFWR1 (MCTL_PHY_BASE + 0x140)
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#define SDR_ZQ0CR0 (MCTL_PHY_BASE + 0x180)
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#define SDR_ZQ0CR1 (MCTL_PHY_BASE + 0x184)
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#define SDR_ZQ0SR0 (MCTL_PHY_BASE + 0x188)
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#define SDR_ZQ0SR1 (MCTL_PHY_BASE + 0x18c)
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#define SDR_DX0GCR (MCTL_PHY_BASE + 0x1c0)
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#define SDR_DX0GSR0 (MCTL_PHY_BASE + 0x1c4)
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#define SDR_DX0GSR1 (MCTL_PHY_BASE + 0x1c8)
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#define SDR_DX0DLLCR (MCTL_PHY_BASE + 0x1cc)
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#define SDR_DX0DQTR (MCTL_PHY_BASE + 0x1d0)
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#define SDR_DX0DQSTR (MCTL_PHY_BASE + 0x1d4)
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#define SDR_DX1GCR (MCTL_PHY_BASE + 0x200)
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#define SDR_DX1GSR0 (MCTL_PHY_BASE + 0x204)
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#define SDR_DX1GSR1 (MCTL_PHY_BASE + 0x208)
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#define SDR_DX1DLLCR (MCTL_PHY_BASE + 0x20c)
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#define SDR_DX1DQTR (MCTL_PHY_BASE + 0x210)
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#define SDR_DX1DQSTR (MCTL_PHY_BASE + 0x214)
|
||||
#define SDR_DX2GCR (MCTL_PHY_BASE + 0x240)
|
||||
#define SDR_DX2GSR0 (MCTL_PHY_BASE + 0x244)
|
||||
#define SDR_DX2GSR1 (MCTL_PHY_BASE + 0x248)
|
||||
#define SDR_DX2DLLCR (MCTL_PHY_BASE + 0x24c)
|
||||
#define SDR_DX2DQTR (MCTL_PHY_BASE + 0x250)
|
||||
#define SDR_DX2DQSTR (MCTL_PHY_BASE + 0x254)
|
||||
#define SDR_DX3GCR (MCTL_PHY_BASE + 0x280)
|
||||
#define SDR_DX3GSR0 (MCTL_PHY_BASE + 0x284)
|
||||
#define SDR_DX3GSR1 (MCTL_PHY_BASE + 0x288)
|
||||
#define SDR_DX3DLLCR (MCTL_PHY_BASE + 0x28c)
|
||||
#define SDR_DX3DQTR (MCTL_PHY_BASE + 0x290)
|
||||
#define SDR_DX3DQSTR (MCTL_PHY_BASE + 0x294)
|
||||
|
||||
#ifndef CCM_BASE
|
||||
#define CCM_BASE (0x01c20000)
|
||||
#endif
|
||||
|
||||
#ifndef CCM_PLL5_DDR_CTRL
|
||||
#define CCM_PLL5_DDR_CTRL (CCM_BASE+0x020)
|
||||
#endif
|
||||
|
||||
#ifndef CCM_MDFS_CLK_CTRL
|
||||
#define CCM_MDFS_CLK_CTRL (CCM_BASE+0x0f0)
|
||||
#endif
|
||||
|
||||
#ifndef CCM_DRAMCLK_CFG_CTRL
|
||||
#define CCM_DRAMCLK_CFG_CTRL (CCM_BASE+0x0f4)
|
||||
#endif
|
||||
|
||||
#ifndef CCM_AHB1_RST_REG0
|
||||
#define CCM_AHB1_RST_REG0 (CCM_BASE+0x02C0)
|
||||
#endif
|
||||
|
||||
#ifndef CCM_AHB1_GATE0_CTRL
|
||||
#define CCM_AHB1_GATE0_CTRL (CCM_BASE+0x060)
|
||||
#endif
|
||||
|
||||
#ifndef R_PRCM_BASE
|
||||
#define R_PRCM_BASE (0x01f01400)
|
||||
#endif
|
||||
|
||||
#ifndef R_VDD_SYS_PWROFF_GATE
|
||||
#define R_VDD_SYS_PWROFF_GATE (R_PRCM_BASE + 0x110)
|
||||
#endif
|
||||
|
||||
#ifndef CCM_AXI_GATE_CTRL
|
||||
#define CCM_AXI_GATE_CTRL (CCM_BASE+0x05c)
|
||||
#endif
|
||||
|
||||
|
||||
#define mctl_read_w(n) (*((volatile unsigned int *)(n)))
|
||||
#define mctl_write_w(n,c) (*((volatile unsigned int *)(n)) = (c))
|
||||
|
||||
#endif //_MCTL_REG_H
|
||||
@ -782,7 +782,7 @@ int mmc_startup(struct mmc *mmc)
|
||||
{
|
||||
int err;
|
||||
u32 mult, freq;
|
||||
u64 cmult, csize, capacity;
|
||||
unsigned long long cmult, csize, capacity;
|
||||
struct mmc_cmd cmd;
|
||||
char ext_csd[512];
|
||||
int timeout = 1000;
|
||||
|
||||
@ -165,7 +165,7 @@ static int mmc_clk_io_onoff(int sdc_no, int onoff)
|
||||
u32 n, k, m;
|
||||
u32 gpioc_base = 0x01c20800 + 0x48;
|
||||
u32 gpiof_base = 0x01c20800 + 0xb4;
|
||||
u32 pll5_base = CCMU_PLL5_CLK_BASE;
|
||||
// u32 pll5_base = CCMU_PLL5_CLK_BASE;
|
||||
|
||||
mmcdbg("init mmc %d clock and io\n", sdc_no);
|
||||
/* config gpio */
|
||||
@ -211,26 +211,18 @@ static int mmc_clk_io_onoff(int sdc_no, int onoff)
|
||||
rval &= ~(1 << (8 + sdc_no));
|
||||
writel(rval, mmchost->hclkbase);
|
||||
/* release reset */
|
||||
/*
|
||||
rval = readl(mmchost->hclkrst);
|
||||
if (onoff)
|
||||
rval |= (1 << (8 + sdc_no));
|
||||
else
|
||||
rval &= ~(1 << (8 + sdc_no));
|
||||
writel(rval, mmchost->hclkrst);
|
||||
|
||||
*/
|
||||
/* config mod clock */
|
||||
if (onoff) {
|
||||
rval = readl(pll5_base);
|
||||
n = (rval >> 8) & 0x1f;
|
||||
k = ((rval >> 4) & 3) + 1;
|
||||
m = (rval & 3) + 1;
|
||||
pll5_clk = 24 * n * k / m;
|
||||
divider = (pll5_clk + 25) / 50 - 1;
|
||||
|
||||
mmcdbg("init mmc n %d, k %d, m %d, pll5clk %d, mbase %x\n", n, k, m, pll5_clk, mmchost->mclkbase);
|
||||
writel((1U << 31) | (2U << 24) | divider, mmchost->mclkbase);
|
||||
mmchost->mclk = pll5_clk * 1000000 / (divider + 1);
|
||||
mmcdbg("init mmc mclk %d\n", mmchost->mclk);
|
||||
writel(0x80100100, mmchost->mclkbase);
|
||||
mmchost->mclk = 24000000;
|
||||
} else {
|
||||
writel(0, mmchost->mclkbase);
|
||||
}
|
||||
@ -258,10 +250,11 @@ static int mmc_update_clk(struct mmc *mmc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mmc_config_clock(struct mmc *mmc, unsigned div)
|
||||
static int mmc_config_clock(struct mmc *mmc, unsigned clk)
|
||||
{
|
||||
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
|
||||
unsigned rval = readl(&mmchost->reg->clkcr);
|
||||
unsigned int clkdiv = 0;
|
||||
|
||||
/*
|
||||
* CLKCREG[7:0]: divider
|
||||
@ -273,14 +266,29 @@ static int mmc_config_clock(struct mmc *mmc, unsigned div)
|
||||
writel(rval, &mmchost->reg->clkcr);
|
||||
if(mmc_update_clk(mmc))
|
||||
return -1;
|
||||
|
||||
clkdiv = mmchost->mclk/clk/2;
|
||||
if (clk <=400000) {
|
||||
mmchost->mclk = 400000;
|
||||
writel(0x8012010f, mmchost->mclkbase);
|
||||
} else {
|
||||
mmchost->mclk = 24000000;
|
||||
writel(0x80100101, mmchost->mclkbase);
|
||||
//writel(0x80700001, mmchost->mclkbase);
|
||||
}
|
||||
|
||||
/*
|
||||
* CLKCREG[7:0]: divider
|
||||
* CLKCREG[16]: on/off
|
||||
* CLKCREG[17]: power save
|
||||
*/
|
||||
/* Change Divider Factor */
|
||||
rval &= ~(0xFF);
|
||||
rval |= div;
|
||||
writel(rval, &mmchost->reg->clkcr);
|
||||
if(mmc_update_clk(mmc))
|
||||
return -1;
|
||||
/* Re-enable Clock */
|
||||
rval |= (1 << 16);
|
||||
rval |= (3 << 16);
|
||||
writel(rval, &mmchost->reg->clkcr);
|
||||
if(mmc_update_clk(mmc))
|
||||
return -1;
|
||||
@ -290,17 +298,14 @@ static int mmc_config_clock(struct mmc *mmc, unsigned div)
|
||||
static void mmc_set_ios(struct mmc *mmc)
|
||||
{
|
||||
struct sunxi_mmc_host* mmchost = (struct sunxi_mmc_host *)mmc->priv;
|
||||
unsigned int clkdiv = 0;
|
||||
|
||||
|
||||
mmcdbg("ios: bus: %d, clock: %d\n", mmc->bus_width, mmc->clock);
|
||||
|
||||
/* Change clock first */
|
||||
clkdiv = (mmchost->mclk + (mmc->clock>>1))/mmc->clock/2;
|
||||
if (mmc->clock)
|
||||
if (mmc_config_clock(mmc, clkdiv)) {
|
||||
mmchost->fatal_err = 1;
|
||||
return;
|
||||
}
|
||||
if (mmc->clock && mmc_config_clock(mmc, mmc->clock)) {
|
||||
msg("[mmc]: " "*** update clock failed\n");
|
||||
mmchost->fatal_err = 1;
|
||||
}
|
||||
/* Change bus width */
|
||||
if (mmc->bus_width == 8)
|
||||
writel(2, &mmchost->reg->width);
|
||||
@ -608,8 +613,8 @@ int sunxi_mmc_init(int sdc_no, unsigned bus_width)
|
||||
struct mmc *mmc;
|
||||
int ret;
|
||||
|
||||
memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc)*MAX_MMC_NUM);
|
||||
memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)*MAX_MMC_NUM);
|
||||
memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc));
|
||||
memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
|
||||
mmc = &mmc_dev[sdc_no];
|
||||
|
||||
strcpy(mmc->name, "SUNXI SD/MMC");
|
||||
@ -624,8 +629,8 @@ int sunxi_mmc_init(int sdc_no, unsigned bus_width)
|
||||
if (bus_width==4)
|
||||
mmc->host_caps |= MMC_MODE_4BIT;
|
||||
|
||||
mmc->f_min = 300000;
|
||||
mmc->f_max = 52000000;
|
||||
mmc->f_min = 400000;
|
||||
mmc->f_max = 25000000;
|
||||
|
||||
mmc_host[sdc_no].pdes = (struct sunxi_mmc_des*)0x42000000;
|
||||
if (mmc_resource_init(sdc_no))
|
||||
|
||||
@ -13,7 +13,7 @@
|
||||
#include "boot0_i.h"
|
||||
#include <string.h>
|
||||
|
||||
#define MMC_SUN6I
|
||||
#define MMC_SUN7I
|
||||
#define MAX_MMC_NUM 4
|
||||
#define MMC_TRANS_BY_DMA
|
||||
//#define MMC_DEBUG
|
||||
|
||||
@ -44,7 +44,7 @@ INCLUDES := $(INCLUDES) \
|
||||
$(foreach dir,$(SRCDIRS),-I$(dir))
|
||||
|
||||
|
||||
ifeq ($(CROSSTOOL), ARMRVDS)
|
||||
ifeq ($(CROSSTOOL), GCC)
|
||||
|
||||
#===============================================================================
|
||||
#使用RVDS编译器
|
||||
|
||||
@ -54,7 +54,7 @@ INCLUDES := $(INCLUDES) \
|
||||
$(foreach dir,$(SRCDIRS),-I$(dir))
|
||||
|
||||
|
||||
ifeq ($(CROSSTOOL), ARMRVDS)
|
||||
ifeq ($(CROSSTOOL), GCC)
|
||||
|
||||
#===============================================================================
|
||||
#使用RVDS编译器
|
||||
|
||||
@ -81,7 +81,7 @@ INCLUDES := $(INCLUDES) \
|
||||
$(foreach dir,$(SRCDIRS),-I$(dir))
|
||||
|
||||
|
||||
ifeq ($(CROSSTOOL), ARMRVDS)
|
||||
ifeq ($(CROSSTOOL), GCC)
|
||||
|
||||
#===============================================================================
|
||||
#使用RVDS编译器
|
||||
|
||||
@ -45,7 +45,7 @@ LOCALTARGET = eGon2_ui.lib
|
||||
|
||||
#扩展交叉编译工具的参数配置
|
||||
|
||||
ifeq ($(CROSSTOOL), ARMRVDS)
|
||||
ifeq ($(CROSSTOOL), GCC)
|
||||
|
||||
#===============================================================================
|
||||
#使用RVDS编译器
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@ -45,7 +45,7 @@ LOCALTARGET = eGon2_libc.lib
|
||||
|
||||
#扩展交叉编译工具的参数配置
|
||||
|
||||
ifeq ($(CROSSTOOL), ARMRVDS)
|
||||
ifeq ($(CROSSTOOL), GCC)
|
||||
|
||||
#===============================================================================
|
||||
#使用RVDS编译器
|
||||
|
||||
@ -19,13 +19,13 @@
|
||||
#
|
||||
|
||||
#工具链配置
|
||||
CROSSTOOL = ARMRVDS
|
||||
CROSSTOOL = GCC
|
||||
|
||||
WORKSPACEPATH = $(SDKROOT)/workspace
|
||||
WORKTOOLS = $(SDKROOT)/workspace/pctools
|
||||
LIBSPATH = $(SDKROOT)/boot1/libs
|
||||
|
||||
ifeq ($(CROSSTOOL), ARMRVDS)
|
||||
ifeq ($(CROSSTOOL), GCC)
|
||||
|
||||
#===============================================================
|
||||
#RVDS编译器参数配置
|
||||
@ -69,32 +69,43 @@ LDFLAGS =
|
||||
else
|
||||
|
||||
|
||||
ifeq ($(CROSSTOOL), ARMGCC)
|
||||
ifeq ($(CROSSTOOL), ARMCC)
|
||||
|
||||
#===============================================================
|
||||
#GNU编译器参数配置
|
||||
#===============================================================
|
||||
|
||||
#编译器
|
||||
CC = @arm-elf-gcc
|
||||
|
||||
CC = @armcc
|
||||
#编译器参数
|
||||
CFLAGS =
|
||||
CFLAGS = --cpu=Cortex-A8.no_neon
|
||||
|
||||
#C++编译器
|
||||
CXX = @armcpp
|
||||
CXXFLAGS = --cpu=Cortex-A8.no_neon --cpp --no_exceptions
|
||||
|
||||
#汇编器
|
||||
AS = @arm-elf-as
|
||||
AS = @armasm
|
||||
#汇编器参数
|
||||
ASFLAGS =
|
||||
ASFLAGS = --cpu=Cortex-A8.no_neon
|
||||
|
||||
#链接器
|
||||
LINK = @arm-elf-ld
|
||||
LINK = armlink
|
||||
#链接器参数
|
||||
LKFLAGS =
|
||||
LKFLAGS = --noremove
|
||||
|
||||
#打包器
|
||||
AR = armar
|
||||
#链接器参数
|
||||
ARFLAGS = -r
|
||||
|
||||
#加载器
|
||||
LOAD = @arm-elf-objdump
|
||||
LOAD = fromelf
|
||||
#加载器参数
|
||||
LDFLAGS =
|
||||
|
||||
|
||||
else
|
||||
|
||||
error:
|
||||
|
||||
Binary file not shown.
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Loading…
x
Reference in New Issue
Block a user