mirror of
https://github.com/joncampbell123/dosbox-x.git
synced 2025-05-08 19:32:39 +08:00
Cleanup VGA other code
This commit is contained in:
Jonathan Campbell
parent
4c67f61244
commit
223342c2a8
@ -943,6 +943,7 @@ static inline unsigned char *pc98_vram_256bank_from_window(const unsigned int b)
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bool J3_IsCga4Dcga();
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void UpdateCGAFromSaveState(void);
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void INT10_PC98_CurMode_Relocate(void);
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unsigned int VGA_ComplexityCheck_ODDEVEN(void);
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void VGA_VsyncUpdateMode(VGA_Vsync vsyncmode);
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uint32_t GetReportedVideoMemorySize(void);
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extern void VGA_TweakUserVsyncOffset(float val);
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@ -28,233 +28,223 @@
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static bool index9warned=false;
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static void write_p3ce(Bitu port,Bitu val,Bitu iolen) {
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(void)port;//UNUSED
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(void)iolen;//UNUSED
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static void write_p3ce(Bitu /*port*/,Bitu val,Bitu /*iolen*/) {
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gfx(index)=val & 0x0f;
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}
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static Bitu read_p3ce(Bitu port,Bitu iolen) {
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(void)port;//UNUSED
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(void)iolen;//UNUSED
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static Bitu read_p3ce(Bitu /*port*/,Bitu /*iolen*/) {
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return gfx(index);
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}
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unsigned int VGA_ComplexityCheck_ODDEVEN(void);
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static void write_p3cf(Bitu port,Bitu val,Bitu iolen) {
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static void write_p3cf(Bitu /*port*/,Bitu val,Bitu iolen) {
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unsigned int cmplx = 0;
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(void)port;//UNUSED
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(void)iolen;//UNUSED
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switch (gfx(index)) {
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case 0: /* Set/Reset Register */
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gfx(set_reset)=val & 0x0f;
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vga.config.full_set_reset=FillTable[val & 0x0f];
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vga.config.full_enable_and_set_reset=vga.config.full_set_reset &
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vga.config.full_enable_set_reset;
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/*
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0 If in Write Mode 0 and bit 0 of 3CEh index 1 is set a write to
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display memory will set all the bits in plane 0 of the byte to this
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bit, if the corresponding bit is set in the Map Mask Register (3CEh
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index 8).
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1 Same for plane 1 and bit 1 of 3CEh index 1.
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2 Same for plane 2 and bit 2 of 3CEh index 1.
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3 Same for plane 3 and bit 3 of 3CEh index 1.
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*/
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// LOG_DEBUG("Set Reset = %2X",val);
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break;
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case 1: /* Enable Set/Reset Register */
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gfx(enable_set_reset)=val & 0x0f;
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vga.config.full_enable_set_reset=FillTable[val & 0x0f];
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vga.config.full_not_enable_set_reset=~vga.config.full_enable_set_reset;
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vga.config.full_enable_and_set_reset=vga.config.full_set_reset &
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vga.config.full_enable_set_reset;
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cmplx |= vga.complexity.setf(VGACMPLX_SETRESET,(val & 0xF) != 0);
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if (cmplx != 0) VGA_SetupHandlers();
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break;
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case 2: /* Color Compare Register */
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gfx(color_compare)=val & 0x0f;
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/*
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0-3 In Read Mode 1 each pixel at the address of the byte read is compared
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to this color and the corresponding bit in the output set to 1 if
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they match, 0 if not. The Color Don't Care Register (3CEh index 7)
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can exclude bitplanes from the comparison.
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*/
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vga.config.color_compare=val & 0xf;
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// LOG_DEBUG("Color Compare = %2X",val);
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break;
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case 3: /* Data Rotate */
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gfx(data_rotate)=(uint8_t)val;
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vga.config.data_rotate=(uint8_t)val & 7;
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vga.config.raster_op=((uint8_t)val>>3) & 3;
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cmplx |= vga.complexity.setf(VGACMPLX_ROPROT,vga.config.data_rotate != 0 || vga.config.raster_op != 0);
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if (cmplx != 0) VGA_SetupHandlers();
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/*
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0-2 Number of positions to rotate data right before it is written to
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display memory. Only active in Write Mode 0.
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3-4 In Write Mode 2 this field controls the relation between the data
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written from the CPU, the data latched from the previous read and the
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data written to display memory:
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0: CPU Data is written unmodified
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1: CPU data is ANDed with the latched data
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2: CPU data is ORed with the latch data.
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3: CPU data is XORed with the latched data.
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*/
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break;
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case 4: /* Read Map Select Register */
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/* 0-1 number of the plane Read Mode 0 will read from */
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gfx(read_map_select)=val & 0x03;
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vga.config.read_map_select=val & 0x03;
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// LOG_DEBUG("Read Map %2X",val);
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break;
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case 5: /* Mode Register */
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if ((gfx(mode) ^ val) & 0xf0) {
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gfx(mode)=(uint8_t)val;
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VGA_DetermineMode();
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cmplx |= VGA_ComplexityCheck_ODDEVEN();
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} else gfx(mode)=(uint8_t)val;
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vga.config.write_mode=(uint8_t)val & 3;
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vga.config.read_mode=((uint8_t)val >> 3) & 1;
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cmplx |= vga.complexity.setf(VGACMPLX_COLORDONTCARE,gfx(color_dont_care) != 0 && vga.config.read_mode == 1);
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cmplx |= vga.complexity.setf(VGACMPLX_WRITEMODE,vga.config.write_mode != 0);
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cmplx |= vga.complexity.setf(VGACMPLX_READMODE,vga.config.read_mode != 0);
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if (cmplx != 0) VGA_SetupHandlers();
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// LOG_DEBUG("Write Mode %d Read Mode %d val %d",vga.config.write_mode,vga.config.read_mode,val);
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/*
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0-1 Write Mode: Controls how data from the CPU is transformed before
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being written to display memory:
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0: Mode 0 works as a Read-Modify-Write operation.
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First a read access loads the data latches of the VGA with the
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value in video memory at the addressed location. Then a write
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access will provide the destination address and the CPU data
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byte. The data written is modified by the function code in the
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Data Rotate register (3CEh index 3) as a function of the CPU
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data and the latches, then data is rotated as specified by the
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same register.
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1: Mode 1 is used for video to video transfers.
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A read access will load the data latches with the contents of
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the addressed byte of video memory. A write access will write
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the contents of the latches to the addressed byte. Thus a single
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MOVSB instruction can copy all pixels in the source address byte
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to the destination address.
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2: Mode 2 writes a color to all pixels in the addressed byte of
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video memory. Bit 0 of the CPU data is written to plane 0 et
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cetera. Individual bits can be enabled or disabled through the
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Bit Mask register (3CEh index 8).
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3: Mode 3 can be used to fill an area with a color and pattern. The
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CPU data is rotated according to 3CEh index 3 bits 0-2 and anded
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with the Bit Mask Register (3CEh index 8). For each bit in the
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result the corresponding pixel is set to the color in the
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Set/Reset Register (3CEh index 0 bits 0-3) if the bit is set and
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to the contents of the processor latch if the bit is clear.
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3 Read Mode
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0: Data is read from one of 4 bit planes depending on the Read Map
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Select Register (3CEh index 4).
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1: Data returned is a comparison between the 8 pixels occupying the
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read byte and the color in the Color Compare Register (3CEh
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index 2). A bit is set if the color of the corresponding pixel
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matches the register.
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4 Enables Odd/Even mode if set (See 3C4h index 4 bit 2).
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5 Enables CGA style 4 color pixels using even/odd bit pairs if set.
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6 Enables 256 color mode if set.
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*/
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break;
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case 6: /* Miscellaneous Register */
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if ((gfx(miscellaneous) ^ val) & 0x0c) {
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gfx(miscellaneous)=(uint8_t)val;
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VGA_DetermineMode();
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} else gfx(miscellaneous)=(uint8_t)val;
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VGA_ComplexityCheck_ODDEVEN();
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VGA_SetupHandlers();
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/*
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0 Indicates Graphics Mode if set, Alphanumeric mode else.
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1 Enables Odd/Even mode if set.
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2-3 Memory Mapping:
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0: use A000h-BFFFh
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1: use A000h-AFFFh VGA Graphics modes
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2: use B000h-B7FFh Monochrome modes
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3: use B800h-BFFFh CGA modes
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*/
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break;
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case 7: /* Color Don't Care Register */
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gfx(color_dont_care)=val & 0x0f;
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cmplx |= vga.complexity.setf(VGACMPLX_COLORDONTCARE,gfx(color_dont_care) != 0 && vga.config.read_mode == 1);
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if (cmplx != 0) VGA_SetupHandlers();
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/*
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0 Ignore bit plane 0 in Read mode 1 if clear.
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1 Ignore bit plane 1 in Read mode 1 if clear.
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2 Ignore bit plane 2 in Read mode 1 if clear.
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3 Ignore bit plane 3 in Read mode 1 if clear.
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*/
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vga.config.color_dont_care=val & 0xf;
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// LOG_DEBUG("Color don't care = %2X",val);
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break;
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case 8: /* Bit Mask Register */
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gfx(bit_mask)=(uint8_t)val;
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vga.config.full_bit_mask=ExpandTable[val];
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cmplx |= vga.complexity.setf(VGACMPLX_BITMASK,vga.config.full_bit_mask != 0xFFFFFFFFu); // at least one bit will be masked off?
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/* check for unusual use of the bit mask register in chained 320x200x256 mode and switch to the slow & accurate emulation */
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if (vga.mode == M_VGA && vga.config.chained)
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VGA_SetupHandlers();
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else if (cmplx != 0)
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VGA_SetupHandlers();
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// LOG_DEBUG("Bit mask %2X",val);
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/*
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0-7 Each bit if set enables writing to the corresponding bit of a byte in
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display memory.
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*/
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break;
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default:
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if (svga.write_p3cf) {
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svga.write_p3cf(gfx(index), val, iolen);
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case 0: /* Set/Reset Register */
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gfx(set_reset)=val & 0x0f;
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vga.config.full_set_reset=FillTable[val & 0x0f];
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vga.config.full_enable_and_set_reset=vga.config.full_set_reset &
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vga.config.full_enable_set_reset;
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/*
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0 If in Write Mode 0 and bit 0 of 3CEh index 1 is set a write to
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display memory will set all the bits in plane 0 of the byte to this
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bit, if the corresponding bit is set in the Map Mask Register (3CEh
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index 8).
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1 Same for plane 1 and bit 1 of 3CEh index 1.
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2 Same for plane 2 and bit 2 of 3CEh index 1.
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3 Same for plane 3 and bit 3 of 3CEh index 1.
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*/
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// LOG_DEBUG("Set Reset = %2X",val);
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break;
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}
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if (gfx(index) == 9 && !index9warned) {
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LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:3CF:Write %2X to illegal index 9",(int)val);
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index9warned=true;
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case 1: /* Enable Set/Reset Register */
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gfx(enable_set_reset)=val & 0x0f;
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vga.config.full_enable_set_reset=FillTable[val & 0x0f];
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vga.config.full_not_enable_set_reset=~vga.config.full_enable_set_reset;
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vga.config.full_enable_and_set_reset=vga.config.full_set_reset &
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vga.config.full_enable_set_reset;
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cmplx |= vga.complexity.setf(VGACMPLX_SETRESET,(val & 0xF) != 0);
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if (cmplx != 0) VGA_SetupHandlers();
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break;
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case 2: /* Color Compare Register */
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gfx(color_compare)=val & 0x0f;
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/*
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0-3 In Read Mode 1 each pixel at the address of the byte read is compared
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to this color and the corresponding bit in the output set to 1 if
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they match, 0 if not. The Color Don't Care Register (3CEh index 7)
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can exclude bitplanes from the comparison.
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*/
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vga.config.color_compare=val & 0xf;
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// LOG_DEBUG("Color Compare = %2X",val);
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break;
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case 3: /* Data Rotate */
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gfx(data_rotate)=(uint8_t)val;
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vga.config.data_rotate=(uint8_t)val & 7;
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vga.config.raster_op=((uint8_t)val>>3) & 3;
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cmplx |= vga.complexity.setf(VGACMPLX_ROPROT,vga.config.data_rotate != 0 || vga.config.raster_op != 0);
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if (cmplx != 0) VGA_SetupHandlers();
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/*
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0-2 Number of positions to rotate data right before it is written to
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display memory. Only active in Write Mode 0.
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3-4 In Write Mode 2 this field controls the relation between the data
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written from the CPU, the data latched from the previous read and the
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data written to display memory:
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0: CPU Data is written unmodified
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1: CPU data is ANDed with the latched data
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2: CPU data is ORed with the latch data.
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3: CPU data is XORed with the latched data.
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*/
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break;
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case 4: /* Read Map Select Register */
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/* 0-1 number of the plane Read Mode 0 will read from */
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gfx(read_map_select)=val & 0x03;
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vga.config.read_map_select=val & 0x03;
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// LOG_DEBUG("Read Map %2X",val);
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break;
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case 5: /* Mode Register */
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if ((gfx(mode) ^ val) & 0xf0) {
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gfx(mode)=(uint8_t)val;
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VGA_DetermineMode();
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cmplx |= VGA_ComplexityCheck_ODDEVEN();
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} else gfx(mode)=(uint8_t)val;
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vga.config.write_mode=(uint8_t)val & 3;
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vga.config.read_mode=((uint8_t)val >> 3) & 1;
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cmplx |= vga.complexity.setf(VGACMPLX_COLORDONTCARE,gfx(color_dont_care) != 0 && vga.config.read_mode == 1);
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cmplx |= vga.complexity.setf(VGACMPLX_WRITEMODE,vga.config.write_mode != 0);
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cmplx |= vga.complexity.setf(VGACMPLX_READMODE,vga.config.read_mode != 0);
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if (cmplx != 0) VGA_SetupHandlers();
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// LOG_DEBUG("Write Mode %d Read Mode %d val %d",vga.config.write_mode,vga.config.read_mode,val);
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/*
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0-1 Write Mode: Controls how data from the CPU is transformed before
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being written to display memory:
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0: Mode 0 works as a Read-Modify-Write operation.
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First a read access loads the data latches of the VGA with the
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value in video memory at the addressed location. Then a write
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access will provide the destination address and the CPU data
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byte. The data written is modified by the function code in the
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Data Rotate register (3CEh index 3) as a function of the CPU
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data and the latches, then data is rotated as specified by the
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same register.
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1: Mode 1 is used for video to video transfers.
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A read access will load the data latches with the contents of
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the addressed byte of video memory. A write access will write
|
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the contents of the latches to the addressed byte. Thus a single
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MOVSB instruction can copy all pixels in the source address byte
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to the destination address.
|
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2: Mode 2 writes a color to all pixels in the addressed byte of
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video memory. Bit 0 of the CPU data is written to plane 0 et
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cetera. Individual bits can be enabled or disabled through the
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Bit Mask register (3CEh index 8).
|
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3: Mode 3 can be used to fill an area with a color and pattern. The
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CPU data is rotated according to 3CEh index 3 bits 0-2 and anded
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with the Bit Mask Register (3CEh index 8). For each bit in the
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result the corresponding pixel is set to the color in the
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Set/Reset Register (3CEh index 0 bits 0-3) if the bit is set and
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to the contents of the processor latch if the bit is clear.
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3 Read Mode
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0: Data is read from one of 4 bit planes depending on the Read Map
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Select Register (3CEh index 4).
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1: Data returned is a comparison between the 8 pixels occupying the
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read byte and the color in the Color Compare Register (3CEh
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index 2). A bit is set if the color of the corresponding pixel
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matches the register.
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4 Enables Odd/Even mode if set (See 3C4h index 4 bit 2).
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5 Enables CGA style 4 color pixels using even/odd bit pairs if set.
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6 Enables 256 color mode if set.
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*/
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break;
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case 6: /* Miscellaneous Register */
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if ((gfx(miscellaneous) ^ val) & 0x0c) {
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gfx(miscellaneous)=(uint8_t)val;
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VGA_DetermineMode();
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} else gfx(miscellaneous)=(uint8_t)val;
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VGA_ComplexityCheck_ODDEVEN();
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VGA_SetupHandlers();
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/*
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0 Indicates Graphics Mode if set, Alphanumeric mode else.
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1 Enables Odd/Even mode if set.
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2-3 Memory Mapping:
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0: use A000h-BFFFh
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1: use A000h-AFFFh VGA Graphics modes
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2: use B000h-B7FFh Monochrome modes
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3: use B800h-BFFFh CGA modes
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*/
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break;
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case 7: /* Color Don't Care Register */
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gfx(color_dont_care)=val & 0x0f;
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cmplx |= vga.complexity.setf(VGACMPLX_COLORDONTCARE,gfx(color_dont_care) != 0 && vga.config.read_mode == 1);
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if (cmplx != 0) VGA_SetupHandlers();
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/*
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0 Ignore bit plane 0 in Read mode 1 if clear.
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1 Ignore bit plane 1 in Read mode 1 if clear.
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2 Ignore bit plane 2 in Read mode 1 if clear.
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3 Ignore bit plane 3 in Read mode 1 if clear.
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*/
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vga.config.color_dont_care=val & 0xf;
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// LOG_DEBUG("Color don't care = %2X",val);
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break;
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case 8: /* Bit Mask Register */
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gfx(bit_mask)=(uint8_t)val;
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vga.config.full_bit_mask=ExpandTable[val];
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cmplx |= vga.complexity.setf(VGACMPLX_BITMASK,vga.config.full_bit_mask != 0xFFFFFFFFu); // at least one bit will be masked off?
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/* check for unusual use of the bit mask register in chained 320x200x256 mode and switch to the slow & accurate emulation */
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if (vga.mode == M_VGA && vga.config.chained)
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VGA_SetupHandlers();
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else if (cmplx != 0)
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VGA_SetupHandlers();
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// LOG_DEBUG("Bit mask %2X",val);
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/*
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0-7 Each bit if set enables writing to the corresponding bit of a byte in
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display memory.
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*/
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break;
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default:
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if (svga.write_p3cf) {
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svga.write_p3cf(gfx(index), val, iolen);
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break;
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}
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if (gfx(index) == 9 && !index9warned) {
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LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:3CF:Write %2X to illegal index 9",(int)val);
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index9warned=true;
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break;
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}
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LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:3CF:Write %2X to illegal index %2X",(int)val,(int)gfx(index));
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break;
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}
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LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:3CF:Write %2X to illegal index %2X",(int)val,(int)gfx(index));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static Bitu read_p3cf(Bitu port,Bitu iolen) {
|
||||
(void)port;//UNUSED
|
||||
(void)iolen;//UNUSED
|
||||
switch (gfx(index)) {
|
||||
case 0: /* Set/Reset Register */
|
||||
return gfx(set_reset);
|
||||
case 1: /* Enable Set/Reset Register */
|
||||
return gfx(enable_set_reset);
|
||||
case 2: /* Color Compare Register */
|
||||
return gfx(color_compare);
|
||||
case 3: /* Data Rotate */
|
||||
return gfx(data_rotate);
|
||||
case 4: /* Read Map Select Register */
|
||||
return gfx(read_map_select);
|
||||
case 5: /* Mode Register */
|
||||
return gfx(mode);
|
||||
case 6: /* Miscellaneous Register */
|
||||
return gfx(miscellaneous);
|
||||
case 7: /* Color Don't Care Register */
|
||||
return gfx(color_dont_care);
|
||||
case 8: /* Bit Mask Register */
|
||||
return gfx(bit_mask);
|
||||
default:
|
||||
if (svga.read_p3cf)
|
||||
return svga.read_p3cf(gfx(index), iolen);
|
||||
LOG(LOG_VGAMISC,LOG_NORMAL)("Reading from illegal index %2X in port %4X",(int)static_cast<uint32_t>(gfx(index)),(int)port);
|
||||
break;
|
||||
case 0: /* Set/Reset Register */
|
||||
return gfx(set_reset);
|
||||
case 1: /* Enable Set/Reset Register */
|
||||
return gfx(enable_set_reset);
|
||||
case 2: /* Color Compare Register */
|
||||
return gfx(color_compare);
|
||||
case 3: /* Data Rotate */
|
||||
return gfx(data_rotate);
|
||||
case 4: /* Read Map Select Register */
|
||||
return gfx(read_map_select);
|
||||
case 5: /* Mode Register */
|
||||
return gfx(mode);
|
||||
case 6: /* Miscellaneous Register */
|
||||
return gfx(miscellaneous);
|
||||
case 7: /* Color Don't Care Register */
|
||||
return gfx(color_dont_care);
|
||||
case 8: /* Bit Mask Register */
|
||||
return gfx(bit_mask);
|
||||
default:
|
||||
if (svga.read_p3cf)
|
||||
return svga.read_p3cf(gfx(index), iolen);
|
||||
|
||||
LOG(LOG_VGAMISC,LOG_NORMAL)("Reading from illegal index %2X in port %4X",(int)static_cast<uint32_t>(gfx(index)),(int)port);
|
||||
break;
|
||||
}
|
||||
return 0; /* Compiler happy */
|
||||
|
||||
return 0; /* Compiler happy */
|
||||
}
|
||||
|
||||
|
||||
|
||||
void VGA_SetupGFX(void) {
|
||||
if (IS_EGAVGA_ARCH) {
|
||||
IO_RegisterWriteHandler(0x3ce,write_p3ce,IO_MB);
|
||||
@ -267,10 +257,10 @@ void VGA_SetupGFX(void) {
|
||||
}
|
||||
|
||||
void VGA_UnsetupGFX(void) {
|
||||
IO_FreeWriteHandler(0x3ce,IO_MB);
|
||||
IO_FreeReadHandler(0x3ce,IO_MB);
|
||||
IO_FreeWriteHandler(0x3cf,IO_MB);
|
||||
IO_FreeReadHandler(0x3cf,IO_MB);
|
||||
IO_FreeWriteHandler(0x3ce,IO_MB);
|
||||
IO_FreeReadHandler(0x3ce,IO_MB);
|
||||
IO_FreeWriteHandler(0x3cf,IO_MB);
|
||||
IO_FreeReadHandler(0x3cf,IO_MB);
|
||||
}
|
||||
|
||||
// save state support
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user