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I can make a few more enhancements to SYSENTER/SYSEXIT, though it still does not solve BSODs

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This commit is contained in:
Jonathan Campbell 2024-12-18 15:36:14 -08:00
parent 69e85235df
commit 2519431b77
3 changed files with 12 additions and 6 deletions
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1
include/regs.h
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@ -34,6 +34,7 @@
#define FLAG_IOPL 0x00003000U
#define FLAG_NT 0x00004000U
#define FLAG_RF 0x00010000U
#define FLAG_VM 0x00020000U
#define FLAG_AC 0x00040000U
#define FLAG_ID 0x00200000U

14
src/cpu/cpu.cpp
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@ -4506,8 +4506,10 @@ bool CPU_SYSENTER() {
CPU_SetCPL(0);
FillFlags();
SETFLAGBIT(VM,false);
SETFLAGBIT(IF,false);
SETFLAGBIT(RF,false);
reg_eip = cpu_sep_eip;
reg_esp = cpu_sep_esp;
@ -4526,8 +4528,8 @@ bool CPU_SYSENTER() {
Segs.limit[ss] = 0xFFFFFFFF;
Segs.expanddown[ss] = false;
cpu.stack.big = true;
cpu.stack.mask=0xffffffff;
cpu.stack.notmask=0x00000000;
cpu.stack.mask = 0xffffffff;
cpu.stack.notmask = 0x00000000;
// DEBUG
// DEBUG_EnableDebugger();
@ -4553,19 +4555,19 @@ bool CPU_SYSEXIT() {
/* NTS: Do NOT use SetSegGeneral, SYSENTER is documented to set CS and SS based on what was given to the MSR,
* but with fixed and very specific descriptor cache values that represent 32-bit flat segments with
* base == 0 and limit == 4GB. */
Segs.val[cs] = (cpu_sep_cs | 3) + 0x10; /* Yes, really. Look it up in Intel's documentation */
Segs.val[cs] = (cpu_sep_cs & 0xFFFC) + 0x10 + 3/*RPL*/; /* Yes, really. Look it up in Intel's documentation */
Segs.phys[cs] = 0;
Segs.limit[cs] = 0xFFFFFFFF;
Segs.expanddown[cs] = false;
cpu.code.big = true;
Segs.val[ss] = (cpu_sep_cs | 3) + 0x18; /* Yes, really. Look it up in Intel's documentation */
Segs.val[ss] = (cpu_sep_cs & 0xFFFC) + 0x18 + 3/*RPL*/; /* Yes, really. Look it up in Intel's documentation */
Segs.phys[ss] = 0;
Segs.limit[ss] = 0xFFFFFFFF;
Segs.expanddown[ss] = false;
cpu.stack.big = true;
cpu.stack.mask=0xffffffff;
cpu.stack.notmask=0x00000000;
cpu.stack.mask = 0xffffffff;
cpu.stack.notmask = 0x00000000;
CPU_SetCPL(3);

3
src/debug/debug.cpp
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@ -1506,6 +1506,8 @@ void SkipSpace(char*& hex) {
while (*hex == ' ') hex++;
}
extern uint32_t cpu_sep_eip;
uint32_t GetHexValue(char* const str, char* &hex,bool *parsed,int exprge)
{
uint32_t regval = 0;
@ -1570,6 +1572,7 @@ uint32_t GetHexValue(char* const str, char* &hex,bool *parsed,int exprge)
else if (something == "CR2") { regval = (uint32_t)paging.cr2; }
else if (something == "CR3") { regval = (uint32_t)paging.cr3; }
else if (something == "CR4") { regval = (uint32_t)cpu.cr4; }
else if (something == "SYSENTER") { regval = (uint32_t)cpu_sep_eip; }
else if (something == "EAX") { regval = reg_eax; }
else if (something == "EBX") { regval = reg_ebx; }
else if (something == "ECX") { regval = reg_ecx; }