mirror of
https://github.com/joncampbell123/dosbox-x.git
synced 2025-05-08 02:53:03 +08:00
cleanup
This commit is contained in:
Jonathan Campbell
parent
8630e55f84
commit
318b3335e6
@ -348,4 +348,6 @@ void physdev_writed(const PhysPt64 addr,const uint32_t val);
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uint32_t MEM_get_address_bits();
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uint32_t MEM_get_address_bits4GB();
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void MEM_ResetPageHandler_Unmapped(Bitu phys_page, Bitu pages);
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#endif
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@ -1,4 +1,6 @@
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#include "dos_inc.h"
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#define PC98_GDC_FIFO_SIZE 32 /* taken from Neko Project II, but what is it really? */
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#define GDC_COMMAND_BYTE 0x100
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@ -203,6 +205,41 @@ extern uint8_t pc98_egc_mask[2]; /* host given (Neko: egc.m
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extern bool pc98_timestamp5c;
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extern uint8_t GDC_display_plane_wait_for_vsync;
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Bitu pc98_read_9a8(Bitu /*port*/,Bitu /*iolen*/);
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void pc98_write_9a8(Bitu port,Bitu val,Bitu iolen);
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void gdc_5mhz_mode_update_vars(void);
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void pc98_port6A_command_write(unsigned char b);
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void pc98_wait_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_crtc_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_port68_command_write(unsigned char b);
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Bitu pc98_read_9a0(Bitu /*port*/,Bitu /*iolen*/);
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void pc98_write_9a0(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_crtc_read(Bitu port,Bitu iolen);
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Bitu pc98_a1_read(Bitu port,Bitu iolen);
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void pc98_a1_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_gdc_write(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_gdc_read(Bitu port,Bitu iolen);
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Bitu pc98_egc4a0_read(Bitu port,Bitu iolen);
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void pc98_egc4a0_write(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_egc4a0_read_warning(Bitu port,Bitu iolen);
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void pc98_egc4a0_write_warning(Bitu port,Bitu val,Bitu iolen);
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extern const UINT8 gdc_defsyncm15[8];
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extern const UINT8 gdc_defsyncs15[8];
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extern const UINT8 gdc_defsyncm24[8];
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extern const UINT8 gdc_defsyncs24[8];
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extern const UINT8 gdc_defsyncm31[8];
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extern const UINT8 gdc_defsyncs31[8];
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extern const UINT8 gdc_defsyncm31_480[8];
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extern const UINT8 gdc_defsyncs31_480[8];
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void PC98_Set24KHz(void);
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void PC98_Set31KHz(void);
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void PC98_Set31KHz_480line(void);
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@ -102,4 +102,6 @@ void PCI_RemoveSST_Device(void);
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RealPt PCI_GetPModeInterface(void);
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bool has_pcibus_enable(void);
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extern bool pcibus_enable;
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#endif
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@ -819,6 +819,9 @@ extern uint32_t TXT_BG_Table[16];
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extern uint32_t Expand16Table[4][16];
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extern uint32_t Expand16BigTable[0x10000];
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extern int hack_lfb_yadjust;
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extern int hack_lfb_xadjust;
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void VGA_DAC_UpdateColorPalette();
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extern uint32_t GFX_Rmask;
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@ -924,4 +927,21 @@ static inline unsigned char *pc98_vram_256bank_from_window(const unsigned int b)
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#define VRAM98_TEXT ( pc98_vram_text() )
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#ifdef VGA_INTERNAL
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#define gfx(blah) vga.gfx.blah
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#define seq(blah) vga.seq.blah
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#define crtc(blah) vga.crtc.blah
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#endif
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void UpdateCGAFromSaveState(void);
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void INT10_PC98_CurMode_Relocate(void);
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void VGA_VsyncUpdateMode(VGA_Vsync vsyncmode);
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uint32_t GetReportedVideoMemorySize(void);
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extern void VGA_TweakUserVsyncOffset(float val);
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void VGA_UnsetupMisc(void);
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void VGA_UnsetupAttr(void);
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void VGA_UnsetupDAC(void);
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void VGA_UnsetupGFX(void);
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void VGA_UnsetupSEQ(void);
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#endif
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@ -116,6 +116,8 @@
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* chained 256-color modes differently.
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*/
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#define VGA_INTERNAL
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#include <assert.h>
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#include "dosbox.h"
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@ -130,6 +132,7 @@
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#include "setup.h"
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#include "timer.h"
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#include "mem.h"
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#include "pci_bus.h"
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#include "util_units.h"
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#include "control.h"
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#include "pc98_cg.h"
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@ -159,6 +162,8 @@
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using namespace std;
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static uint32_t assigned_lfb = 0;
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bool VGA_PITsync = false;
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unsigned int vbe_window_granularity = 0;
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@ -183,23 +188,8 @@ uint32_t S3_LFB_BASE = S3_LFB_BASE_DEFAULT;
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bool enable_pci_vga = true;
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SDL_Rect vga_capture_rect = {0,0,0,0};
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SDL_Rect vga_capture_current_rect = {0,0,0,0};
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uint32_t vga_capture_current_address = 0;
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uint32_t vga_capture_write_address = 0; // literally the address written
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uint32_t vga_capture_address = 0;
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uint32_t vga_capture_stride = 0;
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uint32_t vga_capture_state = 0;
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SDL_Rect &VGA_CaptureRectCurrent(void) {
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return vga_capture_current_rect;
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}
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SDL_Rect &VGA_CaptureRectFromGuest(void) {
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return vga_capture_rect;
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}
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VGA_Type vga;
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JEGA_DATA jega;
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SVGA_Driver svga;
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int enableCGASnow;
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int vesa_modelist_cap = 0;
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@ -252,22 +242,23 @@ bool allow_vesa_8bpp = true;
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bool allow_vesa_4bpp = true;
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bool allow_vesa_tty = true;
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void gdc_5mhz_mode_update_vars(void);
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void pc98_port6A_command_write(unsigned char b);
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void pc98_wait_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_crtc_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_port68_command_write(unsigned char b);
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Bitu pc98_read_9a0(Bitu /*port*/,Bitu /*iolen*/);
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void pc98_write_9a0(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_crtc_read(Bitu port,Bitu iolen);
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Bitu pc98_a1_read(Bitu port,Bitu iolen);
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void pc98_a1_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_gdc_write(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_gdc_read(Bitu port,Bitu iolen);
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Bitu pc98_egc4a0_read(Bitu port,Bitu iolen);
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void pc98_egc4a0_write(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_egc4a0_read_warning(Bitu port,Bitu iolen);
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void pc98_egc4a0_write_warning(Bitu port,Bitu val,Bitu iolen);
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uint32_t HercBlend_2_Table[16];
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uint32_t CGA_2_Table[16];
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uint32_t CGA_4_Table[256];
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uint32_t CGA_4_HiRes_Table[256];
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uint32_t CGA_4_HiRes_TableNP[256];
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uint32_t CGA_16_Table[256];
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uint32_t TXT_Font_Table[16];
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uint32_t TXT_FG_Table[16];
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uint32_t TXT_BG_Table[16];
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uint32_t ExpandTable[256];
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uint32_t Expand16Table[4][16];
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uint32_t FillTable[16];
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uint32_t ColorTable[16];
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double vga_force_refresh_rate = -1;
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uint8_t CGAPal2[2] = {0,0};
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uint8_t CGAPal4[4] = {0,0,0,0};
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/* ARTIC (A Relative Time Indication Counter) I/O read.
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* Ports 0x5C and 0x5E.
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@ -304,21 +295,6 @@ void vsync_poll_debug_notify() {
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vga_3da_polled = true;
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}
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uint32_t HercBlend_2_Table[16];
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uint32_t CGA_2_Table[16];
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uint32_t CGA_4_Table[256];
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uint32_t CGA_4_HiRes_Table[256];
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uint32_t CGA_4_HiRes_TableNP[256];
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uint32_t CGA_16_Table[256];
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uint32_t TXT_Font_Table[16];
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uint32_t TXT_FG_Table[16];
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uint32_t TXT_BG_Table[16];
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uint32_t ExpandTable[256];
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uint32_t Expand16Table[4][16];
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uint32_t FillTable[16];
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uint32_t ColorTable[16];
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double vga_force_refresh_rate = -1;
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void VGA_SetModeNow(VGAModes mode) {
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if (vga.mode == mode) return;
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vga.mode=mode;
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@ -459,9 +435,6 @@ void VGA_SetClock(Bitu which,Bitu target) {
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VGA_StartResize();
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}
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uint8_t CGAPal2[2] = {0,0};
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uint8_t CGAPal4[4] = {0,0,0,0};
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void VGA_SetCGA2Table(uint8_t val0,uint8_t val1) {
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const uint8_t total[2] = {val0,val1};
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for (unsigned int i=0;i < 2;i++) CGAPal2[i] = total[i];
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@ -648,13 +621,6 @@ static inline unsigned int int_log2(unsigned int val) {
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return log;
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}
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extern bool pcibus_enable;
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extern int hack_lfb_yadjust;
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extern int hack_lfb_xadjust;
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extern uint8_t GDC_display_plane_wait_for_vsync;
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void VGA_VsyncUpdateMode(VGA_Vsync vsyncmode);
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VGA_Vsync VGA_Vsync_Decode(const char *vsyncmodestr) {
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if (!strcasecmp(vsyncmodestr,"off")) return VS_Off;
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else if (!strcasecmp(vsyncmodestr,"on")) return VS_On;
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@ -666,11 +632,6 @@ VGA_Vsync VGA_Vsync_Decode(const char *vsyncmodestr) {
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return VS_Off;
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}
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bool has_pcibus_enable(void);
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uint32_t GetReportedVideoMemorySize(void);
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static uint32_t assigned_lfb = 0;
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void VGA_Reset(Section*) {
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// All non-PC98 video-related config settings are now in the [video] section
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@ -1249,18 +1210,6 @@ void VGA_Reset(Section*) {
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}
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}
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extern void VGA_TweakUserVsyncOffset(float val);
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void INT10_PC98_CurMode_Relocate(void);
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void VGA_UnsetupMisc(void);
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void VGA_UnsetupAttr(void);
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void VGA_UnsetupDAC(void);
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void VGA_UnsetupGFX(void);
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void VGA_UnsetupSEQ(void);
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#define gfx(blah) vga.gfx.blah
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#define seq(blah) vga.seq.blah
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#define crtc(blah) vga.crtc.blah
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void VGA_OnEnterPC98(Section *sec) {
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(void)sec;//UNUSED
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VGA_UnsetupMisc();
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@ -1391,73 +1340,11 @@ void VGA_OnEnterPC98(Section *sec) {
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VGA_StartResize();
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}
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void MEM_ResetPageHandler_Unmapped(Bitu phys_page, Bitu pages);
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void updateGDCpartitions4(bool enable) {
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pc98_allow_4_display_partitions = enable;
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pc98_gdc[GDC_SLAVE].display_partition_mask = pc98_allow_4_display_partitions ? 3 : 1;
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}
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/* source: Neko Project II GDC SYNC parameters for each mode */
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#if 0 // NOT YET USED
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static const UINT8 gdc_defsyncm15[8] = {0x10,0x4e,0x07,0x25,0x0d,0x0f,0xc8,0x94};
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static const UINT8 gdc_defsyncs15[8] = {0x06,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94};
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#endif
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static const UINT8 gdc_defsyncm24[8] = {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65};
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static const UINT8 gdc_defsyncs24[8] = {0x06,0x26,0x03,0x11,0x83,0x07,0x90,0x65};
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static const UINT8 gdc_defsyncm31[8] = {0x10,0x4e,0x47,0x0c,0x07,0x0d,0x90,0x89};
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static const UINT8 gdc_defsyncs31[8] = {0x06,0x26,0x41,0x0c,0x83,0x0d,0x90,0x89};
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static const UINT8 gdc_defsyncm31_480[8] = {0x10,0x4e,0x4b,0x0c,0x03,0x06,0xe0,0x95};
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static const UINT8 gdc_defsyncs31_480[8] = {0x06,0x26,0x41,0x0c,0x83,0x06,0xe0,0x95};
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/* ^ NTS: Even in 256-color mode the expectation for Active Display Words is 40, not 80.
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* Writing 80 when INT 18h is used to invoke 256-color mode isn't a problem but
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* it does cause erroneous values in debug functions (1280x480 for
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* "login 256-color paint tool"?). The correct value is 40 according to NP2
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* source code (in what cases exactly?) and some games that manually set up
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* 640x400 16-color mode AND THEN directly switch to 256-color mode (still 640x400)
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* expect the ADW to remain 40 ("battle skin panic"). */
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void PC98_Set24KHz(void) {
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pc98_gdc[GDC_MASTER].write_fifo_command(0x0F/*sync DE=1*/);
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for (unsigned int i=0;i < 8;i++)
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pc98_gdc[GDC_MASTER].write_fifo_param(gdc_defsyncm24[i]);
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pc98_gdc[GDC_MASTER].force_fifo_complete();
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pc98_gdc[GDC_SLAVE].write_fifo_command(0x0F/*sync DE=1*/);
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for (unsigned int i=0;i < 8;i++)
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pc98_gdc[GDC_SLAVE].write_fifo_param(gdc_defsyncs24[i]);
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pc98_gdc[GDC_SLAVE].force_fifo_complete();
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}
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void PC98_Set31KHz(void) {
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pc98_gdc[GDC_MASTER].write_fifo_command(0x0F/*sync DE=1*/);
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for (unsigned int i=0;i < 8;i++)
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pc98_gdc[GDC_MASTER].write_fifo_param(gdc_defsyncm31[i]);
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pc98_gdc[GDC_MASTER].force_fifo_complete();
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pc98_gdc[GDC_SLAVE].write_fifo_command(0x0F/*sync DE=1*/);
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for (unsigned int i=0;i < 8;i++)
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pc98_gdc[GDC_SLAVE].write_fifo_param(gdc_defsyncs31[i]);
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pc98_gdc[GDC_SLAVE].force_fifo_complete();
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}
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void PC98_Set31KHz_480line(void) {
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pc98_gdc[GDC_MASTER].write_fifo_command(0x0F/*sync DE=1*/);
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for (unsigned int i=0;i < 8;i++)
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pc98_gdc[GDC_MASTER].write_fifo_param(gdc_defsyncm31_480[i]);
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pc98_gdc[GDC_MASTER].force_fifo_complete();
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pc98_gdc[GDC_SLAVE].write_fifo_command(0x0F/*sync DE=1*/);
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for (unsigned int i=0;i < 8;i++)
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pc98_gdc[GDC_SLAVE].write_fifo_param(gdc_defsyncs31_480[i]);
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pc98_gdc[GDC_SLAVE].force_fifo_complete();
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}
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void VGA_OnEnterPC98_phase2(Section *sec) {
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(void)sec;//UNUSED
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VGA_SetupHandlers();
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@ -1574,12 +1461,6 @@ void VGA_Destroy(Section*) {
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PC98_FM_Destroy(NULL);
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}
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extern uint8_t pc98_pal_analog[256*3]; /* G R B 0x0..0xF */
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extern uint8_t pc98_pal_digital[8]; /* G R B 0x0..0x7 */
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void pc98_update_palette(void);
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void UpdateCGAFromSaveState(void);
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bool debugpollvga_pf_menu_callback(DOSBoxMenu * const xmenu, DOSBoxMenu::item * const menuitem) {
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(void)xmenu;//UNUSED
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(void)menuitem;//UNUSED
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@ -1696,8 +1577,6 @@ void VGA_Init() {
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AddVMEventFunction(VM_EVENT_RESET,AddVMEventFunctionFuncPair(VGA_Reset));
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}
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JEGA_DATA jega;
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// Store font
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void JEGA_writeFont() {
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jega.RSTAT &= ~0x02;
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@ -1005,3 +1005,61 @@ Bitu pc98_gdc_read(Bitu port,Bitu iolen) {
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return ~0ul;
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}
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/* source: Neko Project II GDC SYNC parameters for each mode */
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const UINT8 gdc_defsyncm15[8] = {0x10,0x4e,0x07,0x25,0x0d,0x0f,0xc8,0x94};
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const UINT8 gdc_defsyncs15[8] = {0x06,0x26,0x03,0x11,0x86,0x0f,0xc8,0x94};
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const UINT8 gdc_defsyncm24[8] = {0x10,0x4e,0x07,0x25,0x07,0x07,0x90,0x65};
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const UINT8 gdc_defsyncs24[8] = {0x06,0x26,0x03,0x11,0x83,0x07,0x90,0x65};
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const UINT8 gdc_defsyncm31[8] = {0x10,0x4e,0x47,0x0c,0x07,0x0d,0x90,0x89};
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const UINT8 gdc_defsyncs31[8] = {0x06,0x26,0x41,0x0c,0x83,0x0d,0x90,0x89};
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const UINT8 gdc_defsyncm31_480[8] = {0x10,0x4e,0x4b,0x0c,0x03,0x06,0xe0,0x95};
|
||||
const UINT8 gdc_defsyncs31_480[8] = {0x06,0x26,0x41,0x0c,0x83,0x06,0xe0,0x95};
|
||||
|
||||
/* ^ NTS: Even in 256-color mode the expectation for Active Display Words is 40, not 80.
|
||||
* Writing 80 when INT 18h is used to invoke 256-color mode isn't a problem but
|
||||
* it does cause erroneous values in debug functions (1280x480 for
|
||||
* "login 256-color paint tool"?). The correct value is 40 according to NP2
|
||||
* source code (in what cases exactly?) and some games that manually set up
|
||||
* 640x400 16-color mode AND THEN directly switch to 256-color mode (still 640x400)
|
||||
* expect the ADW to remain 40 ("battle skin panic"). */
|
||||
|
||||
void PC98_Set24KHz(void) {
|
||||
pc98_gdc[GDC_MASTER].write_fifo_command(0x0F/*sync DE=1*/);
|
||||
for (unsigned int i=0;i < 8;i++)
|
||||
pc98_gdc[GDC_MASTER].write_fifo_param(gdc_defsyncm24[i]);
|
||||
pc98_gdc[GDC_MASTER].force_fifo_complete();
|
||||
|
||||
pc98_gdc[GDC_SLAVE].write_fifo_command(0x0F/*sync DE=1*/);
|
||||
for (unsigned int i=0;i < 8;i++)
|
||||
pc98_gdc[GDC_SLAVE].write_fifo_param(gdc_defsyncs24[i]);
|
||||
pc98_gdc[GDC_SLAVE].force_fifo_complete();
|
||||
}
|
||||
|
||||
void PC98_Set31KHz(void) {
|
||||
pc98_gdc[GDC_MASTER].write_fifo_command(0x0F/*sync DE=1*/);
|
||||
for (unsigned int i=0;i < 8;i++)
|
||||
pc98_gdc[GDC_MASTER].write_fifo_param(gdc_defsyncm31[i]);
|
||||
pc98_gdc[GDC_MASTER].force_fifo_complete();
|
||||
|
||||
pc98_gdc[GDC_SLAVE].write_fifo_command(0x0F/*sync DE=1*/);
|
||||
for (unsigned int i=0;i < 8;i++)
|
||||
pc98_gdc[GDC_SLAVE].write_fifo_param(gdc_defsyncs31[i]);
|
||||
pc98_gdc[GDC_SLAVE].force_fifo_complete();
|
||||
}
|
||||
|
||||
void PC98_Set31KHz_480line(void) {
|
||||
pc98_gdc[GDC_MASTER].write_fifo_command(0x0F/*sync DE=1*/);
|
||||
for (unsigned int i=0;i < 8;i++)
|
||||
pc98_gdc[GDC_MASTER].write_fifo_param(gdc_defsyncm31_480[i]);
|
||||
pc98_gdc[GDC_MASTER].force_fifo_complete();
|
||||
|
||||
pc98_gdc[GDC_SLAVE].write_fifo_command(0x0F/*sync DE=1*/);
|
||||
for (unsigned int i=0;i < 8;i++)
|
||||
pc98_gdc[GDC_SLAVE].write_fifo_param(gdc_defsyncs31_480[i]);
|
||||
pc98_gdc[GDC_SLAVE].force_fifo_complete();
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user