From c45a1f6e261240d5cbea03b75f029ad443305f03 Mon Sep 17 00:00:00 2001
From: Allofich <19624336+Allofich@users.noreply.github.com>
Date: Sat, 6 Nov 2021 17:10:45 +0900
Subject: [PATCH] Limit prefix bug to when REP/REPZ is being used

---
 CHANGELOG                      | 2 ++
 src/cpu/core_normal_286.cpp    | 7 ++++++-
 src/cpu/core_normal_8086.cpp   | 7 ++++++-
 src/cpu/core_prefetch_286.cpp  | 7 ++++++-
 src/cpu/core_prefetch_8086.cpp | 7 ++++++-
 5 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index a07e20c82..43ab04d5c 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -13,6 +13,8 @@
     opcodes 0x70-0x7F. (Allofich)
   - Fixed 0x0F opcode being valid on 80186 core when
     it should be invalid. (Allofich)
+  - Adjusted multiple-prefix bug for 8086/286 to only
+    apply when REP or REPZ is used. (Allofich)
   - Added stub IBM ROM BASIC points in the BIOS area
     so that when MS-DOS 1.x and 2.x BASIC.COM and BASICA.COM
     are run, a polite message is displayed instead of
diff --git a/src/cpu/core_normal_286.cpp b/src/cpu/core_normal_286.cpp
index 9b755db05..60ce1786e 100644
--- a/src/cpu/core_normal_286.cpp
+++ b/src/cpu/core_normal_286.cpp
@@ -88,7 +88,12 @@ extern Bitu cycle_count;
 #define TEST_PREFIX_REP		(core.prefixes & PREFIX_REP)
 
 #define DO_PREFIX_SEG(_SEG)					\
-    if (GETFLAG(IF) && CPU_Cycles <= 0 && !mustCompleteInstruction) goto prefix_out; \
+    if (GETFLAG(IF) && CPU_Cycles <= 0 && !mustCompleteInstruction) \
+    {   \
+        uint8_t next = LoadMb(core.cseip + 1);  \
+        if (next == 0xf2 || next == 0xf3)   \
+            goto prefix_out;    \
+    }   \
 	BaseDS=SegBase(_SEG);					\
 	BaseSS=SegBase(_SEG);					\
 	core.base_val_ds=_SEG;					\
diff --git a/src/cpu/core_normal_8086.cpp b/src/cpu/core_normal_8086.cpp
index a32573361..0bfc15a4d 100644
--- a/src/cpu/core_normal_8086.cpp
+++ b/src/cpu/core_normal_8086.cpp
@@ -124,7 +124,12 @@ extern Bitu cycle_count;
 #define TEST_PREFIX_REP		(core.prefixes & PREFIX_REP)
 
 #define DO_PREFIX_SEG(_SEG)					\
-    if (GETFLAG(IF) && CPU_Cycles <= 0 && !mustCompleteInstruction) goto prefix_out; \
+    if (GETFLAG(IF) && CPU_Cycles <= 0 && !mustCompleteInstruction) \
+    {   \
+        uint8_t next = LoadMb(core.cseip + 1);  \
+        if (next == 0xf2 || next == 0xf3)   \
+            goto prefix_out;    \
+    }   \
 	BaseDS=SegBase(_SEG);					\
 	BaseSS=SegBase(_SEG);					\
 	core.base_val_ds=_SEG;					\
diff --git a/src/cpu/core_prefetch_286.cpp b/src/cpu/core_prefetch_286.cpp
index d0e7d66c4..16a34f432 100644
--- a/src/cpu/core_prefetch_286.cpp
+++ b/src/cpu/core_prefetch_286.cpp
@@ -91,7 +91,12 @@ Bits CPU_Core_Prefetch_Trap_Run(void);
 #define TEST_PREFIX_REP		(core.prefixes & PREFIX_REP)
 
 #define DO_PREFIX_SEG(_SEG)					\
-    if (GETFLAG(IF) && CPU_Cycles <= 0) goto prefix_out; \
+    if (GETFLAG(IF) && CPU_Cycles <= 0) \
+    {   \
+        uint8_t next = LoadMb(core.cseip + 1);  \
+        if (next == 0xf2 || next == 0xf3)   \
+            goto prefix_out;    \
+    }   \
 	BaseDS=SegBase(_SEG);					\
 	BaseSS=SegBase(_SEG);					\
 	core.base_val_ds=_SEG;					\
diff --git a/src/cpu/core_prefetch_8086.cpp b/src/cpu/core_prefetch_8086.cpp
index 6945925d8..4da287615 100644
--- a/src/cpu/core_prefetch_8086.cpp
+++ b/src/cpu/core_prefetch_8086.cpp
@@ -129,7 +129,12 @@ Bits CPU_Core_Prefetch_Trap_Run(void);
 #define TEST_PREFIX_REP		(core.prefixes & PREFIX_REP)
 
 #define DO_PREFIX_SEG(_SEG)					\
-    if (GETFLAG(IF) && CPU_Cycles <= 0) goto prefix_out; \
+    if (GETFLAG(IF) && CPU_Cycles <= 0) \
+    {   \
+        uint8_t next = LoadMb(core.cseip + 1);  \
+        if (next == 0xf2 || next == 0xf3)   \
+            goto prefix_out;    \
+    }   \
 	BaseDS=SegBase(_SEG);					\
 	BaseSS=SegBase(_SEG);					\
 	core.base_val_ds=_SEG;					\