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dosbox-x/doc-collection/opcodes/x86/8086.dop
Jonathan Campbell 23dfbd27e9 more
2020-07-09 01:02:00 -07:00

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arch "x86";
description "Machine-parsable list of opcodes";
charset_encoding "UTF-8"; /* default */
/* predefined variables:
codesize == 16 || codesize == 32 || codesize == 64: word code access size (affects code handling)
datasize == 16 || datasize == 32 || datasize == 64: word data access size (affects data handling)
dsreg: default segment OR segment override
CS, DS, ES, FS, GS, SS: segment registers
reg: general register, operand (regw if word, regb if byte)
regb: general register, byte operand (AH, AL, etc)
regw: general register, word operand (AX, BX, CX, etc if 16-bit, EAX, EBX, etc if 32-bit)
sreg: segment register, operand
rm: register/memory operand, word operand
rmb: register/memory operand, byte operand
rmw: register/memory operand, byte operand
rm16: register/memory operand, 16-bit word operand
mrm: mod/reg/rm (with optional scalar/index/byte if 32-bit addressing with the right combination)
AXH, BXH, CXH, DXH, etc: Upper 16 bits of EAX, EBX, ECX, EDX, etc
opbyte(n): opcode byte n
accum: AX/EAX
base: BX/EBX
counter: CX/ECX
daccum: DX/EDX
srcidx: SI/ESI
dstidx: DI/EDI
immb: 8-bit immediate
immw: word immediate
imma: address (offset) immediate
immsb: 8-bit immediate signed
sib: scalar/index/byte
flags: flags register (FLAGS if 16-bit, EFLAGS if 32-bit)
flags(...): specific flags (bitmask)
stackp: stack pointer (SP/ESP)
basep: base pointer (BP/EBP)
stackdataw: word value on stack [SS:stackp]. 16-bit or 32-bit depending on ?
ip: instruction pointer (IP/EIP). For input, the value is the instruction pointer after decode.
cpulevel: 0=8086 1=80186 2=286 3=386 4=486 5=Pentium
[A,B]: Range syntax, A <= x <= B inclusive
*/
/* avoid copy-pasta */
common opcode "ADD" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* dst += src */
input dst,src; /* reads dst, src */
output dst; /* writes dst */
}
common opcode "OR" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* dst |= src */
input dst,src; /* reads dst, src */
output dst; /* writes dst */
}
common opcode "ADC" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* dst += src + CF */
input dst,src,flags(CF); /* reads dst, src, CF flag */
output dst; /* writes dst */
}
common opcode "SBB" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* dst -= src + CF */
input dst,src,flags(CF); /* reads dst, src, CF flag */
output dst; /* writes dst */
}
common opcode "AND" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* dst &= src */
input dst,src; /* reads dst, src */
output dst; /* writes dst */
}
common opcode "SUB" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* dst -= src */
input dst,src; /* reads dst, src */
output dst; /* writes dst */
}
common opcode "XOR" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* dst ^= src */
input dst,src; /* reads dst, src */
output dst; /* writes dst */
}
common opcode "CMP" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* tmp = dst - src */
input dst,src; /* reads dst, src */
}
common opcode "MOV" param(dst,src) {
/* does not modify flags */
/* dst = src */
input src; /* reads src */
output dst; /* writes dst */
}
common opcode "LEA" param(dst,ea) {
/* does not modify flags */
/* dst = ea */
input ea; /* reads src */
output dst; /* writes dst */
}
common opcode "TEST" param(dst,src) {
modifies flags(CF,PF,AF,ZF,SF,OF);
/* tmp = dst & src */
input dst,src; /* reads dst, src */
}
common opcode "XCHG" param(dst,src) {
/* does not modify flags */
/* tmp = dst; dst = src; src = tmp */
input dst,src; /* reads dst, src */
output dst,src; /* writes dst, src */
}
common opcode "PUSH" param(src) {
modifies stackp; /* stackp -= word size */
output stackdataw;
input src;
/* how to show it */
syntax src;
}
common opcode "POP" param(dst) {
modifies stackp; /* stackp += word size */
input stackdataw;
output dst;
/* how to show it */
syntax dst;
}
common opcode "PUSHF" param(src) {
modifies stackp; /* stackp -= word size */
output stackdataw;
input src;
/* how to show it */
syntax ;
}
common opcode "POPF" param(dst) {
modifies stackp; /* stackp += word size */
input stackdataw;
output dst;
/* how to show it */
syntax ;
}
common opcode "INC" param(what) {
modifies flags(PF,AF,ZF,SF,OF); /* not CF */
/* what++ or what = what + 1 */
input what;
output what;
/* how to show it */
syntax what;
}
common opcode "DEC" param(what) {
modifies flags(PF,AF,ZF,SF,OF); /* not CF */
/* what-- or what = what - 1 */
input what;
output what;
/* how to show it */
syntax what;
}
common opcode "Jcc" param(imm,insp,flags,cond) {
modifies insp if cond();
input insp,flags,imm;
/* if cond(), instruction pointer (after decode) is set to insp+imm */
var fip = insp+imm;
insp = fip if cond();
/* how to show it (disassemblers show the sum, not the immediate) */
syntax fip;
}
common opcode "CALL FAR" param(sv,ov) {
modifies stackp; /* stackp -= (word size + 16 bits) */
modifies CS,insp;
/* CS = sv, [E]IP = ov */
input sv,ov;
output CS,insp;
output order(stackdataw,stackdata16);
/* how to show it */
syntax farptr(sv,ov); /* seg:off */
}
common opcode "RET" param(iw) {
modifies stackp; /* stackp += (word size + iw) */
modifies insp;
output insp;
input order(stackdataw);
input iw;
}
common opcode "RETF" param(iw) {
modifies stackp; /* stackp += (word size + 16 bits + iw) */
modifies CS,insp;
output CS,insp;
input order(stackdataw,stackdata16);
input iw;
}
common opcode "INT" param(iw) {
modifies stackp; /* stackp += (word size + 16 bits + iw) */
modifies CS,insp;
input iw;
output CS,insp;
output order(stackdataw,stackdata16,flags);
}
opcode sequence(0x00 mrm) name "ADD" { /* ADD r/m, reg */ common opcode "ADD" param(rmb,regb); }
opcode sequence(0x01 mrm) name "ADD" { /* ADD r/m, reg */ common opcode "ADD" param(rmw,regw); }
opcode sequence(0x02 mrm) name "ADD" { /* ADD reg, r/m */ common opcode "ADD" param(regb,rmb); }
opcode sequence(0x03 mrm) name "ADD" { /* ADD reg, r/m */ common opcode "ADD" param(regw,rmw); }
opcode sequence(0x04 immb) name "ADD" { /* ADD AL, imm */ common opcode "ADD" param(AL,immb); }
opcode sequence(0x05 immw) name "ADD" { /* ADD AX, imm */ common opcode "ADD" param(accum,immw); }
opcode sequence(0x06) name "PUSH" { /* PUSH ES */ common opcode "PUSH" param(ES); }
opcode sequence(0x07) name "POP" { /* POP ES */ common opcode "POP" param(ES); }
opcode sequence(0x08 mrm) name "OR" { /* OR r/m, reg */ common opcode "OR" param(rmb,regb); }
opcode sequence(0x09 mrm) name "OR" { /* OR r/m, reg */ common opcode "OR" param(rmw,regw); }
opcode sequence(0x0A mrm) name "OR" { /* OR reg, r/m */ common opcode "OR" param(regb,rmb); }
opcode sequence(0x0B mrm) name "OR" { /* OR reg, r/m */ common opcode "OR" param(regw,rmw); }
opcode sequence(0x0C immb) name "OR" { /* OR AL, imm */ common opcode "OR" param(AL,immb); }
opcode sequence(0x0D immw) name "OR" { /* OR AX, imm */ common opcode "OR" param(accum,immw); }
opcode sequence(0x0E) name "PUSH" { /* PUSH CS */ common opcode "PUSH" param(CS); }
opcode sequence(0x0F) name "POP" { /* POP CS */
if cpulevel == 0 {
common opcode "POP" param(CS);
}
else {
reject; /* prefix to next opcode byte, not opcode, this rule does not apply */
}
}
opcode sequence(0x10 mrm) name "ADC" { /* ADC r/m, reg */ common opcode "ADC" param(rmb,regb); }
opcode sequence(0x11 mrm) name "ADC" { /* ADC r/m, reg */ common opcode "ADC" param(rmw,regw); }
opcode sequence(0x12 mrm) name "ADC" { /* ADC reg, r/m */ common opcode "ADC" param(regb,rmb); }
opcode sequence(0x13 mrm) name "ADC" { /* ADC reg, r/m */ common opcode "ADC" param(regw,rmw); }
opcode sequence(0x14 immb) name "ADC" { /* ADC AL, imm */ common opcode "ADC" param(AL,immb); }
opcode sequence(0x15 immw) name "ADC" { /* ADC AX, imm */ common opcode "ADC" param(accum,immw); }
opcode sequence(0x16) name "PUSH" { /* PUSH ES */ common opcode "PUSH" param(SS); }
opcode sequence(0x17) name "POP" { /* POP ES */ common opcode "POP" param(SS); }
opcode sequence(0x18 mrm) name "SBB" { /* SBB r/m, reg */ common opcode "SBB" param(rmb,regb); }
opcode sequence(0x19 mrm) name "SBB" { /* SBB r/m, reg */ common opcode "SBB" param(rmw,regw); }
opcode sequence(0x1A mrm) name "SBB" { /* SBB reg, r/m */ common opcode "SBB" param(regb,rmb); }
opcode sequence(0x1B mrm) name "SBB" { /* SBB reg, r/m */ common opcode "SBB" param(regw,rmw); }
opcode sequence(0x1C immb) name "SBB" { /* SBB AL, imm */ common opcode "SBB" param(AL,immb); }
opcode sequence(0x1D immw) name "SBB" { /* SBB AX, imm */ common opcode "SBB" param(accum,immw); }
opcode sequence(0x1E) name "PUSH" { /* PUSH ES */ common opcode "PUSH" param(DS); }
opcode sequence(0x1F) name "POP" { /* POP ES */ common opcode "POP" param(DS); }
opcode sequence(0x20 mrm) name "AND" { /* AND r/m, reg */ common opcode "AND" param(rmb,regb); }
opcode sequence(0x21 mrm) name "AND" { /* AND r/m, reg */ common opcode "AND" param(rmw,regw); }
opcode sequence(0x22 mrm) name "AND" { /* AND reg, r/m */ common opcode "AND" param(regb,rmb); }
opcode sequence(0x23 mrm) name "AND" { /* AND reg, r/m */ common opcode "AND" param(regw,rmw); }
opcode sequence(0x24 immb) name "AND" { /* AND AL, imm */ common opcode "AND" param(AL,immb); }
opcode sequence(0x25 immw) name "AND" { /* AND AX, imm */ common opcode "AND" param(accum,immw); }
prefix sequence(0x26) name "ES:" { segment override ES; }
opcode sequence(0x27) name "DAA" {
modifies flags(CF,PF,AF,ZF,SF,OF);
input al,flags(CF);
output al;
}
opcode sequence(0x28 mrm) name "SUB" { /* SUB r/m, reg */ common opcode "SUB" param(rmb,regb); }
opcode sequence(0x29 mrm) name "SUB" { /* SUB r/m, reg */ common opcode "SUB" param(rmw,regw); }
opcode sequence(0x2A mrm) name "SUB" { /* SUB reg, r/m */ common opcode "SUB" param(regb,rmb); }
opcode sequence(0x2B mrm) name "SUB" { /* SUB reg, r/m */ common opcode "SUB" param(regw,rmw); }
opcode sequence(0x2C immb) name "SUB" { /* SUB AL, imm */ common opcode "SUB" param(AL,immb); }
opcode sequence(0x2D immw) name "SUB" { /* SUB AX, imm */ common opcode "SUB" param(accum,immw); }
prefix sequence(0x2E) name "CS:" { segment override CS; }
opcode sequence(0x2F) name "DAS" {
modifies flags(CF,PF,AF,ZF,SF,OF);
input al,flags(CF);
output al;
}
opcode sequence(0x30 mrm) name "XOR" { /* XOR r/m, reg */ common opcode "XOR" param(rmb,regb); }
opcode sequence(0x31 mrm) name "XOR" { /* XOR r/m, reg */ common opcode "XOR" param(rmw,regw); }
opcode sequence(0x32 mrm) name "XOR" { /* XOR reg, r/m */ common opcode "XOR" param(regb,rmb); }
opcode sequence(0x33 mrm) name "XOR" { /* XOR reg, r/m */ common opcode "XOR" param(regw,rmw); }
opcode sequence(0x34 immb) name "XOR" { /* XOR AL, imm */ common opcode "XOR" param(AL,immb); }
opcode sequence(0x35 immw) name "XOR" { /* XOR AX, imm */ common opcode "XOR" param(accum,immw); }
prefix sequence(0x36) name "ES:" { segment override SS; }
opcode sequence(0x37) name "AAA" {
modifies flags(CF,PF,AF,ZF,SF,OF);
input al,flags(CF);
output al;
}
opcode sequence(0x38 mrm) name "CMP" { /* CMP r/m, reg */ common opcode "CMP" param(rmb,regb); }
opcode sequence(0x39 mrm) name "CMP" { /* CMP r/m, reg */ common opcode "CMP" param(rmw,regw); }
opcode sequence(0x3A mrm) name "CMP" { /* CMP reg, r/m */ common opcode "CMP" param(regb,rmb); }
opcode sequence(0x3B mrm) name "CMP" { /* CMP reg, r/m */ common opcode "CMP" param(regw,rmw); }
opcode sequence(0x3C immb) name "CMP" { /* CMP AL, imm */ common opcode "CMP" param(AL,immb); }
opcode sequence(0x3D immw) name "CMP" { /* CMP AX, imm */ common opcode "CMP" param(accum,immw); }
prefix sequence(0x3E) name "CS:" { segment override DS; }
opcode sequence(0x3F) name "AAS" {
modifies flags(CF,PF,AF,ZF,SF,OF);
input al,flags(CF);
output al;
}
opcode sequence([0x40,0x47]) name "INC" {
reg index = opbyte(0) & 7;
common opcode "INC" param(regw); }
}
opcode sequence([0x48,0x4F]) name "DEC" {
reg index = opbyte(0) & 7;
common opcode "DEC" param(regw); }
}
opcode sequence([0x50,0x57]) name "PUSH" {
reg index = opbyte(0) & 7;
common opcode "PUSH" param(regw);
}
opcode sequence([0x58,0x5F]) name "POP" {
reg index = opbyte(0) & 7;
common opcode "POP" param(regw);
}
opcode sequence(0x70 immsb) name "JO" { common opcode "Jcc" param(immsb,ip,flags(OF),function(flags(OF))); }
opcode sequence(0x71 immsb) name "JNO" { common opcode "Jcc" param(immsb,ip,flags(OF),function(!flags(OF))); }
opcode sequence(0x72 immsb) name "JB" alias "JNAE" { common opcode "Jcc" param(immsb,ip,flags(CF),function(flags(CF))); }
opcode sequence(0x73 immsb) name "JNB" alias "JAE" { common opcode "Jcc" param(immsb,ip,flags(CF),function(!flags(CF))); }
opcode sequence(0x74 immsb) name "JZ" alias "JE" { common opcode "Jcc" param(immsb,ip,flags(ZF),function(flags(ZF))); }
opcode sequence(0x75 immsb) name "JNZ" alias "JNE" { common opcode "Jcc" param(immsb,ip,flags(ZF),function(!flags(ZF))); }
opcode sequence(0x76 immsb) name "JBE" alias "JNA" { common opcode "Jcc" param(immsb,ip,flags(CF,ZF),function(flags(CF) | flags(ZF))); }
opcode sequence(0x77 immsb) name "JNBE" alias "JA" { common opcode "Jcc" param(immsb,ip,flags(CF,ZF),function(!(flags(CF) | flags(ZF)))); }
opcode sequence(0x78 immsb) name "JS" { common opcode "Jcc" param(immsb,ip,flags(SF),function(flags(SF))); }
opcode sequence(0x79 immsb) name "JNS" { common opcode "Jcc" param(immsb,ip,flags(SF),function(!flags(SF))); }
opcode sequence(0x7A immsb) name "JP" alias "JPE" { common opcode "Jcc" param(immsb,ip,flags(PF),function(flags(PF))); }
opcode sequence(0x7B immsb) name "JNP" alias "JPO" { common opcode "Jcc" param(immsb,ip,flags(PF),function(!flags(PF))); }
opcode sequence(0x7C immsb) name "JL" alias "JNGE" { common opcode "Jcc" param(immsb,ip,flags(SF,OF),function(flags(SF) ^ flags(OF))); }
opcode sequence(0x7D immsb) name "JNL" alias "JGE" { common opcode "Jcc" param(immsb,ip,flags(SF,OF),function(!(flags(SF) ^ flags(OF)))); }
opcode sequence(0x7E immsb) name "JLE" alias "JNG" { common opcode "Jcc" param(immsb,ip,flags(SF,OF,ZF),function((flags(SF) ^ flags(OF)) | flags(ZF))); }
opcode sequence(0x7F immsb) name "JNLE" alias "JG" { common opcode "Jcc" param(immsb,ip,flags(SF,OF,ZF),function(!((flags(SF) ^ flags(OF)) | flags(ZF)))); }
/* GRP1. reg selects function. Notice reg maps instructions the same as 0x00-0x3F? */
/* For the 0x83 opcode byte case the immediate byte is sign extended to a word. */
opcode sequence(0x80 mrm immb) where reg == 0 name "ADD" { common opcode "ADD" param(rmb,immb); }
opcode sequence(0x81 mrm immw) where reg == 0 name "ADD" { common opcode "ADD" param(rmw,immw); }
opcode sequence(0x82 mrm immb) where reg == 0 name "ADD" { common opcode "ADD" param(rmb,immb); }
opcode sequence(0x83 mrm immsb) where reg == 0 name "ADD" { common opcode "ADD" param(rmw,immsb); }
opcode sequence(0x80 mrm immb) where reg == 1 name "OR" { common opcode "OR" param(rmb,immb); }
opcode sequence(0x81 mrm immw) where reg == 1 name "OR" { common opcode "OR" param(rmw,immw); }
opcode sequence(0x82 mrm immb) where reg == 1 name "OR" { common opcode "OR" param(rmb,immb); }
opcode sequence(0x83 mrm immsb) where reg == 1 name "OR" { common opcode "OR" param(rmw,immsb); }
opcode sequence(0x80 mrm immb) where reg == 2 name "ADC" { common opcode "ADC" param(rmb,immb); }
opcode sequence(0x81 mrm immw) where reg == 2 name "ADC" { common opcode "ADC" param(rmw,immw); }
opcode sequence(0x82 mrm immb) where reg == 2 name "ADC" { common opcode "ADC" param(rmb,immb); }
opcode sequence(0x83 mrm immsb) where reg == 2 name "ADC" { common opcode "ADC" param(rmw,immsb); }
opcode sequence(0x80 mrm immb) where reg == 3 name "SBB" { common opcode "SBB" param(rmb,immb); }
opcode sequence(0x81 mrm immw) where reg == 3 name "SBB" { common opcode "SBB" param(rmw,immw); }
opcode sequence(0x82 mrm immb) where reg == 3 name "SBB" { common opcode "SBB" param(rmb,immb); }
opcode sequence(0x83 mrm immsb) where reg == 3 name "SBB" { common opcode "SBB" param(rmw,immsb); }
opcode sequence(0x80 mrm immb) where reg == 4 name "AND" { common opcode "AND" param(rmb,immb); }
opcode sequence(0x81 mrm immw) where reg == 4 name "AND" { common opcode "AND" param(rmw,immw); }
opcode sequence(0x82 mrm immb) where reg == 4 name "AND" { common opcode "AND" param(rmb,immb); }
opcode sequence(0x83 mrm immsb) where reg == 4 name "AND" { common opcode "AND" param(rmw,immsb); }
opcode sequence(0x80 mrm immb) where reg == 5 name "SUB" { common opcode "SUB" param(rmb,immb); }
opcode sequence(0x81 mrm immw) where reg == 5 name "SUB" { common opcode "SUB" param(rmw,immw); }
opcode sequence(0x82 mrm immb) where reg == 5 name "SUB" { common opcode "SUB" param(rmb,immb); }
opcode sequence(0x83 mrm immsb) where reg == 5 name "SUB" { common opcode "SUB" param(rmw,immsb); }
opcode sequence(0x80 mrm immb) where reg == 6 name "XOR" { common opcode "XOR" param(rmb,immb); }
opcode sequence(0x81 mrm immw) where reg == 6 name "XOR" { common opcode "XOR" param(rmw,immw); }
opcode sequence(0x82 mrm immb) where reg == 6 name "XOR" { common opcode "XOR" param(rmb,immb); }
opcode sequence(0x83 mrm immsb) where reg == 6 name "XOR" { common opcode "XOR" param(rmw,immsb); }
opcode sequence(0x80 mrm immb) where reg == 7 name "CMP" { common opcode "CMP" param(rmb,immb); }
opcode sequence(0x81 mrm immw) where reg == 7 name "CMP" { common opcode "CMP" param(rmw,immw); }
opcode sequence(0x82 mrm immb) where reg == 7 name "CMP" { common opcode "CMP" param(rmb,immb); }
opcode sequence(0x83 mrm immsb) where reg == 7 name "CMP" { common opcode "CMP" param(rmw,immsb); }
opcode sequence(0x84 mrm) name "TEST" { common opcode "TEST" param(regb,rmb); }
opcode sequence(0x85 mrm) name "TEST" { common opcode "TEST" param(regw,rmw); }
opcode sequence(0x86 mrm) name "XCHG" { common opcode "XCHG" param(regb,rmb); }
opcode sequence(0x87 mrm) name "XCHG" { common opcode "XCHG" param(regw,rmw); }
opcode sequence(0x88 mrm) name "MOV" { common opcode "MOV" param(rmb,regb); }
opcode sequence(0x89 mrm) name "MOV" { common opcode "MOV" param(rmw,regw); }
opcode sequence(0x8A mrm) name "MOV" { common opcode "MOV" param(regb,rmb); }
opcode sequence(0x8B mrm) name "MOV" { common opcode "MOV" param(regw,rmw); }
opcode sequence(0x8C mrm) name "MOV" { common opcode "MOV" param(rm16,sreg); } /* mov r/m,segment register */
opcode sequence(0x8D mrm) name "LEA" where mod != 3 { common opcode "LEA" param(regw,eaw); } /* LEA reg, [memory ref] */
opcode sequence(0x8E mrm) name "MOV" { common opcode "MOV" param(sreg,rm16); } /* mov segment register,r/m */
opcode sequence(0x8F mrm) where reg == 0 name "POP" { common opcode "POP" param(rmw); } /* POP r/m */
opcode sequence(0x90) name "NOP" { }
opcode sequence([0x91,0x97]) name "XCHG" {
reg index = opbyte(0) & 7;
common opcode "XCHG" param(regw,accum);
}
opcode sequence(0x98) name "CBW" if datasize == 16 {
/* AX = sign extended AL */
input AL;
output AX only modifies AH;
}
opcode sequence(0x98) name "CWDE" if datasize == 32 {
/* EAX = sign extended AX */
input AX;
output EAX only modifies AXH;
}
opcode sequence(0x99) name "CWD" if datasize == 16 {
/* DX:AX = sign extended AX */
input AX;
output DX,AX only modifies DX;
}
opcode sequence(0x99) name "CDQ" if datasize == 32 {
/* EDX:EAX = sign extended EAX */
input EAX;
output EDX,EAX only modifies EDX;
}
opcode sequence(0x9A immw imm16) name "CALL" { /* CALL FAR imm16:immw aka seg:off */
common opcode "CALL FAR" param(imm16,immw);
}
opcode sequence(0x9B) name "WAIT" { /* wait for FPU */
/* check pending unmasked floating point exceptions */
}
opcode sequence(0x9C) name "PUSHF" { common opcode "PUSHF" param(flags); }
opcode sequence(0x9D) name "POPF" { common opcode "POPF" param(flags); }
opcode sequence(0x9E) name "SAHF" {
input AH;
output flags;
}
opcode sequence(0x9F) name "LAHF" {
input flags;
output AH;
}
opcode sequence(0xA0 imma) name "MOV" { common opcode "MOV" param(AL,memory reference word imma); }
opcode sequence(0xA1 imma) name "MOV" { common opcode "MOV" param(accum,memory reference word imma); }
opcode sequence(0xA2 imma) name "MOV" { common opcode "MOV" param(memory reference word imma,AL); }
opcode sequence(0xA3 imma) name "MOV" { common opcode "MOV" param(memory reference word imma,accum); }
opcode sequence(0xA4) name "MOVSB" {
/* if DF = 1, srcidx -= 1, dstidx -= 1; */
/* if DF = 0, srcidx += 1, dstidx += 1; */
input memory reference byte srcidx, flags(DF);
output memory reference byte farptr(ES,dstidx);
modifies srcidx,dstidx;
/* how to show it */
syntax ;
}
opcode sequence(0xA5) name "MOVSW" {
/* if DF = 1, srcidx -= wordsize, dstidx -= wordsize; */
/* if DF = 0, srcidx += wordsize, dstidx += wordsize; */
input memory reference word srcidx, flags(DF);
output memory reference word farptr(ES,dstidx);
modifies srcidx,dstidx;
/* how to show it */
syntax ;
}
opcode sequence(0xA6) name "CMPSB" {
/* if DF = 1, srcidx -= 1, dstidx -= 1; */
/* if DF = 0, srcidx += 1, dstidx += 1; */
input memory reference byte srcidx, memory reference byte farptr(ES,dstidx), flags(DF);
modifies srcidx,dstidx,flags(CF,PF,AF,ZF,SF,OF);
/* how to show it */
syntax ;
}
opcode sequence(0xA7) name "CMPSW" {
/* if DF = 1, srcidx -= wordsize, dstidx -= wordsize; */
/* if DF = 0, srcidx += wordsize, dstidx += wordsize; */
input memory reference word srcidx, memory reference word farptr(ES,dstidx), flags(DF);
modifies srcidx,dstidx,flags(CF,PF,AF,ZF,SF,OF);
/* how to show it */
syntax ;
}
opcode sequence(0xA8 immb) name "TEST" { common opcode "TEST" param(AL,immb); }
opcode sequence(0xA9 immw) name "TEST" { common opcode "TEST" param(accum,immw); }
opcode sequence(0xAA) name "STOSB" {
/* if DF = 1, dstidx -= 1; */
/* if DF = 0, dstidx += 1; */
input AL, flags(DF);
output memory reference byte farptr(ES,dstidx);
modifies dstidx;
/* how to show it */
syntax ;
}
opcode sequence(0xAB) name "STOSW" {
/* if DF = 1, dstidx -= wordsize; */
/* if DF = 0, dstidx += wordsize; */
input accum, flags(DF);
output memory reference word farptr(ES,dstidx);
modifies dstidx;
/* how to show it */
syntax ;
}
opcode sequence(0xAC) name "LODSB" {
/* if DF = 1, srcidx -= 1; */
/* if DF = 0, srcidx += 1; */
input memory reference byte srcidx, flags(DF);
output AL;
modifies srcidx;
/* how to show it */
syntax ;
}
opcode sequence(0xAD) name "LODSW" {
/* if DF = 1, srcidx -= wordsize; */
/* if DF = 0, srcidx += wordsize; */
input memory reference word srcidx, flags(DF);
output accum;
modifies srcidx;
/* how to show it */
syntax ;
}
opcode sequence(0xAE) name "SCASB" {
/* if DF = 1, dstidx -= 1; */
/* if DF = 0, dstidx += 1; */
input AL,memory reference byte farptr(ES,dstidx), flags(DF);
modifies flags(CF,PF,AF,ZF,SF,OF);
/* how to show it */
syntax ;
}
opcode sequence(0xAF) name "SCASW" {
/* if DF = 1, dstidx -= wordsize; */
/* if DF = 0, dstidx += wordsize; */
input accum,memory reference word farptr(ES,dstidx), flags(DF);
modifies flags(CF,PF,AF,ZF,SF,OF);
/* how to show it */
syntax ;
}
opcode sequence([0xB0,0xB7] immb) name "MOV" {
reg index = opbyte(0) & 7;
common opcode "MOV" param(regb,immb);
}
opcode sequence([0xB8,0xBF] immw) name "MOV" {
reg index = opbyte(0) & 7;
common opcode "MOV" param(regw,immw);
}
opcode sequence(0xC2 immw) name "RET" {
common opcode "RET" param(immw);
}
opcode sequence(0xC3) name "RET" {
common opcode "RET" param(0);
}
opcode sequence(0xCA immw) name "RETF" {
common opcode "RETF" param(immw);
}
opcode sequence(0xCB) name "RETF" {
common opcode "RETF" param(0);
}
opcode sequence(0xCC) name "INT" {
common opcode "INT" param(3);
}
opcode sequence(0xCD immb) name "INT" {
common opcode "INT" param(immb);
}
opcode sequence(0xCE) name "INTO" {
input flags;
common opcode "INT" param(4);
}
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