mirror of
https://github.com/joncampbell123/dosbox-x.git
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249 lines
6.6 KiB
C
249 lines
6.6 KiB
C
/*
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* Copyright (C) 2002-2021 The DOSBox Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef DOSBOX_FPU_H
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#define DOSBOX_FPU_H
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#include "mmx.h"
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void FPU_ESC0_Normal(Bitu rm);
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void FPU_ESC0_EA(Bitu rm,PhysPt addr);
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void FPU_ESC1_Normal(Bitu rm);
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void FPU_ESC1_EA(Bitu rm,PhysPt addr);
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void FPU_ESC2_Normal(Bitu rm);
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void FPU_ESC2_EA(Bitu rm,PhysPt addr);
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void FPU_ESC3_Normal(Bitu rm);
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void FPU_ESC3_EA(Bitu rm,PhysPt addr);
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void FPU_ESC4_Normal(Bitu rm);
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void FPU_ESC4_EA(Bitu rm,PhysPt addr);
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void FPU_ESC5_Normal(Bitu rm);
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void FPU_ESC5_EA(Bitu rm,PhysPt addr);
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void FPU_ESC6_Normal(Bitu rm);
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void FPU_ESC6_EA(Bitu rm,PhysPt addr);
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void FPU_ESC7_Normal(Bitu rm);
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void FPU_ESC7_EA(Bitu rm,PhysPt addr);
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/* Floating point register, in the form the native host uses for "double".
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* This is slightly less precise than the 80-bit extended IEEE used by Intel,
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* but can be faster using the host processor "double" support. Most DOS games
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* using the FPU for 3D rendering are unaffected by the loss of precision.
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* However, there are cases where the full 80-bit precision is required such
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* as the "Fast Pentium memcpy trick" using the 80-bit versions of FLD/FST to
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* copy memory. */
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typedef union {
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double d;
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#ifndef WORDS_BIGENDIAN
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struct {
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uint32_t lower;
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int32_t upper;
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} l;
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#else
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struct {
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int32_t upper;
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uint32_t lower;
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} l;
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#endif
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int64_t ll;
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MMX_reg reg_mmx;
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} FPU_Reg;
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// dynamic x86 core needs this
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typedef struct {
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uint32_t m1;
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uint32_t m2;
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uint16_t m3;
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uint16_t d1;
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uint32_t d2;
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} FPU_P_Reg;
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// memory barrier macro. to ensure that reads/stores to one half of the FPU reg struct
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// do not overlap with reads/stores from the other half. things can go wrong if the
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// compiler writes code to write the mantissa, then load the overall as float, then store
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// the exponent. note this is not a hardware level memory barrier, this is a compiler
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// level memory barrier against the optimization engine.
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#if defined(__GCC__)
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# define FPU_Reg_m_barrier() __asm__ __volatile__ ("":::"memory")
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#else
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# define FPU_Reg_m_barrier()
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#endif
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#pragma pack(push,1)
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typedef union {
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// TODO: The configure script needs to use "long double" on x86/x86_64 and verify sizeof(long double) == 10,
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// else undef a macro to let the code emulate long double 80-bit IEEE. Also needs to determine host
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// byte order here so host long double matches our struct.
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struct {
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uint64_t mantissa; // [63:0]
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unsigned int exponent:15; // [78:64]
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unsigned int sign:1; // [79:79]
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} f;
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#if defined(HAS_LONG_DOUBLE)
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long double v; // [79:0]
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#endif
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struct {
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uint64_t l;
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uint16_t h;
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} raw;
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} FPU_Reg_80;
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// ^ Remember that in 80-bit extended, the mantissa contains both the fraction and integer bit. There is no
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// "implied bit" like 32-bit and 64-bit formats.
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#pragma pack(pop)
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#define FPU_Reg_80_exponent_bias (16383)
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#pragma pack(push,1)
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typedef union {
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struct {
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uint64_t mantissa:52; // [51:0]
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uint64_t exponent:11; // [62:52]
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uint64_t sign:1; // [63:63]
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} f;
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double v;
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uint64_t raw;
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} FPU_Reg_64;
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#pragma pack(pop)
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#define FPU_Reg_64_exponent_bias (1023)
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static const uint64_t FPU_Reg_64_implied_bit = ((uint64_t)1ULL << (uint64_t)52ULL);
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#pragma pack(push,1)
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typedef union {
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struct {
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uint32_t mantissa:23; // [22:0]
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uint32_t exponent:8; // [30:23]
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uint32_t sign:1; // [31:31]
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} f;
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float v;
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uint32_t raw;
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} FPU_Reg_32;
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#pragma pack(pop)
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#define FPU_Reg_32_exponent_bias (127)
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static const uint32_t FPU_Reg_32_implied_bit = ((uint32_t)1UL << (uint32_t)23UL);
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enum FPU_Tag {
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TAG_Valid = 0,
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TAG_Zero = 1,
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TAG_Weird = 2,
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TAG_Empty = 3
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};
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enum FPU_Round {
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ROUND_Nearest = 0,
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ROUND_Down = 1,
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ROUND_Up = 2,
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ROUND_Chop = 3
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};
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typedef struct {
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#if defined(HAS_LONG_DOUBLE)//probably shouldn't allow struct to change size based on this
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FPU_Reg _do_not_use__regs[9];
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#else
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FPU_Reg regs[9];
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#endif
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FPU_P_Reg p_regs[9];
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FPU_Reg_80 regs_80[9];
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#if defined(HAS_LONG_DOUBLE)//probably shouldn't allow struct to change size based on this
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bool _do_not_use__use80[9]; // if set, use the 80-bit precision version
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#else
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bool use80[9]; // if set, use the 80-bit precision version
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#endif
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FPU_Tag tags[9];
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uint16_t cw,cw_mask_all;
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uint16_t sw;
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uint32_t top;
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FPU_Round round;
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} FPU_rec;
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//get pi from a real library
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#define PI 3.14159265358979323846
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#define L2E 1.4426950408889634
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#define L2T 3.3219280948873623
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#define LN2 0.69314718055994531
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#define LG2 0.3010299956639812
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extern FPU_rec fpu;
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#define TOP fpu.top
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#define STV(i) ( (fpu.top+ (i) ) & 7 )
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uint16_t FPU_GetTag(void);
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void FPU_FLDCW(PhysPt addr);
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static INLINE void FPU_SetTag(uint16_t tag){
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for(Bitu i=0;i<8;i++)
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fpu.tags[i] = static_cast<FPU_Tag>((tag >>(2*i))&3);
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}
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static INLINE void FPU_SetCW(Bitu word){
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// HACK: Bits 13-15 are not defined. Apparently, one program likes to test for
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// Cyrix EMC87 by trying to set bit 15. We want the test program to see
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// us as an Intel 287 when cputype == 286.
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word &= 0x7FFF;
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fpu.cw = (uint16_t)word;
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fpu.cw_mask_all = (uint16_t)(word | 0x3f);
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fpu.round = (FPU_Round)((word >> 10) & 3);
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}
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static INLINE uint8_t FPU_GET_TOP(void) {
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return (fpu.sw & 0x3800U) >> 11U;
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}
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static INLINE void FPU_SET_TOP(Bitu val){
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fpu.sw &= ~0x3800U;
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fpu.sw |= (val & 7U) << 11U;
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}
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static INLINE void FPU_SET_C0(Bitu C){
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fpu.sw &= ~0x0100U;
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if(C) fpu.sw |= 0x0100U;
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}
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static INLINE void FPU_SET_C1(Bitu C){
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fpu.sw &= ~0x0200U;
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if(C) fpu.sw |= 0x0200U;
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}
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static INLINE void FPU_SET_C2(Bitu C){
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fpu.sw &= ~0x0400U;
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if(C) fpu.sw |= 0x0400U;
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}
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static INLINE void FPU_SET_C3(Bitu C){
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fpu.sw &= ~0x4000U;
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if(C) fpu.sw |= 0x4000U;
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}
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static INLINE void FPU_SET_D(Bitu C){
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fpu.sw &= ~0x0002U;
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if(C) fpu.sw |= 0x0002U;
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}
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static INLINE void FPU_LOG_WARN(Bitu tree, bool ea, Bitu group, Bitu sub) {
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LOG(LOG_FPU,LOG_WARN)("ESC %lu%s:Unhandled group %lu subfunction %lu",(long unsigned int)tree,ea?" EA":"",(long unsigned int)group,(long unsigned int)sub);
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}
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#endif
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