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Merging r366868:

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r366868 | rogfer01 | 2019-07-24 07:33:46 +0200 (Wed, 24 Jul 2019) | 6 lines

[RISCV] Implement benchmark::cycleclock::Now

This is a cherrypick of D64237 onto llvm/utils/benchmark and
libcxx/utils/google-benchmark.

Differential Revision: https://reviews.llvm.org/D65142
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git-svn-id: https://llvm.org/svn/llvm-project/libcxx/branches/release_90@367813 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hans Wennborg
2019-08-05 08:14:21 +00:00
parent cd281462e2
commit 1d53e6cb6d
2 changed files with 21 additions and 0 deletions
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6
utils/google-benchmark/README.LLVM
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@@ -4,3 +4,9 @@ LLVM notes
This directory contains the Google Benchmark source code with some unnecessary
files removed. Note that this directory is under a different license than
libc++.
Changes:
* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2
is applied on top of
https://github.com/google/benchmark/commit/4528c76b718acc9b57956f63069c699ae21edcab
to add RISC-V timer support.

15
utils/google-benchmark/src/cycleclock.h
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@@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
uint64_t tsc;
asm("stck %0" : "=Q"(tsc) : : "cc");
return tsc;
#elif defined(__riscv) // RISC-V
// Use RDCYCLE (and RDCYCLEH on riscv32)
#if __riscv_xlen == 32
uint64_t cycles_low, cycles_hi0, cycles_hi1;
asm("rdcycleh %0" : "=r"(cycles_hi0));
asm("rdcycle %0" : "=r"(cycles_lo));
asm("rdcycleh %0" : "=r"(cycles_hi1));
// This matches the PowerPC overflow detection, above
cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
return (cycles_hi1 << 32) | cycles_lo;
#else
uint64_t cycles;
asm("rdcycle %0" : "=r"(cycles));
return cycles;
#endif
#else
// The soft failover to a generic implementation is automatic only for ARM.
// For other platforms the developer is expected to make an attempt to create