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tcl/target/max32xxx: Add max3267x support

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Add configuration files for max32670, max32672 and max32675

Change-Id: I073db6294740bf46713134d75f718dfc7338156e
Signed-off-by: Henrik Mau <henrik.mau@analog.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8979
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Henrik Mau
2025-06-30 13:23:23 +01:00
committed by Antonio Borneo
parent a0ee225618
commit a2d0566a93
3 changed files with 99 additions and 0 deletions
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36
tcl/target/max32670.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# maxim Integrated OpenOCD target configuration file
# reset pin configuration
reset_config none
adapter_nsrst_delay 200
adapter_nsrst_assert_width 200
# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x60000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_OPTIONS 0x01
# Use Serial Wire Debug
transport select swd
source [find target/max32xxx.cfg]
# Early revisions of the MAX32670 will disable SWD upon reset. There are reserved address locations
# in the ROM code that can be used to insert breakpoints.
# This workaround will enable SWD for affected revisions.
$_CHIPNAME.cpu configure -event reset-assert-pre {
if {$halt} {catch {bp 0x00002174 2 hw}}
}
$_CHIPNAME.cpu configure -event reset-deassert-post {
if {$halt} {
$::_CHIPNAME.cpu arp_poll
$::_CHIPNAME.cpu arp_poll
$::_CHIPNAME.cpu arp_halt
rbp 0x00002174
}
}

27
tcl/target/max32672.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# maxim Integrated OpenOCD target configuration file
# reset pin configuration
reset_config none
adapter_nsrst_delay 200
adapter_nsrst_assert_width 200
# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x80000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_OPTIONS 0x01
# Use Serial Wire Debug
transport select swd
source [find target/max32xxx.cfg]
# Add additional flash bank
set FLASH_BASE 0x10080000
set FLC_BASE 0x40029400
flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS

36
tcl/target/max32675.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# maxim Integrated OpenOCD target configuration file
# reset pin configuration
reset_config none
adapter_nsrst_delay 200
adapter_nsrst_assert_width 200
# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x60000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_OPTIONS 0x01
# Use Serial Wire Debug
transport select swd
source [find target/max32xxx.cfg]
# Early revisions of the MAX3275 will disable SWD upon reset. There are reserved address locations
# in the ROM code that can be used to insert breakpoints.
# This workaround will enable SWD for affected revisions.
$_CHIPNAME.cpu configure -event reset-assert-pre {
if {$halt} {catch {bp 0x00002174 2 hw}}
}
$_CHIPNAME.cpu configure -event reset-deassert-post {
if {$halt} {
$::_CHIPNAME.cpu arp_poll
$::_CHIPNAME.cpu arp_poll
$::_CHIPNAME.cpu arp_halt
rbp 0x00002174
}
}