target/arm_adi: add URLs of latest ARM ADI spec

While on it warn about screwed SWD diagrams in ADI spec
and add reference to a SWD timing diagram.

Change-Id: I628d707ebf8ce7c22ba19bdcfd06028d4eaa60f8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8690
Tested-by: jenkins

src/jtag/swd.h

@@ -270,6 +270,7 @@ struct swd_driver {
 	 * @param Where to store value to read from register
 	 * @param ap_delay_hint Number of idle cycles that may be
 	 * needed after an AP access to avoid WAITs
+	 * or zero in case of DP read.
 	 */
 	void (*read_reg)(uint8_t cmd, uint32_t *value, uint32_t ap_delay_hint);
 
@@ -280,6 +281,7 @@ struct swd_driver {
 	 * @param Value to be written to the register
 	 * @param ap_delay_hint Number of idle cycles that may be
 	 * needed after an AP access to avoid WAITs
+	 * or zero in case of DP write.
 	 */
 	void (*write_reg)(uint8_t cmd, uint32_t value, uint32_t ap_delay_hint);
 

src/target/arm_adi_v5.c

@@ -50,8 +50,16 @@
 /*
  * Relevant specifications from ARM include:
  *
- * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031F
+ * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031G
+ * https://developer.arm.com/documentation/ihi0031/latest/
+ *
  * ARM(tm) Debug Interface v6 Architecture Specification    ARM IHI 0074C
+ * https://developer.arm.com/documentation/ihi0074/latest/
+ *
+ * Note that diagrams B4-1 to B4-7 in both ADI specifications show
+ * SWCLK signal mostly in wrong polarity. See detailed SWD timing
+ * https://developer.arm.com/documentation/dui0499/b/arm-dstream-target-interface-connections/swd-timing-requirements
+ *
  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  *
  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D