Andreas Färber 8e5eaac529 tcl/interface/ftdi: Add Digilent JTAG-HS3 config
Derived from tcl/interface/digilent-hs1.cfg.

JTAG-HS3 has an open drain buffer on pin 14 for SRST to work with
PS_SRST_B on Xilinx Zynq SoC.

Change-Id: I1e9e72d0511528a61207e318aff937ae9fad5bf9
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2728
Tested-by: jenkins
Reviewed-by: Robert Jordens <jordens@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-09-30 22:10:36 +01:00
..
2012-10-02 22:03:38 +00:00
2013-07-08 09:31:28 +00:00
2013-08-29 07:56:38 +00:00
2013-12-14 21:54:11 +00:00