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https://github.com/ptitSeb/box64.git
synced 2025-05-09 00:21:32 +08:00
[RV64_DYNAREC] Added E0/E1/E2/E3 opcodes
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6b9d617fa6
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@ -621,6 +621,58 @@ uintptr_t dynarec64_00_3(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int
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case 0xDF:
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addr = dynarec64_DF(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
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break;
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#define GO(Z) \
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BARRIER(BARRIER_MAYBE); \
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JUMP(addr+i8, 1); \
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if(dyn->insts[ninst].x64.jmp_insts==-1 || \
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CHECK_CACHE()) { \
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/* out of the block */ \
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i32 = dyn->insts[ninst].epilog-(dyn->native_size); \
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if(Z) {BNE(xRCX, xZR, i32);} else {BEQ(xRCX, xZR, i32);}; \
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if(dyn->insts[ninst].x64.jmp_insts==-1) { \
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if(!(dyn->insts[ninst].x64.barrier&BARRIER_FLOAT)) \
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fpu_purgecache(dyn, ninst, 1, x1, x2, x3); \
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jump_to_next(dyn, addr+i8, 0, ninst); \
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} else { \
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CacheTransform(dyn, ninst, cacheupd, x1, x2, x3); \
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i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size); \
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B(i32); \
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} \
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} else { \
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/* inside the block */ \
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i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size); \
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if(Z) {BEQ(xRCX, xZR, i32);} else {BNE(xRCX, xZR, i32);}; \
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}
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case 0xE0:
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INST_NAME("LOOPNZ");
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READFLAGS(X_ZF);
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i8 = F8S;
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SUBI(xRCX, xRCX, 1);
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ANDI(x1, xFlags, 1 << F_ZF);
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CBNZ_NEXT(x1);
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GO(0);
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break;
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case 0xE1:
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INST_NAME("LOOPZ");
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READFLAGS(X_ZF);
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i8 = F8S;
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SUBI(xRCX, xRCX, 1);
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ANDI(x1, xFlags, 1 << F_ZF);
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CBZ_NEXT(x1);
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GO(0);
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break;
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case 0xE2:
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INST_NAME("LOOP");
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i8 = F8S;
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SUBI(xRCX, xRCX, 1);
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GO(0);
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break;
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case 0xE3:
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INST_NAME("JECXZ");
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i8 = F8S;
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GO(1);
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break;
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#undef GO
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case 0xE8:
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INST_NAME("CALL Id");
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@ -334,7 +334,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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}
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} else {
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if (rex.w) {
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LI(x2, 0xff);
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MOV_U12(x2, 0xff);
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SLLI(x1, gd, 56);
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SRLI(x3, gd, 56);
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SRLI(x4, gd, 40);
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@ -365,7 +365,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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AND(x3, x3, x4);
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OR(gd, x1, x3);
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} else {
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LI(x2, 0xff);
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MOV_U12(x2, 0xff);
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SLLIW(x2, x2, 8);
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SLLIW(x1, gd, 24);
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SRLIW(x3, gd, 24);
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@ -393,7 +393,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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}
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} else {
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if (rex.w) {
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LI(x2, 0xff);
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MOV_U12(x2, 0xff);
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SLLI(x1, gd, 56);
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SRLI(x3, gd, 56);
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SRLI(x4, gd, 40);
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@ -424,7 +424,7 @@ uintptr_t dynarec64_0F(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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AND(x3, x3, x4);
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OR(x1, x1, x3);
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} else {
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LI(x2, 0xff);
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MOV_U12(x2, 0xff);
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SLLIW(x2, x2, 8);
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SLLIW(x1, gd, 24);
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SRLIW(x3, gd, 24);
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@ -567,6 +567,63 @@ uintptr_t dynarec64_67(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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}
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}
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break;
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#define GO(Z) \
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BARRIER(BARRIER_MAYBE); \
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JUMP(addr+i8, 1); \
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if(dyn->insts[ninst].x64.jmp_insts==-1 || \
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CHECK_CACHE()) { \
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/* out of the block */ \
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i32 = dyn->insts[ninst].epilog-(dyn->native_size); \
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if(Z) {BNE(x1, xZR, i32);} else {BEQ(x1, xZR, i32);}; \
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if(dyn->insts[ninst].x64.jmp_insts==-1) { \
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if(!(dyn->insts[ninst].x64.barrier&BARRIER_FLOAT)) \
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fpu_purgecache(dyn, ninst, 1, x1, x2, x3); \
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jump_to_next(dyn, addr+i8, 0, ninst); \
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} else { \
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CacheTransform(dyn, ninst, cacheupd, x1, x2, x3); \
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i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size); \
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B(i32); \
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} \
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} else { \
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/* inside the block */ \
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i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size); \
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if(Z) {BEQ(x1, xZR, i32);} else {BNE(x1, xZR, i32);}; \
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}
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case 0xE0:
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INST_NAME("LOOPNZ (32bits)");
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READFLAGS(X_ZF);
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i8 = F8S;
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SUBI(xRCX, xRCX, 1);
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ANDI(x1, xFlags, 1 << F_ZF);
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CBNZ_NEXT(x1);
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AND(x1, xRCX, xMASK);
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GO(0);
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break;
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case 0xE1:
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INST_NAME("LOOPZ (32bits)");
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READFLAGS(X_ZF);
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i8 = F8S;
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SUBI(xRCX, xRCX, 1);
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ANDI(x1, xFlags, 1 << F_ZF);
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CBZ_NEXT(x1);
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AND(x1, xRCX, xMASK);
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GO(0);
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break;
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case 0xE2:
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INST_NAME("LOOP (32bits)");
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i8 = F8S;
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SUBI(xRCX, xRCX, 1);
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AND(x1, xRCX, xMASK);
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GO(0);
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break;
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case 0xE3:
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INST_NAME("JECXZ (32bits)");
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i8 = F8S;
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AND(x1, xRCX, xMASK);
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GO(1);
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break;
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#undef GO
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default:
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DEFAULT;
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}
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@ -129,7 +129,6 @@ f28–31 ft8–11 FP temporaries Caller
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// put imm20 in the [31:12] bits of rd, zero [11:0] and sign extend bits31
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#define LUI(rd, imm20) EMIT(U_type((imm20)<<12, rd, 0b0110111))
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#define LI(rd, imm12) if (imm12 < 0x800) { ADDI(rd, xZR, imm12);} else {LUI(rd, 1); ADDIW(rd, rd, -(0x1000 - imm12));}
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// put PC+imm20 in rd
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#define AUIPC(rd, imm20) EMIT(U_type((imm20)<<12, rd, 0b0010111))
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