diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
index 50e741153..25286e1d9 100644
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -182,7 +182,7 @@ jobs:
             INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=false,zba=true,zbb=true,zbc=true,zbs=true ctest --timeout 60 -j$(nproc) --repeat until-pass:20 --output-on-failure
             INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=true,vlen=128,vext_spec=v1.0 ctest --timeout 60 -j$(nproc) --repeat until-pass:20 --output-on-failure
             INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=true,vlen=256,vext_spec=v1.0 ctest --timeout 60 -j$(nproc) --repeat until-pass:20 --output-on-failure
-            INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,v=false,xtheadba=true,xtheadba=true,xtheadbb=true,xtheadbs=true,xtheadcondmov=true,xtheadmemidx=true,xtheadmempair=true,xtheadfmemidx=true,xtheadmac=true,xtheadfmv=true ctest --timeout 60 -j$(nproc) --repeat until-pass:20 --output-on-failure
+            INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=thead-c906 ctest --timeout 60 -j$(nproc) --repeat until-pass:20 --output-on-failure
             if [[ ${{ env.BOX64_BOX32 }} != 1 ]]; then
             INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ BOX64_DYNAREC_TEST=2 ctest --timeout 60 -j$(nproc) --repeat until-pass:20 --output-on-failure
             INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ BOX64_DYNAREC_TEST=2 QEMU_CPU=rv64,v=false,zba=true,zbb=true,zbc=true,zbs=true ctest --timeout 60 -j$(nproc) --repeat until-pass:20 --output-on-failure
diff --git a/src/dynarec/rv64/rv64_printer.c b/src/dynarec/rv64/rv64_printer.c
index 1b84ea7c7..0e87d9a7a 100644
--- a/src/dynarec/rv64/rv64_printer.c
+++ b/src/dynarec/rv64/rv64_printer.c
@@ -7,6 +7,16 @@
 #include "rv64_printer.h"
 #include "debug.h"
 
+extern int rv64_xtheadba;
+extern int rv64_xtheadbb;
+extern int rv64_xtheadbs;
+extern int rv64_xtheadcondmov;
+extern int rv64_xtheadmemidx;
+extern int rv64_xtheadmempair;
+extern int rv64_xtheadfmemidx;
+extern int rv64_xtheadmac;
+extern int rv64_xtheadfmv;
+
 static const char gpr[32][9] = {
     "zero",
     "ra",
@@ -178,6 +188,180 @@ const char* rv64_print(uint32_t opcode, uintptr_t addr)
     static char buff[200];
     rv64_print_t a;
 
+    if (rv64_xtheadba || rv64_xtheadbb || rv64_xtheadbs || rv64_xtheadcondmov || rv64_xtheadmempair) {
+
+        /****************
+         *  Generated by https://github.com/ksco/riscv-opcodes/tree/box64_printer
+         *  Command: python parse.py -box64 rv_xtheadba rv_xtheadbb rv_xtheadbs rv_xtheadcondmov rv_xtheadmempair > code.c
+         *  Please do NOT edit the following code manually.
+         */
+
+        // rv_xtheadba, TH.ADDSL
+        if ((opcode & 0xf800707f) == 0x100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            a.rs2 = FX(opcode, 24, 20);
+            a.imm = FX(opcode, 26, 25);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, %s, 0x%x(%d)", "TH.ADDSL", gpr[a.rd], gpr[a.rs1], gpr[a.rs2], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.EXT
+        if ((opcode & 0x707f) == 0x200b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm2 = FX(opcode, 31, 26);
+            a.imm = FX(opcode, 25, 20);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%x(%d), 0x%x(%d)", "TH.EXT", gpr[a.rd], gpr[a.rs1], a.imm2, a.imm2, a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.EXTU
+        if ((opcode & 0x707f) == 0x300b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm2 = FX(opcode, 31, 26);
+            a.imm = FX(opcode, 25, 20);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%x(%d), 0x%x(%d)", "TH.EXTU", gpr[a.rd], gpr[a.rs1], a.imm2, a.imm2, a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.FF0
+        if ((opcode & 0xfff0707f) == 0x8400100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s", "TH.FF0", gpr[a.rd], gpr[a.rs1]);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.FF1
+        if ((opcode & 0xfff0707f) == 0x8600100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s", "TH.FF1", gpr[a.rd], gpr[a.rs1]);
+            return buff;
+        }
+
+        // rv_xtheadmempair, TH.LDD
+        if ((opcode & 0xf800707f) == 0xf800400b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs2 = FX(opcode, 24, 20);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm = FX(opcode, 26, 25);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, %s, 0x%x(%d)", "TH.LDD", gpr[a.rd], gpr[a.rs2], gpr[a.rs1], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadmempair, TH.LWD
+        if ((opcode & 0xf800707f) == 0xe000400b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs2 = FX(opcode, 24, 20);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm = FX(opcode, 26, 25);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, %s, 0x%x(%d)", "TH.LWD", gpr[a.rd], gpr[a.rs2], gpr[a.rs1], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadmempair, TH.LWUD
+        if ((opcode & 0xf800707f) == 0xf000400b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs2 = FX(opcode, 24, 20);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm = FX(opcode, 26, 25);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, %s, 0x%x(%d)", "TH.LWUD", gpr[a.rd], gpr[a.rs2], gpr[a.rs1], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadcondmov, TH.MVEQZ
+        if ((opcode & 0xfe00707f) == 0x4000100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            a.rs2 = FX(opcode, 24, 20);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "TH.MVEQZ", gpr[a.rd], gpr[a.rs1], gpr[a.rs2]);
+            return buff;
+        }
+
+        // rv_xtheadcondmov, TH.MVNEZ
+        if ((opcode & 0xfe00707f) == 0x4200100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            a.rs2 = FX(opcode, 24, 20);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, %s", "TH.MVNEZ", gpr[a.rd], gpr[a.rs1], gpr[a.rs2]);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.REV
+        if ((opcode & 0xfff0707f) == 0x8200100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s", "TH.REV", gpr[a.rd], gpr[a.rs1]);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.REVW
+        if ((opcode & 0xfff0707f) == 0x9000100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s", "TH.REVW", gpr[a.rd], gpr[a.rs1]);
+            return buff;
+        }
+
+        // rv_xtheadmempair, TH.SDD
+        if ((opcode & 0xf800707f) == 0xf800500b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs2 = FX(opcode, 24, 20);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm = FX(opcode, 26, 25);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, %s, 0x%x(%d)", "TH.SDD", gpr[a.rd], gpr[a.rs2], gpr[a.rs1], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.SRRI
+        if ((opcode & 0xfc00707f) == 0x1000100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm = FX(opcode, 25, 20);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%x(%d)", "TH.SRRI", gpr[a.rd], gpr[a.rs1], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.SRRIW
+        if ((opcode & 0xfe00707f) == 0x1400100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm = FX(opcode, 24, 20);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%x(%d)", "TH.SRRIW", gpr[a.rd], gpr[a.rs1], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadmempair, TH.SWD
+        if ((opcode & 0xf800707f) == 0xe000500b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs2 = FX(opcode, 24, 20);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm = FX(opcode, 26, 25);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, %s, 0x%x(%d)", "TH.SWD", gpr[a.rd], gpr[a.rs2], gpr[a.rs1], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadbs, TH.TST
+        if ((opcode & 0xfc00707f) == 0x8800100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            a.imm = FX(opcode, 25, 20);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s, 0x%x(%d)", "TH.TST", gpr[a.rd], gpr[a.rs1], a.imm, a.imm);
+            return buff;
+        }
+
+        // rv_xtheadbb, TH.TSTNBZ
+        if ((opcode & 0xfff0707f) == 0x8000100b) {
+            a.rd = FX(opcode, 11, 7);
+            a.rs1 = FX(opcode, 19, 15);
+            snprintf(buff, sizeof(buff), "%-15s %s, %s", "TH.TSTNBZ", gpr[a.rd], gpr[a.rs1]);
+            return buff;
+        }
+    }
+
     /****************
      *  Generated by https://github.com/ksco/riscv-opcodes/tree/box64_printer
      *  Command: python parse.py -box64 rv_a rv_d rv_f rv_i rv_m rv_v rv_zba rv_zbb rv_zbc rv_zicsr rv_zbs rv64_a rv64_d rv64_f rv64_i rv64_m rv64_zba rv64_zbb rv64_zbs > code.c