mirror of
https://github.com/riscv-software-src/riscv-isa-sim.git
synced 2025-10-14 10:38:57 +08:00

We add an abstract interrupt controller interface which can be used by devices to trigger wired interrupts. Signed-off-by: Anup Patel <anup@brainfault.org>
15 lines
336 B
C++
15 lines
336 B
C++
#ifndef _RISCV_ABSTRACT_INTERRUPT_CONTROLLER_H
|
|
#define _RISCV_ABSTRACT_INTERRUPT_CONTROLLER_H
|
|
|
|
#include "decode.h"
|
|
#include <cstdint>
|
|
#include <cstddef>
|
|
|
|
class abstract_interrupt_controller_t {
|
|
public:
|
|
virtual void set_interrupt_level(uint32_t interrupt_id, int level) = 0;
|
|
virtual ~abstract_interrupt_controller_t() {}
|
|
};
|
|
|
|
#endif
|