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https://github.com/riscv-software-src/riscv-isa-sim.git
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9b2a1d6c81
Adds DCSR.MPRVEN bit support, as specified in RISC-V External Debug Support Version 1.0.0-rc4 (https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc4, see 4.9.1 Debug Control and Status). This bit allows to enable hardware virtual address translation when memory access is initiated by the debugger (see 4.1 Debug Mode, clause 2). This change: * Increases debug specification coverage, allows more detailed testing of external debuggers with Spike. * Decreases the number of required abstract commands to read virtual memory thus improving the user experience. Commit's changes: * Added MPRVEN field to DCSR register * Updated debug_rom.S to turn off MPRVEN on memory access To avoid unwanted address translation while debug_rom.S executed DCSR.MPRVEN bit has to be cleared before and restored after access. Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
116 lines
3.8 KiB
ArmAsm
Executable File
116 lines
3.8 KiB
ArmAsm
Executable File
// See LICENSE.SiFive for license details.
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#include "riscv/encoding.h"
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#include "riscv/debug_rom_defines.h"
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.option norvc
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.global entry
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.global exception
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// This macro handles mem access with proper management of the MPRVEN
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// Usage: MEMORY_ACCESS_WITH_MPRV(<your code>)
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#define MEMORY_ACCESS_WITH_MPRV(...) \
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csrrci s0, CSR_DCSR, DCSR_MPRVEN; \
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andi s0, s0, DCSR_MPRVEN; \
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bnez s0, 1f; \
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__VA_ARGS__; \
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j 2f; \
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1: \
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__VA_ARGS__; \
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csrrsi zero, CSR_DCSR, DCSR_MPRVEN; \
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2:
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// Entry location on ebreak, Halt, or Breakpoint
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// It is the same for all harts. They branch when
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// their GO or RESUME bit is set.
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entry:
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jal zero, _entry
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resume:
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// Not used.
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jal zero, _resume
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exception:
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jal zero, _exception
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_entry:
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// This fence is required because the execution may have written something
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// into the Abstract Data or Program Buffer registers.
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fence
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csrw CSR_DSCRATCH0, s0 // Save s0 to allow signaling MHARTID
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// We continue to let the hart know that we are halted in order that
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// a DM which was reset is still made aware that a hart is halted.
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// We keep checking both whether there is something the debugger wants
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// us to do, or whether we should resume.
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entry_loop:
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// 1 byte flag per hart. Only one hart advances here.
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MEMORY_ACCESS_WITH_MPRV(
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csrr s0, CSR_MHARTID;
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sw s0, DEBUG_ROM_HALTED(zero);
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lbu s0, DEBUG_ROM_FLAGS(s0);
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)
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andi s0, s0, (1 << DEBUG_ROM_FLAG_GO)
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bnez s0, going
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// multiple harts can resume here
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MEMORY_ACCESS_WITH_MPRV(
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csrr s0, CSR_MHARTID;
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lbu s0, DEBUG_ROM_FLAGS(s0);
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)
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andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME)
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bnez s0, _resume
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wfi
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jal zero, entry_loop
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_exception:
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// Restore S0, which we always save to dscratch.
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// We need this in case the user tried an abstract write to a
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// non-existent CSR.
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// Let debug module know you got an exception.
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MEMORY_ACCESS_WITH_MPRV(
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csrr s0, CSR_DSCRATCH0;
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sw zero, DEBUG_ROM_EXCEPTION(zero);
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)
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ebreak
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going:
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// When debug module sees this write, the GO flag is reset.
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MEMORY_ACCESS_WITH_MPRV(
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csrr s0, CSR_MHARTID;
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sw s0, DEBUG_ROM_GOING(zero);
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)
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csrr s0, CSR_DSCRATCH0 // Restore s0 here
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fence
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fence.i
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jalr zero, zero, %lo(whereto) // Debug module will put different instructions and data in the RAM,
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// so we use fence and fence.i for safety. (rocket-chip doesn't have this
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// because jalr is special there)
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_resume:
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// When Debug Module sees this write, the RESUME flag is reset.
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MEMORY_ACCESS_WITH_MPRV(
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csrr s0, CSR_MHARTID;
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sw s0, DEBUG_ROM_RESUMING(zero);
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)
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csrr s0, CSR_DSCRATCH0 // Restore s0
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dret
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// END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT.
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.section .whereto
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whereto:
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nop
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// Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer,
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// or jal x0 resume, as desired.
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// Debug Module state machine tracks what is 'desired'.
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// We don't need/want to use jalr here because all of the
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// Variable ROM contents are set by
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// Debug Module before setting the OK_GO byte.
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