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https://github.com/riscv-software-src/riscv-isa-sim.git
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46 lines
738 B
ArmAsm
46 lines
738 B
ArmAsm
.option norvc
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.global _entry
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.global fromhost
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.global tohost
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.text
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_entry:
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la t0, exception_handler
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csrw mtvec, t0
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csrr t1, mstatus
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# Setting bit number 9 (mstatus.VS)
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li t2, 1
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slli t2, t2, 9
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or t1, t1, t2
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# Setting bit number 13 (mstatus.FS)
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li t3, 1
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slli t3, t3, 13
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or t1, t1, t3
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csrw mstatus, t1
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la t0, SNIPPY_ENTRY
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jalr t0
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exception_handler:
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csrr x10, mcause
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# In case of breakpoint (Interrupt = 0, Exception code = 3) we finalize.
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# Otherwise it's not the expected behavior and we go into an infinite loop.
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li x11, 3
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beq x10, x11, exit
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j infinite_loop
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exit:
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li ra, 1
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la sp, tohost
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sd ra, 0(sp)
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infinite_loop:
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j infinite_loop
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.balign 64
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tohost:
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.8byte 0x0
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.balign 64
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fromhost:
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.8byte 0x0
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