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Hyphenate exception names (#1996)

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Manual merge of #1994.
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6
marchid.md
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@ -16,13 +16,13 @@ requests against this repository to request the allocation of an architecture
ID.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Project Name | Maintainers | Point of Contact | Architecture ID | Project URL
Project Name | Maintainers | Point of Contact | Architecture ID | Project URL
------------- | ------------------------------- | ----------------------------------------------------------- | ----------------- | ---------------------------------------------------
Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/chipsalliance/rocket-chip
BOOM | UC Berkeley | [Christopher Celio](mailto:celio@berkeley.edu) | 2 | https://github.com/riscv-boom/riscv-boom
CVA6 | OpenHW Group | [Florian Zaruba](mailto:florian@openhwgroup.org), OpenHW Group | 3 | https://github.com/openhwgroup/cva6
CVA6 | OpenHW Group | [Florian Zaruba](mailto:florian@openhwgroup.org), OpenHW Group | 3 | https://github.com/openhwgroup/cva6
CV32E40P | OpenHW Group | [Davide Schiavone](mailto:davide@openhwgroup.org), OpenHW Group | 4 | https://github.com/openhwgroup/cv32e40p
Spike | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 5 | https://github.com/riscv/riscv-isa-sim
Spike | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 5 | https://github.com/riscv/riscv-isa-sim
E-Class | IIT Madras | [Neel Gala](mailto:neelgala@gmail.com) | 6 | https://gitlab.com/shaktiproject/cores/e-class
ORCA | VectorBlox | [Joel Vandergriendt](mailto:joel@vectorblox.com) | 7 | https://github.com/vectorblox/orca
SCR1 | Syntacore | [Dmitri Pavlov](mailto:dmitri.pavlov@syntacore.com), Syntacore| 8 | https://github.com/syntacore/scr1

64
src/cmo.adoc
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@ -302,17 +302,17 @@ described in the <<#csr_state>> section, or due to the address translation and
protection mechanisms. The trapping behavior of CMO instructions is described in
the following sections.
===== Illegal Instruction and Virtual Instruction Exceptions
===== Illegal-Instruction and Virtual-Instruction Exceptions
Cache-block management instructions and cache-block zero instructions may raise
illegal instruction exceptions or virtual instruction exceptions depending on
illegal-instruction exceptions or virtual-instruction exceptions depending on
the current privilege mode and the state of the CMO control registers described
in the <<#csr_state>> section.
Cache-block prefetch instructions raise neither illegal instruction exceptions
nor virtual instruction exceptions.
Cache-block prefetch instructions raise neither illegal-instruction exceptions
nor virtual-instruction exceptions.
===== Page Fault, Guest-Page Fault, and Access Fault Exceptions
===== Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions
Similar to load and store instructions, CMO instructions are explicit memory
access instructions that compute an effective address. The effective address is
@ -352,8 +352,8 @@ instruction is permitted to access the physical addresses, but an instruction
fetch is permitted to access the physical addresses, whether a cache-block
management instruction is permitted to access the cache block is UNSPECIFIED. If
access to the cache block is not permitted, a cache-block management instruction
raises a store page fault or store guest-page fault exception if address
translation does not permit any access or raises a store access fault exception
raises a store page-fault or store guest-page-fault exception if address
translation does not permit any access or raises a store access-fault exception
otherwise. During address translation, the instruction also checks the accessed
bit and may either raise an exception or set the bit as required.
@ -370,9 +370,9 @@ A cache-block zero instruction is permitted to access the specified cache block
whenever a store instruction is permitted to access the corresponding physical
addresses and when the PMAs indicate that cache-block zero instructions are a
supported access type. If access to the cache block is not permitted, a
cache-block zero instruction raises a store page fault or store guest-page fault
cache-block zero instruction raises a store page-fault or store guest-page-fault
exception if address translation does not permit write access or raises a store
access fault exception otherwise. During address translation, the instruction
access-fault exception otherwise. During address translation, the instruction
also checks the accessed and dirty bits and may either raise an exception or set
the bits as required.
@ -384,7 +384,7 @@ exceptions and shall not access any caches or memory. During address
translation, the instruction does _not_ check the accessed and dirty bits and
neither raises an exception nor sets the bits.
When a page fault, guest-page fault, or access fault exception is taken, the
When a page-fault, guest-page-fault, or access-fault exception is taken, the
relevant *tval CSR is written with the faulting effective address (i.e. the
value of _rs1_).
@ -400,9 +400,9 @@ management instructions like store/AMO instructions, so store/AMO exceptions are
appropriate for these instructions, regardless of the permissions required._
====
===== Address Misaligned Exceptions
===== Address-Misaligned Exceptions
CMO instructions do _not_ generate address misaligned exceptions.
CMO instructions do _not_ generate address-misaligned exceptions.
===== Breakpoint Exceptions and Debug Mode Entry
@ -557,7 +557,7 @@ generic format:
Enables the execution of the cache block invalidate instruction, `CBO.INVAL`, in
a lower privilege mode:
* `00`: The instruction raises an illegal instruction or virtual instruction
* `00`: The instruction raises an illegal-instruction or virtual-instruction
exception
* `01`: The instruction is executed and performs a flush operation
* `10`: _Reserved_
@ -568,7 +568,7 @@ a lower privilege mode:
Enables the execution of the cache block clean instruction, `CBO.CLEAN`, and the
cache block flush instruction, `CBO.FLUSH`, in a lower privilege mode:
* `0`: The instruction raises an illegal instruction or virtual instruction
* `0`: The instruction raises an illegal-instruction or virtual-instruction
exception
* `1`: The instruction is executed
@ -577,7 +577,7 @@ cache block flush instruction, `CBO.FLUSH`, in a lower privilege mode:
Enables the execution of the cache block zero instruction, `CBO.ZERO`, in a
lower privilege mode:
* `0`: The instruction raises an illegal instruction or virtual instruction
* `0`: The instruction raises an illegal-instruction or virtual-instruction
exception
* `1`: The instruction is executed
@ -586,24 +586,24 @@ lower privilege mode:
The x{csrname} registers control CBO instruction execution based on the current
privilege mode and the state of the appropriate CSRs, as detailed below.
A `CBO.INVAL` instruction executes or raises either an illegal instruction
exception or a virtual instruction exception based on the state of the
A `CBO.INVAL` instruction executes or raises either an illegal-instruction
exception or a virtual-instruction exception based on the state of the
`x{csrname}.CBIE` fields:
[source,sail,subs="attributes+"]
--
// illegal instruction exceptions
// illegal-instruction exceptions
if (((priv_mode != M) && (m{csrname}.CBIE == 00)) ||
((priv_mode == U) && (s{csrname}.CBIE == 00)))
{
<raise illegal instruction exception>
<raise illegal-instruction exception>
}
// virtual instruction exceptions
// virtual-instruction exceptions
else if (((priv_mode == VS) && (h{csrname}.CBIE == 00)) ||
((priv_mode == VU) && ((h{csrname}.CBIE == 00) || (s{csrname}.CBIE == 00))))
{
<raise virtual instruction exception>
<raise virtual-instruction exception>
}
// execute instruction
else
@ -640,23 +640,23 @@ either traps or performs a flush operation in a lower privileged level._
====
A `CBO.CLEAN` or `CBO.FLUSH` instruction executes or raises an illegal
instruction or virtual instruction exception based on the state of the
instruction or virtual-instruction exception based on the state of the
`x{csrname}.CBCFE` bits:
[source,sail,subs="attributes+"]
--
// illegal instruction exceptions
// illegal-instruction exceptions
if (((priv_mode != M) && !m{csrname}.CBCFE) ||
((priv_mode == U) && !s{csrname}.CBCFE))
{
<raise illegal instruction exception>
<raise illegal-instruction exception>
}
// virtual instruction exceptions
// virtual-instruction exceptions
else if (((priv_mode == VS) && !h{csrname}.CBCFE) ||
((priv_mode == VU) && !(h{csrname}.CBCFE && s{csrname}.CBCFE)))
{
<raise virtual instruction exception>
<raise virtual-instruction exception>
}
// execute instruction
else
@ -666,23 +666,23 @@ else
--
Finally, a `CBO.ZERO` instruction executes or raises an illegal instruction or
virtual instruction exception based on the state of the `x{csrname}.CBZE` bits:
Finally, a `CBO.ZERO` instruction executes or raises an illegal-instruction or
virtual-instruction exception based on the state of the `x{csrname}.CBZE` bits:
[source,sail,subs="attributes+"]
--
// illegal instruction exceptions
// illegal-instruction exceptions
if (((priv_mode != M) && !m{csrname}.CBZE) ||
((priv_mode == U) && !s{csrname}.CBZE))
{
<raise illegal instruction exception>
<raise illegal-instruction exception>
}
// virtual instruction exceptions
// virtual-instruction exceptions
else if (((priv_mode == VS) && !h{csrname}.CBZE) ||
((priv_mode == VU) && !(h{csrname}.CBZE && s{csrname}.CBZE)))
{
<raise virtual instruction exception>
<raise virtual-instruction exception>
}
// execute instruction
else

4
src/hypervisor.adoc
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@ -334,7 +334,7 @@ corresponding `hedeleg` bit is set. Each bit of `hedeleg` shall be
either writable or read-only zero. Many bits of `hedeleg` are required
specifically to be writable or zero, as enumerated in
<<hedeleg-bits>>. Bit 0, corresponding to
instruction address misaligned exceptions, must be writable if
instruction address-misaligned exceptions, must be writable if
IALIGN=32.
[NOTE]
@ -708,7 +708,7 @@ apply when `V=1`:
* 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop.
* The `pte.xwr=010b` encoding in VS-stage page tables becomes reserved.
* The `senvcfg.SSE` field will read as zero and is read-only.
* When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises a virtual instruction
* When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises a virtual-instruction
exception.
The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `henvcfg`.

22
src/indirect-csr.adoc
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@ -115,7 +115,7 @@ which the `miselect` value is allocated.
[NOTE]
====
Ordinarily, each `mireg`*_i_* will access register state, access
read-only 0 state, or raise an illegal instruction exception.
read-only 0 state, or raise an illegal-instruction exception.
For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is recommended that the lower 32 bits of the register are accessed through one of `mireg`, `mireg2`, or `mireg3`, while the upper 32 bits are accessed through `mireg4`, `mireg5`, or `mireg6`, respectively.
====
@ -170,7 +170,7 @@ holds a value that is not implemented at supervisor level, is UNSPECIFIED.
[%unbreakable]
[NOTE]
====
It is recommended that implementations raise an illegal instruction
It is recommended that implementations raise an illegal-instruction
exception for such accesses, to facilitate possible emulation (by
M-mode) of these accesses.
====
@ -194,7 +194,7 @@ allocated.
====
Ordinarily, each `sireg`*_i_* will access register state, access
read-only 0 state, or, unless executing in a virtual machine (covered in
the next section), raise an illegal instruction exception.
the next section), raise an illegal-instruction exception.
====
Note that the widths of `siselect` and `sireg*` are always the
@ -257,21 +257,21 @@ most-significant bit of `vsiselect` moves to the new position, retaining
its value from before.
For alias CSRs `sireg*` and `vsireg*`, the hypervisor extension’s usual
rules for when to raise a virtual instruction exception (based on
rules for when to raise a virtual-instruction exception (based on
whether an instruction is HS-qualified) are not applicable. The
rules given in this section for `sireg` and `vsireg` apply instead, unless
overridden by the requirements specified in the section below, which
take precedence over this section when extension Smstateen is also
implemented.
A virtual instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`.
A virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`.
The behavior upon accessing `vsireg*` from M-mode or HS-mode, or accessing `sireg*` (really `vsireg*`) from VS-mode, while `vsiselect` holds a value that is not implemented at HS level, is UNSPECIFIED.
[%unbreakable]
[NOTE]
====
It is recommended that implementations raise an illegal instruction exception for such accesses, to facilitate possible emulation (by M-mode) of these accesses.
It is recommended that implementations raise an illegal-instruction exception for such accesses, to facilitate possible emulation (by M-mode) of these accesses.
====
Otherwise, while `vsiselect` holds a number in a standard-defined and
@ -284,7 +284,7 @@ allocated.
[%unbreakable]
[NOTE]
====
Ordinarily, each `vsireg`*_i_* will access register state, access read-only 0 state, or raise an exception (either an illegal instruction exception or, for select accesses from VS-mode, a virtual instruction exception). When `vsiselect` holds a value that is implemented at HS level but not at VS level, attempts to access `sireg*` (really `vsireg*`) from VS-mode will typically raise a virtual instruction exception. But there may be cases specific to an extension where different behavior is more appropriate.
Ordinarily, each `vsireg`*_i_* will access register state, access read-only 0 state, or raise an exception (either an illegal-instruction exception or, for select accesses from VS-mode, a virtual-instruction exception). When `vsiselect` holds a value that is implemented at HS level but not at VS level, attempts to access `sireg*` (really `vsireg*`) from VS-mode will typically raise a virtual-instruction exception. But there may be cases specific to an extension where different behavior is more appropriate.
====
Like `siselect` and `sireg*`, the widths of `vsiselect` and `vsireg*` are always
@ -299,7 +299,7 @@ If extension Smstateen is implemented together with Smcsrind, bit 60 of
state-enable register `mstateen0` controls access to `siselect`, `sireg*`,
`vsiselect`, and `vsireg*`. When `mstateen0`[60]=0, an attempt to access one
of these CSRs from a privilege mode less privileged than M-mode results
in an illegal instruction exception. As always, the state-enable CSRs do
in an illegal-instruction exception. As always, the state-enable CSRs do
not affect the accessibility of any state when in M-mode, only in less
privileged modes. For more explanation, see the documentation for
extension
@ -308,7 +308,7 @@ https://github.com/riscv/riscv-state-enable/releases/download/v1.0.0/Smstateen.p
Other extensions may specify that certain mstateen bits control access
to registers accessed indirectly through `siselect` + `sireg*`, and/or
`vsiselect` + `vsireg*`. However, regardless of any other mstateen bits, if
`mstateen0`[60] = 1, a virtual instruction exception is raised as
`mstateen0`[60] = 1, a virtual-instruction exception is raised as
described in the previous section for all attempts from VS-mode or
VU-mode to directly access `vsiselect` or `vsireg*`, and for all attempts
from VU-mode to access `siselect` or `sireg*`.
@ -318,8 +318,8 @@ in hypervisor CSR `hstateen0`, but controls access to only `siselect` and `sireg
(really `vsiselect` and `vsireg*`), which is the state potentially
accessible to a virtual machine executing in VS or VU-mode. When
`hstateen0`[60]=0 and `mstateen0`[60]=1, all attempts from VS or VU-mode to
access `siselect` or `sireg*` raise a virtual instruction exception, not an
illegal instruction exception, regardless of the value of `vsiselect` or
access `siselect` or `sireg*` raise a virtual-instruction exception, not an
illegal-instruction exception, regardless of the value of `vsiselect` or
any other mstateen bit.
Extension Ssstateen is defined as the supervisor-level view of

14
src/machine.adoc
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@ -1470,7 +1470,7 @@ software interrupts. SSIP is writable in `mip` and may also be set to 1
by a platform-specific interrupt controller.
If the Sscofpmf extension is implemented, bits `mip`.LCOFIP and `mie`.LCOFIE
are the interrupt-pending and interrupt-enable bits for local counter-overflow
are the interrupt-pending and interrupt-enable bits for local-counter-overflow
interrupts.
LCOFIP is read-write in `mip` and reflects the occurrence of a local
counter-overflow overflow interrupt request resulting from any of the
@ -1942,7 +1942,7 @@ instruction).
***
Instruction address misaligned exceptions are raised by control-flow
Instruction address-misaligned exceptions are raised by control-flow
instructions with misaligned targets, rather than by the act of fetching
an instruction. Therefore, these exceptions have lower priority than
other instruction address exceptions.
@ -1950,7 +1950,7 @@ other instruction address exceptions.
[NOTE]
====
A Software Check exception is a synchronous exception that is triggered when
A software-check exception is a synchronous exception that is triggered when
there are violations of checks and assertions defined by ISA extensions that
aim to safeguard the integrity of software assets, including e.g. control-flow
and memory-access constraints. When this exception is raised, the `__x__tval`
@ -1959,14 +1959,14 @@ that stipulated the exception be raised. The priority of this exception,
relative to other synchronous exceptions, depends on the cause of this exception
and is defined by the extension that stipulated the exception be raised.
A Hardware Error exception is a synchronous exception triggered when corrupted or
A hardware-error exception is a synchronous exception triggered when corrupted or
uncorrectable data is accessed explicitly or implicitly by an instruction. In
this context, "data" encompasses all types of information used within a RISC-V
hart. Upon a hardware error exception, the `__x__epc` register is set to the
hart. Upon a hardware-error exception, the `__x__epc` register is set to the
address of the instruction that attempted to access corrupted data, while the
`__x__tval` register is set either to 0 or to the virtual address of an
instruction fetch, load, or store that attempted to access corrupted data. The
priority of Hardware Error exception is implementation-defined, but any given
priority of hardware-error exception is implementation-defined, but any given
occurrence is generally expected to be recognized at the point in the overall
priority order at which the hardware error is discovered.
====
@ -2049,7 +2049,7 @@ two cases (or alternatively, the system configuration information can be
interrogated to install the appropriate trap handling before runtime).
====
On a trap caused by a software check exception, the `mtval` register holds
On a trap caused by a software-check exception, the `mtval` register holds
the cause for the exception. The following encodings are defined:
* 0 - No information provided.

12
src/priv-cfi.adoc
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@ -124,17 +124,17 @@ This section specifies the Privileged ISA for the Zicfiss extension.
==== Shadow Stack Pointer (`ssp`) CSR access control
Attempts to access the `ssp` CSR may result in either an illegal-instruction
exception or a virtual instruction exception, contingent upon the state of the
exception or a virtual-instruction exception, contingent upon the state of the
*__x__*`envcfg.SSE` fields. The conditions are specified as follows:
* If the privilege mode is less than M and `menvcfg.SSE` is 0, an
illegal-instruction exception is raised.
* Otherwise, if in U-mode and `senvcfg.SSE` is 0, an illegal-instruction
exception is raised.
* Otherwise, if in VS-mode and `henvcfg.SSE` is 0, a virtual instruction
* Otherwise, if in VS-mode and `henvcfg.SSE` is 0, a virtual-instruction
exception is raised.
* Otherwise, if in VU-mode and either `henvcfg.SSE` or `senvcfg.SSE` is 0,
a virtual instruction exception is raised.
a virtual-instruction exception is raised.
* Otherwise, the access is allowed.
==== Shadow-Stack-Enabled (SSE) State
@ -227,7 +227,7 @@ Stores to shadow stack pages by instructions other than `SSAMOSWAP`, `SSPUSH`,
and `C.SSPUSH` will trigger a store/AMO access-fault exception, not a store/AMO
page-fault exception, signaling a fatal error. A store/AMO page-fault suggests
that the operating system could address and rectify the fault, which is not
feasible in this scenario. Hence, the page fault handler must decode the opcode
feasible in this scenario. Hence, the page-fault handler must decode the opcode
of the faulting instruction to discern whether the fault was caused by a
non-shadow-stack instruction writing to an SS page (a fatal condition) or by a
shadow stack instruction to a non-resident page (a recoverable condition). The
@ -281,7 +281,7 @@ store/AMO page-fault exception will be triggered.
====
Shadow stack loads and stores will trigger a store/AMO page-fault if the
accessed page is read-only, to support copy-on-write (COW) of a shadow stack
page. If the page has been marked read-only for COW tracking, the page fault
page. If the page has been marked read-only for COW tracking, the page-fault
handler responds by creating a copy of the page and updates the `pte.xwr` to
`010b`, thereby designating each copy as a shadow stack page. Conversely, if
the access targets a genuinely read-only page, the fault being reported as a
@ -345,7 +345,7 @@ The G-stage address translation and protections remain unaffected by the Zicfiss
extension. The `xwr == 010b` encoding in the G-stage PTE remains reserved. When
G-stage page tables are active, the shadow stack instructions that access memory
require the G-stage page table to have read-write permission for the accessed
memory; else a store/AMO guest-page fault exception is raised.
memory; else a store/AMO guest-page-fault exception is raised.
[NOTE]
====

2
src/priv-preface.adoc
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@ -178,7 +178,7 @@ implemented.
* Defined the misaligned atomicity granule PMA, superseding the proposed Zam
extension.
* Allocated interrupt 13 for Sscofpmf LCOFI interrupt.
* Defined hardware error and software check exception codes.
* Defined hardware-error and software-check exception codes.
* Specified synchronization requirements when changing the PBMTE fields
in `menvcfg` and `henvcfg`.
* Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension.

22
src/scalar-crypto.adoc
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@ -3561,7 +3561,7 @@ The 32-bit contents of `seed` are as follows:
Attempts to access the `seed` CSR using a read-only CSR-access instruction
(`CSRRS`/`CSRRC` with _rs1_=`x0` or `CSRRSI`/`CSRRCI` with _uimm_=0) raise an
illegal instruction exception; any other CSR-access instruction may be used
illegal-instruction exception; any other CSR-access instruction may be used
to access `seed`.
The write value (in `rs1` or `uimm`) must be ignored by implementations.
The purpose of the write is to signal polling and flushing.
@ -3582,7 +3582,7 @@ Encoding::
....
The `seed` CSR is also access controlled by execution mode, and attempted
read or write access will raise an illegal instruction exception outside M mode
read or write access will raise an illegal-instruction exception outside M mode
unless access is explicitly granted. See <<crypto_scalar_es_access>> for
more details.
@ -3770,15 +3770,15 @@ available to other modes via the `mseccfg.sseed` and `mseccfg.useed`
access control bits. `sseed` is bit `9` of and `useed` is
bit `8` of the `mseccfg` CSR.
Without the corresponding access control bit set to 1, any attempted
access to `seed` from U, S, or HS modes will raise an illegal instruction
access to `seed` from U, S, or HS modes will raise an illegal-instruction
exception.
VS and VU modes are present in systems with Hypervisor (H) extension
implemented. If desired, a hypervisor can emulate accesses to the seed CSR
from a virtual machine. Attempted access to `seed` from virtual modes
VS and VU always raises an exception; a read-only instruction causes an
illegal instruction exception, while a read-write instruction (that can
potentially be emulated) causes a virtual instruction exception only if
illegal-instruction exception, while a read-write instruction (that can
potentially be emulated) causes a virtual-instruction exception only if
`mseccfg.sseed=1`. Note that `mseccfg.useed` has no effect on the exception
type for either VS or VU modes.
@ -3793,12 +3793,12 @@ type for either VS or VU modes.
| `*`
| The `seed` CSR is always available in machine mode as normal (with a
CSR read-write instruction.) Attempted read without a write raises an
illegal instruction exception regardless of mode and access control bits.
illegal-instruction exception regardless of mode and access control bits.
| U
| `*`
| `0`
| Any `seed` CSR access raises an illegal instruction exception.
| Any `seed` CSR access raises an illegal-instruction exception.
| U
| `*`
@ -3808,7 +3808,7 @@ illegal instruction exception regardless of mode and access control bits.
| S/HS
| `0`
| `*`
| Any `seed` CSR access raises an illegal instruction exception.
| Any `seed` CSR access raises an illegal-instruction exception.
| S/HS
@ -3819,13 +3819,13 @@ illegal instruction exception regardless of mode and access control bits.
| VS/VU
| `0`
| `*`
| Any `seed` CSR access raises an illegal instruction exception.
| Any `seed` CSR access raises an illegal-instruction exception.
| VS/VU
| `1`
| `*`
| A read-write `seed` access raises a virtual instruction exception,
while other access conditions raise an illegal instruction exception.
| A read-write `seed` access raises a virtual-instruction exception,
while other access conditions raise an illegal-instruction exception.
|=======================================================================

16
src/smcdeleg.adoc
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@ -77,7 +77,7 @@ The remaining rules of this section apply only when access to a CSR is
not blocked by `mstateen0`[60] = 0 or `hstateen0`[60] = 0.
While the privilege mode is M or S and `siselect` holds a value in the
range 0x40-0x5F, illegal instruction exceptions are raised for the
range 0x40-0x5F, illegal-instruction exceptions are raised for the
following cases:
* attempts to access any `sireg*` when `menvcfg`.CDE = 0;
@ -95,16 +95,16 @@ For each `siselect` and `sireg*` combination defined in <<indirect-hpm-state-map
further indicates the extensions upon which the underlying counter state
depends. If any extension upon which the underlying state depends is not
implemented, an attempt from M or S mode to access the given state
through `sireg*` raises an illegal instruction exception.
through `sireg*` raises an illegal-instruction exception.
If the hypervisor (H) extension is also implemented, then as specified
by extension Smcsrind/Sscsrind, a virtual instruction exception is
by extension Smcsrind/Sscsrind, a virtual-instruction exception is
raised for attempts from VS-mode or VU-mode to directly access `vsiselect`
or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`. Furthermore, while `vsiselect` holds a value in the range 0x40-0x5F:
* An attempt to access any `vsireg*` from M or S mode raises an illegal
instruction exception.
* An attempt from VS-mode to access any `sireg*` (really `vsireg*`) raises an illegal instruction exception if `menvcfg`.CDE = 0, or a virtual
* An attempt from VS-mode to access any `sireg*` (really `vsireg*`) raises an illegal-instruction exception if `menvcfg`.CDE = 0, or a virtual
instruction exception if `menvcfg`.CDE = 1.
If Sscofpmf is implemented, `sireg2` and `sireg5` provide access only to a
@ -125,18 +125,18 @@ zero.
When `menvcfg`.CDE=0, attempts to access `scountinhibit` raise an illegal
instruction exception. When the Supervisor Counter Delegation extension
is enabled, attempts to access `scountinhibit` from VS-mode or VU-mode
raise a virtual instruction exception.
raise a virtual-instruction exception.
=== Virtualizing `scountovf`
For implementations that support Smcdeleg/Ssccfg, Sscofpmf, and the H
extension, when `menvcfg`.CDE=1, attempts to read `scountovf` from VS-mode
or VU-mode raise a virtual instruction exception.
or VU-mode raise a virtual-instruction exception.
=== Virtualizing Local Counter Overflow Interrupts
=== Virtualizing Local-Counter-Overflow Interrupts
For implementations that support Smcdeleg, Sscofpmf, and Smaia, the
local counter overflow interrupt (LCOFI) bit (bit 13) in each of CSRs
local-counter-overflow interrupt (LCOFI) bit (bit 13) in each of CSRs
`mvip` and `mvien` is implemented and writable.
For implementations that support Smcdeleg/Ssccfg, Sscofpmf,

2
src/smcntrpmf.adoc
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@ -47,7 +47,7 @@ The content of these registers may be accessible from Supervisor level if the Sm
====
The more natural CSR number for mcyclecfg would be 0x320, but that was allocated to mcountinhibit.
This register format matches that specified for programmable counters by Sscofpmf. The bit position for the OF bit (bit 63) is read-only 0, since these counters do not generate local counter overflow interrupts on overflow.
This register format matches that specified for programmable counters by Sscofpmf. The bit position for the OF bit (bit 63) is read-only 0, since these counters do not generate local-counter-overflow interrupts on overflow.
====
=== Counter Behavior

10
src/smctr.adoc
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@ -74,7 +74,7 @@ The `mctrctl` register is a 64-bit read/write register that enables and configur
|BPFRZ |Set `sctrstatus`.FROZEN on a breakpoint exception that traps to M-mode or S-mode. See <<Freeze>>.
|LCOFIFRZ |Set `sctrstatus`.FROZEN on local counter overflow interrupt (LCOFI) that traps to M-mode or S-mode. See <<Freeze>>.
|LCOFIFRZ |Set `sctrstatus`.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to M-mode or S-mode. See <<Freeze>>.
|EXCINH |Inhibit recording of exceptions. See <<Transfer Type Filtering>>.
@ -166,7 +166,7 @@ If the H extension is implemented, the `vsctrctl` register is a 64-bit read/writ
|U |Enable transfer recording in VU-mode.
|STE |Enables recording of traps to VS-mode when S=0. See <<External Traps>>.
|BPFRZ |Set `sctrstatus`.FROZEN on a breakpoint exception that traps to VS-mode. See <<Freeze>>.
|LCOFIFRZ |Set `sctrstatus`.FROZEN on local counter overflow interrupt (LCOFI) that traps to VS-mode. See <<Freeze>>.
|LCOFIFRZ |Set `sctrstatus`.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to VS-mode. See <<Freeze>>.
2+|Other field definitions match those of `sctrctl`. The optional fields implemented in `vsctrctl` should match those implemented in `sctrctl`.
|===
@ -724,19 +724,19 @@ an implementation may opt to record CCV=0 for all calls, or those whose parent c
When `sctrstatus`.FROZEN=1, transfer recording is inhibited. This bit can be set by hardware, as described below, or by software.
When `sctrctl`.LCOFIFRZ=1 and a local counter overflow interrupt
When `sctrctl`.LCOFIFRZ=1 and a local-counter-overflow interrupt
(LCOFI) traps (as a result of an HPM counter overflow) to M-mode or to S-mode, `sctrstatus`.FROZEN is set by hardware. This inhibits CTR recording until software clears FROZEN. The LCOFI trap itself is not recorded.
[NOTE]
[%unbreakable]
====
_Freeze on LCOFI ensures that the execution path leading to the sampled
instruction (`__x__epc`) is preserved, and that the local counter overflow
instruction (`__x__epc`) is preserved, and that the local-counter-overflow
interrupt (LCOFI) and associated Interrupt Service Routine (ISR) do not
displace any recorded transfer history state. It is the responsibility
of the ISR to clear FROZEN before __x__RET, if continued control transfer
recording is desired._
_LCOFI refers only to architectural traps directly caused by a local counter overflow. If a local counter overflow interrupt is recognized without a trap, FROZEN is not automatically set. For instance, no freeze occurs if the LCOFI is pended while interrupts are masked, and software recognizes the LCOFI (perhaps by reading `stopi` or `sip`) and clears `sip`.LCOFIP before the trap is raised. As a result, some or all CTR history may be overwritten while handling the LCOFI. Such cases are expected to be very rare; for most usages (e.g., application profiling) privilege mode filtering is sufficient to ensure that CTR updates are inhibited while interrupts are handled in a more privileged mode._
_LCOFI refers only to architectural traps directly caused by a local counter overflow. If a local-counter-overflow interrupt is recognized without a trap, FROZEN is not automatically set. For instance, no freeze occurs if the LCOFI is pended while interrupts are masked, and software recognizes the LCOFI (perhaps by reading `stopi` or `sip`) and clears `sip`.LCOFIP before the trap is raised. As a result, some or all CTR history may be overwritten while handling the LCOFI. Such cases are expected to be very rare; for most usages (e.g., application profiling) privilege mode filtering is sufficient to ensure that CTR updates are inhibited while interrupts are handled in a more privileged mode._
====
Similarly, on a breakpoint exception that traps to M-mode or S-mode with `sctrctl`.BPFRZ=1, FROZEN is set by hardware. The breakpoint exception itself is not recorded.

12
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@ -87,16 +87,16 @@ as with the `counteren` CSRs, when a `stateen` CSR prevents access to state by
less-privileged levels, an attempt in one of those privilege modes to execute
an instruction that would read or write the protected state raises an illegal
instruction exception, or, if executing in VS or VU mode and the circumstances
for a virtual instruction exception apply, raises a virtual instruction
exception instead of an illegal instruction exception.
for a virtual-instruction exception apply, raises a virtual-instruction
exception instead of an illegal-instruction exception.
When this extension is not implemented, all state added by an extension is
accessible as defined by that extension.
When a `stateen` CSR prevents access to state for a privilege mode, attempting to
execute in that privilege mode an instruction that _implicitly_ updates the
state without reading it may or may not raise an illegal instruction or virtual
instruction exception. Such cases must be disambiguated by being explicitly
state without reading it may or may not raise an illegal-instruction or virtual-instruction
exception. Such cases must be disambiguated by being explicitly
specified one way or the other.
In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables
@ -247,8 +247,8 @@ the Zfinx and related extensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit
of `mstateen0` is read-only zero (and hence read-only zero in `hstateen0` and
`sstateen0` too). For convenience, when the `stateen` CSRs are implemented and
`misa.F` = 0, then if the FCSR bit of a controlling `stateen0` CSR is zero, all
floating-point instructions cause an illegal instruction trap (or virtual
instruction trap, if relevant), as though they all access `fcsr`, regardless of
floating-point instructions cause an illegal-instruction exception (or virtual-instruction
exception, if relevant), as though they all access `fcsr`, regardless of
whether they really do.
The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension.

10
src/sstc.adoc
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@ -84,7 +84,7 @@ This extension modifies the description of the STIP/STIE bits in these
registers as follows:
Bits `sip`.STIP and `sie`.STIE are the interrupt-pending and interrupt-enable bits
for supervisor level timer interrupts. If implemented, STIP is read-only in
for supervisor-level timer interrupts. If implemented, STIP is read-only in
sip, and is either set and cleared by the execution environment (if `stimecmp` is
not implemented), or reflects the timer interrupt signal resulting from
`stimecmp` (if `stimecmp` is implemented). The `sip`.STIP bit, in response to timer
@ -99,7 +99,7 @@ follows:
In addition, when the TM bit in the mcounteren register is clear, attempts to
access the `stimecmp` or `vstimecmp` register while executing in a mode less
privileged than M will cause an illegal instruction exception. When this bit
privileged than M will cause an illegal-instruction exception. When this bit
is set, access to the `stimecmp` or `vstimecmp` register is permitted in S-mode if
implemented, and access to the `vstimecmp` register (via `stimecmp`) is permitted
in VS-mode if implemented and not otherwise prevented by the TM bit in
@ -162,7 +162,7 @@ follows:
In addition, when the TM bit in the `hcounteren` register is clear, attempts to
access the `vstimecmp` register (via stimecmp) while executing in VS-mode will
cause a virtual instruction exception if the same bit in `mcounteren` is set.
cause a virtual-instruction exception if the same bit in `mcounteren` is set.
When this bit and the same bit in `mcounteren` are both set, access to the
`vstimecmp` register (if implemented) is permitted in VS-mode.
@ -177,11 +177,11 @@ enables `vstimecmp` for VS-mode. These STCE bits are WARL and are hard-wired to
when this extension is not implemented.
When this extension is implemented and STCE in `menvcfg` is zero, an attempt to access `stimecmp` or `vstimecmp` in a
mode other than M-mode raises an illegal instruction exception, STCE in `henvcfg`
mode other than M-mode raises an illegal-instruction exception, STCE in `henvcfg`
is read-only zero, and STIP in `mip` and `sip` reverts to its defined behavior as
if this extension is not implemented. Further, if the H extension is implemented, then hip.VSTIP also reverts its defined behavior as if this extension is not implemented.
But when STCE in `menvcfg` is one and STCE in `henvcfg` is zero, an attempt to access
`stimecmp` (really `vstimecmp`) when V = 1 raises a virtual instruction exception,
`stimecmp` (really `vstimecmp`) when V = 1 raises a virtual-instruction exception,
and VSTIP in hip reverts to its defined behavior as if this extension is not
implemented.

12
src/supervisor.adoc
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@ -276,10 +276,10 @@ trap that may occur during the tail phase, where it restores critical state
to return from a trap.
The consequence of this specification is that if a critical error condition was
caused by a guest page-fault, then the GPA will not be available in `mtval2`
caused by a guest-page fault, then the GPA will not be available in `mtval2`
when the double trap is delivered to M-mode. This condition arises if the
HS-mode invokes a hypervisor virtual-machine load or store instruction when
`SDT` is 1 and the instruction raises a guest page-fault. The use of such an
`SDT` is 1 and the instruction raises a guest-page fault. The use of such an
instruction in this phase of trap handling is not common. However, not recording
the GPA is considered benign because, if required, it can still be obtained
-- albeit with added effort -- through the process of walking the page tables.
@ -412,7 +412,7 @@ implemented, SSIP is writable in `sip` and may also be set to 1 by a
platform-specific interrupt controller.
If the Sscofpmf extension is implemented, bits `sip`.LCOFIP and `sie`.LCOFIE
are the interrupt-pending and interrupt-enable bits for local counter-overflow
are the interrupt-pending and interrupt-enable bits for local-counter-overflow
interrupts.
LCOFIP is read-write in `sip` and reflects the occurrence of a local
counter-overflow overflow interrupt request resulting from any of the
@ -697,7 +697,7 @@ will contain the shortest of:
The value loaded into `stval` on an illegal-instruction exception is
right-justified and all unused upper bits are cleared to zero.
On a trap caused by a software check exception, the `stval` register holds the
On a trap caused by a software-check exception, the `stval` register holds the
cause for the exception. The following encodings are defined:
* 0 - No information provided.
@ -844,7 +844,7 @@ rules apply:
* 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop.
* 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop.
* When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises an illegal-instruction
exception in U-mode and a virtual instruction exception in VU-mode.
exception in U-mode and a virtual-instruction exception in VU-mode.
[[satp]]
==== Supervisor Address Translation and Protection (`satp`) Register
@ -2209,7 +2209,7 @@ or HS-mode when `mstatus`.TVM=1 also raises an illegal-instruction
exception. An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode
or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a
virtual-instruction exception. When `hstatus`.VTVM=1, an attempt to execute
SINVAL.VMA in VS-mode also raises a virtual instruction exception.
SINVAL.VMA in VS-mode also raises a virtual-instruction exception.
Attempting to execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U-mode
raises an illegal-instruction exception.

8
src/unpriv-cfi.adoc
View File

@ -778,9 +778,9 @@ data values.
else if privilege_mode == U && senvcfg.SSE == 0
raise illegal-instruction exception
else if privilege_mode == VS && henvcfg.SSE == 0
raise virtual instruction exception
raise virtual-instruction exception
else if privilege_mode == VU && senvcfg.SSE == 0
raise virtual instruction exception
raise virtual-instruction exception
else
X(rd) = mem[X(rs1)]
mem[X(rs1)] = X(rs2)
@ -802,9 +802,9 @@ address in `rs1`.
else if privilege_mode == U && senvcfg.SSE == 0
raise illegal-instruction exception
else if privilege_mode == VS && henvcfg.SSE == 0
raise virtual instruction exception
raise virtual-instruction exception
else if privilege_mode == VU && senvcfg.SSE == 0
raise virtual instruction exception
raise virtual-instruction exception
else
temp[31:0] = mem[X(rs1)]
X(rd) = SignExtend(temp[31:0])

28
src/v-st-ext.adoc
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@ -545,7 +545,7 @@ instruction exception as defined below.
NOTE: Making `vstart` visible to unprivileged code supports user-level
threading libraries.
Implementations are permitted to raise illegal instruction exceptions when
Implementations are permitted to raise illegal-instruction exceptions when
attempting to execute a vector instruction with a value of `vstart` that the
implementation can never produce when executing that same instruction with
the same `vtype` setting.
@ -553,7 +553,7 @@ the same `vtype` setting.
NOTE: For example, some implementations will never take interrupts during
execution of a vector arithmetic instruction, instead waiting until the
instruction completes to take the interrupt. Such implementations are
permitted to raise an illegal instruction exception when attempting to execute
permitted to raise an illegal-instruction exception when attempting to execute
a vector arithmetic instruction when `vstart` is nonzero.
NOTE: When migrating a software thread between two harts with
@ -1410,7 +1410,7 @@ If the vector offset elements are narrower than XLEN, they are
zero-extended to XLEN before adding to the base effective address. If
the vector offset elements are wider than XLEN, the least-significant
XLEN bits are used in the address calculation. An implementation must
raise an illegal instruction exception if the EEW is not supported for
raise an illegal-instruction exception if the EEW is not supported for
offset elements.
NOTE: A profile may place an upper limit on the maximum supported index
@ -2099,7 +2099,7 @@ vs4r.v v4, (a1) # Store v4-v7 to address in a1
vs8r.v v8, (a1) # Store v8-v15 to address in a1
----
NOTE: Implementations should raise illegal instruction exceptions on
NOTE: Implementations should raise illegal-instruction exceptions on
`vl<nf>r` instructions for EEW values that are not supported.
NOTE: We have considered adding a whole register mask load instruction
@ -2123,7 +2123,7 @@ vsetvli x0, t0, <new type> # Restore vl (potentially already present)
If an element accessed by a vector memory instruction is not naturally
aligned to the size of the element, either the element is transferred
successfully or an address misaligned exception is raised on that
successfully or an address-misaligned exception is raised on that
element.
Support for misaligned vector memory accesses is independent of an
@ -3251,7 +3251,7 @@ half-precision floating-point support.
If the floating-point unit status field `mstatus.FS` is `Off` then any
attempt to execute a vector floating-point instruction will raise an
illegal instruction exception. Any vector floating-point instruction
illegal-instruction exception. Any vector floating-point instruction
that modifies any floating-point extension state (i.e., floating-point
CSRs or `f` registers) must set `mstatus.FS` to `Dirty`.
@ -3259,7 +3259,7 @@ If the hypervisor extension is implemented and V=1, the `vsstatus.FS` field is
additionally in effect for vector floating-point instructions. If
`vsstatus.FS` or `mstatus.FS` is `Off` then any
attempt to execute a vector floating-point instruction will raise an
illegal instruction exception. Any vector floating-point instruction
illegal-instruction exception. Any vector floating-point instruction
that modifies any floating-point extension state (i.e., floating-point
CSRs or `f` registers) must set both `mstatus.FS` and `vsstatus.FS` to `Dirty`.
@ -4161,7 +4161,7 @@ The `vcpop.m` instruction writes `x[rd]` even if `vl`=0 (with the
value 0, since no mask elements are active).
Traps on `vcpop.m` are always reported with a `vstart` of 0. The
`vcpop.m` instruction will raise an illegal instruction exception if
`vcpop.m` instruction will raise an illegal-instruction exception if
`vstart` is non-zero.
==== `vfirst` find-first-set mask bit
@ -4183,7 +4183,7 @@ The `vfirst.m` instruction writes `x[rd]` even if `vl`=0 (with the
value -1, since no mask elements are active).
Traps on `vfirst` are always reported with a `vstart` of 0. The
`vfirst` instruction will raise an illegal instruction exception if
`vfirst` instruction will raise an illegal-instruction exception if
`vstart` is non-zero.
==== `vmsbf.m` set-before-first mask bit
@ -4224,7 +4224,7 @@ The tail elements in the destination mask register are updated under a
tail-agnostic policy.
Traps on `vmsbf.m` are always reported with a `vstart` of 0. The
`vmsbf` instruction will raise an illegal instruction exception if
`vmsbf` instruction will raise an illegal-instruction exception if
`vstart` is non-zero.
The destination register cannot overlap the source register
@ -4260,7 +4260,7 @@ The tail elements in the destination mask register are updated under a
tail-agnostic policy.
Traps on `vmsif.m` are always reported with a `vstart` of 0. The
`vmsif` instruction will raise an illegal instruction exception if
`vmsif` instruction will raise an illegal-instruction exception if
`vstart` is non-zero.
The destination register cannot overlap the source register
@ -4297,7 +4297,7 @@ The tail elements in the destination mask register are updated under a
tail-agnostic policy.
Traps on `vmsof.m` are always reported with a `vstart` of 0. The
`vmsof` instruction will raise an illegal instruction exception if
`vmsof` instruction will raise an illegal-instruction exception if
`vstart` is non-zero.
The destination register cannot overlap the source register
@ -4349,7 +4349,7 @@ destination SEW, the least-significant SEW bits are retained.
Traps on `viota.m` are always reported with a `vstart` of 0, and
execution is always restarted from the beginning when resuming after a
trap handler. An illegal instruction exception is raised if `vstart`
trap handler. An illegal-instruction exception is raised if `vstart`
is non-zero.
The destination register group cannot overlap the source register
@ -4763,7 +4763,7 @@ encoding is reserved.
A trap on a `vcompress` instruction is always reported with a
`vstart` of 0. Executing a `vcompress` instruction with a non-zero
`vstart` raises an illegal instruction exception.
`vstart` raises an illegal-instruction exception.
NOTE: Although possible, `vcompress` is one of the more difficult
instructions to restart with a non-zero `vstart`, so assumption is

36
src/vector-crypto.adoc
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@ -236,10 +236,10 @@ Likewise the starting element group is `vstart`/`EGS`.
See <<crypto-vector-instruction-constraints>> for limitations on `vl` and `vstart`
for vector crypto instructions.
// If this ratio is not an integer for a vector crypto instruction, an illegal instruction exception is raised.
// If this ratio is not an integer for a vector crypto instruction, an illegal-instruction exception is raised.
// Since `vstart` is expressed in elements, the starting element group is `vstart`/`EGS`.
// If this ratio is not an integer for a vector crypto instruction, an illegal instruction exception is raised.
// If this ratio is not an integer for a vector crypto instruction, an illegal-instruction exception is raised.
[[crypto-vector-instruction-constraints]]
==== Instruction Constraints
@ -273,7 +273,7 @@ Element Group Size (`EGS`).
LMUL constraints::
For element-group instructions, `LMUL`*`VLEN` must always be at least as large as `EGW`, otherwise an
_illegal instruction exception_ is raised, even if `vl`=0.
_illegal-instruction exception_ is raised, even if `vl`=0.
[%autowidth]
[%header,cols="4,2,2"]
@ -1261,7 +1261,7 @@ Operation::
--
function clause execute (VAESDF(vs2, vd, suffix)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -1366,7 +1366,7 @@ Operation::
--
function clause execute (VAESDM(vs2, vd, suffix)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -1472,7 +1472,7 @@ Operation::
--
function clause execute (VAESEF(vs2, vd, suffix) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -1577,7 +1577,7 @@ Operation::
--
function clause execute (VAESEM(vs2, vd, suffix)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -1688,7 +1688,7 @@ Operation::
--
function clause execute (VAESKF1(rnd, vd, vs2)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -1800,7 +1800,7 @@ Operation::
--
function clause execute (VAESKF2(rnd, vd, vs2)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -1908,7 +1908,7 @@ Operation::
--
function clause execute (VAESZ(vs2, vd) = {
if(((vstart%EGS)<>0) | (LMUL*VLEN < EGW)) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -2641,7 +2641,7 @@ Operation::
function clause execute (VGHSH(vs2, vs1, vd)) = {
// operands are input with bits reversed in each byte
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -2772,7 +2772,7 @@ Operation::
function clause execute (VGMUL(vs2, vs1, vd)) = {
// operands are input with bits reversed in each byte
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -3267,7 +3267,7 @@ Operation::
--
function clause execute (VSHA2c(vs2, vs1, vd)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -3474,7 +3474,7 @@ function clause execute (VSHA2ms(vs2, vs1, vd)) = {
// SEW32 = SHA-256
// SEW64 = SHA-512
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -3623,7 +3623,7 @@ Operation::
--
function clause execute (VSM3C(rnds, vs2, vd)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -3798,7 +3798,7 @@ Operation::
--
function clause execute (VSM3ME(vs2, vs1)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -4018,7 +4018,7 @@ Operation::
function clause execute (vsm4k(uimm, vs2)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {
@ -4177,7 +4177,7 @@ Operation::
--
function clause execute (VSM4R(vd, vs2)) = {
if(LMUL*VLEN < EGW) then {
handle_illegal(); // illegal instruction exception
handle_illegal(); // illegal-instruction exception
RETIRE_FAIL
} else {

6
src/zawrs.adoc
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@ -76,12 +76,12 @@ for resuming execution on a pending interrupt.
When the `TW` (Timeout Wait) bit in `mstatus` is set and `WRS.NTO` is executed
in any privilege mode other than M mode, and it does not complete within an
implementation-specific bounded time limit, the `WRS.NTO` instruction will cause
an illegal instruction exception.
an illegal-instruction exception.
When executing in VS or VU mode, if the `VTW` bit is set in `hstatus`, the
`TW` bit in `mstatus` is clear, and the `WRS.NTO` does not complete within an
implementation-specific bounded time limit, the `WRS.NTO` instruction will cause
a virtual instruction exception.
a virtual-instruction exception.
[NOTE]
====
@ -97,7 +97,7 @@ cacheless access to main memory.
`WRS.NTO`, unlike `WFI`, is not specified to cause an illegal instruction
exception if executed in U-mode when the governing `TW` bit is 0. `WFI` is
typically not expected to be used in U-mode and on many systems may promptly
cause an illegal instruction exception if used at U-mode. Unlike `WFI`,
cause an illegal-instruction exception if used at U-mode. Unlike `WFI`,
`WRS.NTO` is expected to be used by software in U-mode when waiting on
memory but without a deadline for that wait.
====

4
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@ -1290,7 +1290,7 @@ ret
An implementation may have a requirement to issue a PUSH/POP instruction to non-idempotent memory.
If the core implementation does not support PUSH/POP to non-idempotent memories, the core may use an idempotency PMA to detect it and take a
load (POP/POPRET) or store (PUSH) access fault exception in order to avoid unpredictable results.
load (POP/POPRET) or store (PUSH) access-fault exception in order to avoid unpredictable results.
Software should only use these instructions on non-idempotent memory regions when software can tolerate the required memory accesses
being issued repeatedly in the case that they cause exceptions.
@ -2428,7 +2428,7 @@ _jvt_ CSR adds architectural state to the system software context (such as an OS
State Enable:
If the Smstateen extension is implemented, then bit 2 in _mstateen0_, _sstateen0_, and _hstateen0_ is implemented. If bit 2 of a controlling _stateen0_ CSR is zero, then access to the _jvt_ CSR and execution of a _cm.jalt_ or _cm.jt_ instruction by a lower privilege level results in an Illegal Instruction trap (or, if appropriate, a Virtual Instruction trap).
If the Smstateen extension is implemented, then bit 2 in _mstateen0_, _sstateen0_, and _hstateen0_ is implemented. If bit 2 of a controlling _stateen0_ CSR is zero, then access to the _jvt_ CSR and execution of a _cm.jalt_ or _cm.jt_ instruction by a lower privilege level results in an illegal-instruction trap (or, if appropriate, a virtual-instruction trap).
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[#insns-cm_jt,reftext="Jump via table"]