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Add note about tvec/jvt register layout/alignment (#1988)

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Supersedes #1987
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Andrew Waterman 2025-04-25 15:58:54 -07:00 committed by GitHub
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3
src/machine.adoc
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@ -1185,6 +1185,9 @@ read-only value. If `mtvec` is writable, the set of values the register
may hold can vary by implementation. The value in the BASE field must
always be aligned on a 4-byte boundary, and the MODE setting may impose
additional alignment constraints on the value in the BASE field.
Note that the CSR contains only bits XLEN-1 through 2 of the address BASE.
When used as an address, the lower two bits are filled with zeroes to obtain
an XLEN-bit address that is always aligned on a 4-byte boundary.
[NOTE]
====

3
src/supervisor.adoc
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@ -311,6 +311,9 @@ physical address, subject to the following alignment constraints: the
address must be 4-byte aligned, and MODE settings other than Direct
might impose additional alignment constraints on the value in the BASE
field.
Note that the CSR contains only bits XLEN-1 through 2 of the address BASE.
When used as an address, the lower two bits are filled with zeroes to obtain
an XLEN-bit address that is always aligned on a 4-byte boundary.
[[stvec-mode]]
.Encoding of `stvec` MODE field.

1
src/zc.adoc
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@ -2399,6 +2399,7 @@ Description:
The _jvt_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).
If <<Zcmt>> is implemented then _jvt_ must also be implemented, but can contain a read-only value. If _jvt_ is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary.
Note that the CSR contains only bits XLEN-1 through 6 of the address _base_. When computing jump-table accesses, the lower six bits of _base_ are filled with zeroes to obtain an XLEN-bit jump-table base address _jvt.base_ that is always aligned on a 64-byte boundary.
_jvt.base_ is a virtual address, whenever virtual memory is enabled.