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Fix SPARC_SWTRAP_IRQDIS typo

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close #3493.
This commit is contained in:
Joel Sherrill 2018-08-09 08:42:28 -05:00
parent 806806cdcf
commit 135b90cb1b
1 changed files with 1 additions and 1 deletions
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cpu-supplement/sparc.rst
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@ -641,7 +641,7 @@ as non-maskable interrupts.
Interrupts are disabled or enabled by performing a system call to the Operating
System reserved software traps 9 (SPARC_SWTRAP_IRQDIS) or 10
(SPARC_SWTRAP_IRQDIS). The trap is generated by the software trap (Ticc)
(SPARC_SWTRAP_IRQEN). The trap is generated by the software trap (Ticc)
instruction or indirectly by calling sparc_disable_interrupts() or
sparc_enable_interrupts() functions. Disabling interrupts return the previous
interrupt level (on trap entry) in register G1 and sets PSR.PIL to 15 to