cpu-supplement: Fix header levels.

2025-06-06 17:52:59 +08:00 · 2016-11-09 12:39:16 +11:00 · 2016-11-09 12:39:16 +11:00 · 6916004896
commit 6916004896
parent cc1d3facbe
21 changed files with 24 additions and 23 deletions
--- a/cpu-supplement/altera_nios_ii.rst
+++ b/cpu-supplement/altera_nios_ii.rst
@ -4,7 +4,7 @@
 .. COMMENT: All rights reserved.

 Altera Nios II Specific Information
-###################################
+***********************************

 Symmetric Multiprocessing
 =========================
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 ARM Specific Information
-########################
+************************

 This chapter discusses the *ARM architecture*
 (http://en.wikipedia.org/wiki/ARM_architecture) dependencies in this port of
--- a/cpu-supplement/atmel_avr.rst
+++ b/cpu-supplement/atmel_avr.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 Atmel AVR Specific Information
-##############################
+******************************

 This chapter discusses the AVR architecture dependencies in this port of RTEMS.

--- a/cpu-supplement/blackfin.rst
+++ b/cpu-supplement/blackfin.rst
@ -4,7 +4,7 @@
 .. COMMENT: Hesham ALMatary <hmka501@york.ac.uk>

 Blackfin Specific Information
-#############################
+*****************************

 This chapter discusses the Blackfin architecture dependencies in this port of
 RTEMS.
--- a/cpu-supplement/command.rst
+++ b/cpu-supplement/command.rst
@ -1,9 +1,8 @@
 .. comment SPDX-License-Identifier: CC-BY-SA-4.0

 Command and Variable Index
-##########################
+**************************

 There are currently no Command and Variable Index entries.

 .. COMMENT: @printindex fn
-
--- a/cpu-supplement/conf.py
+++ b/cpu-supplement/conf.py
@ -4,7 +4,7 @@ sys.path.append(os.path.abspath('../common/'))
 from conf import *

 version = '1.0'
-release = '5.0'
+release = '4.11.0'

 latex_documents = [
 	('index', 'cpu-supplement.tex', u'RTEMS CPU Supplement Documentation', u'RTEMS Documentation Project', 'manual'),
--- a/cpu-supplement/ephiphany.rst
+++ b/cpu-supplement/ephiphany.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 Epiphany Specific Information
-#############################
+*****************************

 This chapter discusses the`Epiphany Architecture
 http://adapteva.com/docs/epiphany_sdk_ref.pdf dependencies in this port of
--- a/cpu-supplement/index.rst
+++ b/cpu-supplement/index.rst
@ -4,6 +4,9 @@
 RTEMS CPU Architecture Supplement
 =================================

+RTEMS CPU Architecture Supplement
+---------------------------------
+
 | COPYRIGHT (c) 1988 - 2015.
 | On-Line Applications Research Corporation (OAR).

@ -32,7 +35,7 @@ to the Community Project hosted at http://www.rtems.org/.
  ================  =============================

 .. toctree::
-	:maxdepth: 3
+	:maxdepth: 5
 	:numbered:

 	preface
--- a/cpu-supplement/intel_amd_x86.rst
+++ b/cpu-supplement/intel_amd_x86.rst
@ -7,7 +7,7 @@
 .. COMMENT: Micro-Research Finland Oy

 Intel/AMD x86 Specific Information
-##################################
+**********************************

 This chapter discusses the Intel x86 architecture dependencies in this port of
 RTEMS.  This family has multiple implementations from multiple vendors and
--- a/cpu-supplement/lattice_micro32.rst
+++ b/cpu-supplement/lattice_micro32.rst
@ -3,7 +3,7 @@
 .. COMMENT: Copyright (c) 2014 embedded brains GmbH.  All rights reserved.

 Lattice Mico32 Specific Information
-###################################
+***********************************

 This chaper discusses the Lattice Mico32 architecture dependencies in this port
 of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC architecture "soft"
--- a/cpu-supplement/m68xxx_and_coldfire.rst
+++ b/cpu-supplement/m68xxx_and_coldfire.rst
@ -3,7 +3,7 @@
 .. COMMENT: Copyright (c) 2014 embedded brains GmbH.  All rights reserved.

 M68xxx and Coldfire Specific Information
-########################################
+****************************************

 This chapter discusses the Freescale (formerly Motorola) MC68xxx and Coldfire
 architectural dependencies.  The MC68xxx family has a wide variety of CPU
--- a/cpu-supplement/mips.rst
+++ b/cpu-supplement/mips.rst
@ -3,7 +3,7 @@
 .. COMMENT: Copyright (c) 2014 embedded brains GmbH.  All rights reserved.

 MIPS Specific Information
-#########################
+*************************

 This chapter discusses the MIPS architecture dependencies in this port of
 RTEMS.  The MIPS family has a wide variety of implementations by a wide range
--- a/cpu-supplement/openrisc_1000.rst
+++ b/cpu-supplement/openrisc_1000.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 OpenRISC 1000 Specific Information
-##################################
+**********************************

 This chapter discusses the`OpenRISC 1000 architecture
 http://opencores.org/or1k/Main_Page dependencies in this port of RTEMS. There
--- a/cpu-supplement/port.rst
+++ b/cpu-supplement/port.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 Port Specific Information
-#########################
+*************************

 This chaper provides a general description of the type of architecture specific
 information which is in each of the architecture specific chapters that follow.
--- a/cpu-supplement/powerpc.rst
+++ b/cpu-supplement/powerpc.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 PowerPC Specific Information
-############################
+****************************

 This chapter discusses the PowerPC architecture dependencies in this port of
 RTEMS.  The PowerPC family has a wide variety of implementations by a range of
--- a/cpu-supplement/preface.rst
+++ b/cpu-supplement/preface.rst
@ -4,9 +4,8 @@
 .. COMMENT: On-Line Applications Research Corporation (OAR).
 .. COMMENT: All rights reserved.

-=======
 Preface
-=======
+*******

 The Real Time Executive for Multiprocessor Systems (RTEMS) is designed to be
 portable across multiple processor architectures.  However, the nature of
--- a/cpu-supplement/renesas_m32c.rst
+++ b/cpu-supplement/renesas_m32c.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 Renesas M32C Specific Information
-#################################
+*********************************

 Symmetric Multiprocessing
 =========================
--- a/cpu-supplement/sparc.rst
+++ b/cpu-supplement/sparc.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 SPARC Specific Information
-##########################
+**************************

 The Real Time Executive for Multiprocessor Systems (RTEMS) is designed to be
 portable across multiple processor architectures.  However, the nature of
--- a/cpu-supplement/sparc64.rst
+++ b/cpu-supplement/sparc64.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 SPARC-64 Specific Information
-#############################
+*****************************

 This document discusses the SPARC Version 9 (aka SPARC-64, SPARC64 or SPARC V9)
 architecture dependencies in this port of RTEMS.
--- a/cpu-supplement/superh.rst
+++ b/cpu-supplement/superh.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 SuperH Specific Information
-###########################
+***************************

 This chapter discusses the SuperH architecture dependencies in this port of
 RTEMS.  The SuperH family has a wide variety of implementations by a wide range
--- a/cpu-supplement/xilinx_microblaze.rst
+++ b/cpu-supplement/xilinx_microblaze.rst
@ -5,7 +5,7 @@
 .. COMMENT: All rights reserved.

 Xilinx MicroBlaze Specific Information
-######################################
+**************************************

 Symmetric Multiprocessing
 =========================