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@ -285,11 +285,11 @@ Special Registers
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~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~
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The SPARC architecture includes two special registers which are critical to the
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The SPARC architecture includes two special registers which are critical to the
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programming model: the Processor State Register (psr) and the Window Invalid
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programming model: the Processor State Register (``PSR``) and the Window Invalid
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Mask (wim). The psr contains the condition codes, processor interrupt level,
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Mask (``WIM``). The ``PSR`` contains the condition codes, processor interrupt level,
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trap enable bit, supervisor mode and previous supervisor mode bits, version
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trap enable bit, supervisor mode and previous supervisor mode bits, version
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information, floating point unit and coprocessor enable bits, and the current
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information, floating point unit and coprocessor enable bits, and the current
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window pointer (cwp). The cwp field of the psr and wim register are used to
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window pointer (``CWP``). The ``CWP`` field of the ``PSR`` and ``WIM`` register are used to
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manage the register windows in the SPARC architecture. The register windows
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manage the register windows in the SPARC architecture. The register windows
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are discussed in more detail below.
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are discussed in more detail below.
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@ -330,15 +330,15 @@ underflow condition must be handled in software by a trap handler. The window
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underflow trap handler is responsible for reloading the contents of the
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underflow trap handler is responsible for reloading the contents of the
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register window requested by the restore instruction from the program stack.
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register window requested by the restore instruction from the program stack.
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The Window Invalid Mask (wim) and the Current Window Pointer (cwp) field in the
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The Window Invalid Mask (``WIM``) and the Current Window Pointer (``CWP``) field in the
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psr are used in conjunction to manage the finite set of register windows and
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``PSR`` are used in conjunction to manage the finite set of register windows and
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detect the window overflow and underflow conditions. The cwp contains the
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detect the window overflow and underflow conditions. The ``CWP`` contains the
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index of the register window currently in use. The save instruction decrements
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index of the register window currently in use. The save instruction decrements
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the cwp modulo the number of register windows. Similarly, the restore
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the ``CWP`` modulo the number of register windows. Similarly, the restore
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instruction increments the cwp modulo the number of register windows. Each bit
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instruction increments the ``CWP`` modulo the number of register windows. Each bit
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in the wim represents represents whether a register window contains valid
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in the ``WIM`` represents represents whether a register window contains valid
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information. The value of 0 indicates the register window is valid and 1
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information. The value of 0 indicates the register window is valid and 1
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indicates it is invalid. When a save instruction causes the cwp to point to a
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indicates it is invalid. When a save instruction causes the ``CWP`` to point to a
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register window which is marked as invalid, a window overflow condition
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register window which is marked as invalid, a window overflow condition
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results. Conversely, the restore instruction may result in a window underflow
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results. Conversely, the restore instruction may result in a window underflow
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condition.
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condition.
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@ -346,8 +346,8 @@ condition.
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Other than the assumption that a register window is always available for trap
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Other than the assumption that a register window is always available for trap
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(i.e. interrupt) handlers, the SPARC architecture places no limits on the
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(i.e. interrupt) handlers, the SPARC architecture places no limits on the
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number of register windows simultaneously marked as invalid (i.e. number of
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number of register windows simultaneously marked as invalid (i.e. number of
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bits set in the wim). However, RTEMS assumes that only one register window is
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bits set in the ``WIM``). However, RTEMS assumes that only one register window is
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marked invalid at a time (i.e. only one bit set in the wim). This makes the
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marked invalid at a time (i.e. only one bit set in the ``WIM``). This makes the
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maximum possible number of register windows available to the user while still
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maximum possible number of register windows available to the user while still
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meeting the requirement that window overflow and underflow conditions can be
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meeting the requirement that window overflow and underflow conditions can be
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detected.
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detected.
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@ -356,7 +356,7 @@ The window overflow and window underflow trap handlers are a critical part of
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the run-time environment for a SPARC application. The SPARC architectural
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the run-time environment for a SPARC application. The SPARC architectural
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specification allows for the number of register windows to be any power of two
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specification allows for the number of register windows to be any power of two
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less than or equal to 32. The most common choice for SPARC implementations
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less than or equal to 32. The most common choice for SPARC implementations
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appears to be 8 register windows. This results in the cwp ranging in value
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appears to be 8 register windows. This results in the ``CWP`` ranging in value
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from 0 to 7 on most implementations.
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from 0 to 7 on most implementations.
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The second complicating factor is the sharing of registers between adjacent
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The second complicating factor is the sharing of registers between adjacent
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@ -569,25 +569,25 @@ Vectoring of Interrupt Handler
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Upon receipt of an interrupt the SPARC automatically performs the following
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Upon receipt of an interrupt the SPARC automatically performs the following
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actions:
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actions:
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- disables traps (sets the ET bit of the psr to 0),
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- disables traps (sets the ET bit of the ``PSR`` to 0),
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- the S bit of the psr is copied into the Previous Supervisor Mode (PS) bit of
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- the S bit of the ``PSR`` is copied into the Previous Supervisor Mode (PS) bit of
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the psr,
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the ``PSR``,
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- the cwp is decremented by one (modulo the number of register windows) to
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- the ``CWP`` is decremented by one (modulo the number of register windows) to
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activate a trap window,
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activate a trap window,
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- the PC and nPC are loaded into local register 1 and 2 (l0 and l1),
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- the PC and nPC are loaded into local register 1 and 2 (l0 and l1),
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- the trap type (tt) field of the Trap Base Register (TBR) is set to the
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- the trap type (tt) field of the Trap Base Register (``TBR``) is set to the
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appropriate value, and
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appropriate value, and
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- if the trap is not a reset, then the PC is written with the contents of the
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- if the trap is not a reset, then the PC is written with the contents of the
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TBR and the nPC is written with TBR + 4. If the trap is a reset, then the PC
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``TBR`` and the nPC is written with ``TBR`` + 4. If the trap is a reset, then the PC
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is set to zero and the nPC is set to 4.
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is set to zero and the nPC is set to 4.
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Trap processing on the SPARC has two features which are noticeably different
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Trap processing on the SPARC has two features which are noticeably different
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than interrupt processing on other architectures. First, the value of psr
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than interrupt processing on other architectures. First, the value of ``PSR``
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register in effect immediately before the trap occurred is not explicitly
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register in effect immediately before the trap occurred is not explicitly
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saved. Instead only reversible alterations are made to it. Second, the
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saved. Instead only reversible alterations are made to it. Second, the
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Processor Interrupt Level (pil) is not set to correspond to that of the
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Processor Interrupt Level (pil) is not set to correspond to that of the
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@ -764,27 +764,27 @@ An RTEMS based application is initiated or re-initiated when the SPARC
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processor is reset. When the SPARC is reset, the processor performs the
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processor is reset. When the SPARC is reset, the processor performs the
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following actions:
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following actions:
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- the enable trap (ET) of the psr is set to 0 to disable traps,
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- the enable trap (ET) of the ``PSR`` is set to 0 to disable traps,
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- the supervisor bit (S) of the psr is set to 1 to enter supervisor mode, and
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- the supervisor bit (S) of the ``PSR`` is set to 1 to enter supervisor mode, and
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- the PC is set 0 and the nPC is set to 4.
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- the PC is set 0 and the nPC is set to 4.
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The processor then begins to execute the code at location 0. It is important
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The processor then begins to execute the code at location 0. It is important
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to note that all fields in the psr are not explicitly set by the above steps
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to note that all fields in the ``PSR`` are not explicitly set by the above steps
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and all other registers retain their value from the previous execution mode.
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and all other registers retain their value from the previous execution mode.
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This is true even of the Trap Base Register (TBR) whose contents reflect the
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This is true even of the Trap Base Register (``TBR``) whose contents reflect the
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last trap which occurred before the reset.
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last trap which occurred before the reset.
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Processor Initialization
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Processor Initialization
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------------------------
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------------------------
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It is the responsibility of the application's initialization code to initialize
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It is the responsibility of the application's initialization code to initialize
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the TBR and install trap handlers for at least the register window overflow and
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the ``TBR`` and install trap handlers for at least the register window overflow and
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register window underflow conditions. Traps should be enabled before invoking
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register window underflow conditions. Traps should be enabled before invoking
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any subroutines to allow for register window management. However, interrupts
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any subroutines to allow for register window management. However, interrupts
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should be disabled by setting the Processor Interrupt Level (pil) field of the
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should be disabled by setting the Processor Interrupt Level (pil) field of the
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psr to 15. RTEMS installs it's own Trap Table as part of initialization which
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``PSR`` to 15. RTEMS installs it's own Trap Table as part of initialization which
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is initialized with the contents of the Trap Table in place when the
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is initialized with the contents of the Trap Table in place when the
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``rtems_initialize_executive`` directive was invoked. Upon completion of
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``rtems_initialize_executive`` directive was invoked. Upon completion of
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executive initialization, interrupts are enabled.
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executive initialization, interrupts are enabled.
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