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microblaze: Document BSPs and update CPU supplement
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.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
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.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
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Xilinx MicroBlaze Specific Information
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Xilinx MicroBlaze Specific Information
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**************************************
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**************************************
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This chapter discusses the dependencies of the *MicroBlaze architecture*
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(https://en.wikipedia.org/wiki/MicroBlaze).
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**Architecture Documents**
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For information on the MicroBlaze architecture, refer to
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*UG984 MicroBlaze Processor Reference Guide*
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(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf).
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CPU Model Dependent Features
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============================
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There are no CPU model dependent features in this port.
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Calling Conventions
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===================
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Please refer to "Chapter 4: MicroBlaze Application Binary Interface" of
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*UG984 MicroBlaze Processor Reference Guide*
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(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf).
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Interrupt Processing
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====================
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Hardware exceptions, interrupts, and user exceptions are all supported. When a
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hardware exception or user exception occurs, a fatal error will be generated.
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When an interrupt occurs, the interrupt source is determined by reading the
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AXI Interrupt Controller's Interrupt Status Register and masking it with the
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Interrupt Enable Register.
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Interrupt Levels
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----------------
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There are exactly two interrupt levels on MicroBlaze with respect to RTEMS.
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Level zero corresponds to interrupts disabled. Level one corresponds to
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interrupts enabled. This is the inverse of how most other architectures handle
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interrupt enable status.
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Interrupt Stack
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---------------
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The memory region for the interrupt stack is defined by the BSP.
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Default Fatal Error Processing
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==============================
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The default fatal error is BSP-specific.
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Symmetric Multiprocessing
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Symmetric Multiprocessing
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=========================
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=========================
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@ -13,4 +61,4 @@ SMP is not supported.
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Thread-Local Storage
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Thread-Local Storage
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====================
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====================
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Thread-local storage is not implemented.
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Thread-local storage is supported.
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@ -1,8 +1,153 @@
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.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. Copyright (C) 2018 embedded brains GmbH
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.. Copyright (C) 2018 embedded brains GmbH
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.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
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microblaze (Microblaze)
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microblaze (MicroBlaze)
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***********************
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***********************
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There are no Microblaze BSPs yet.
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KCU105 QEMU
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===========
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The basic hardware initialization is performed by the BSP. This BSP supports the
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QEMU emulated Xilinx AXI Interrupt Controller v4.1.
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Boot via ELF
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------------
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The executable image is booted by QEMU in ELF format.
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Clock Driver
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------------
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The clock driver supports the QEMU emulated Xilinx AXI Timer v2.0. It is
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implemented as a simple downcounter.
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Console Driver
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--------------
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The console driver supports the QEMU emulated Xilinx AXI UART Lite v2.0. It is
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initialized to a baud rate of 115200.
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Network Driver
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--------------
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Support for networking is provided by the libbsd library. Network interface
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configuration is extracted from the device tree binary which, by default, is
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in `<bsp/microblaze-dtb.h> <https://git.rtems.org/rtems/tree/bsps/microblaze/microblaze_fpga/include/bsp/microblaze-dtb.h>`_.
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The device tree source for the default device tree is at `dts/system.dts <https://git.rtems.org/rtems/tree/bsps/microblaze/microblaze_fpga/dts/system.dts>`_.
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To replace the default device tree with your own, assuming ``my_device_tree.dts``
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is the name of your device tree source file, first you must convert your device
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tree to .dtb format.
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.. code-block:: none
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$ dtc -I dts -O dtb my_device_tree.dts > my_device_tree.dtb
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The device tree blob, ``my_device_tree.dtb``, can now be converted to a C file.
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The name ``system_dtb`` is significant as it is the name expected by the BSP.
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.. code-block:: none
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$ rtems-bin2c -C -A 8 -N system_dtb my_device_tree.dtb my_dtb
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The ``BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH`` BSP configuration option can then be
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set to the path of the resulting source file, ``my_dtb.c``, to include it in the
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BSP build.
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.. code-block:: none
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BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH = /path/to/my_dtb.c
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Running Executables
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-------------------
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A .dtb (device tree blob) file should be provided to QEMU via the ``-hw-dtb``
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option. In the example command below, the device tree blob comes from the Xilinx
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Petalinux KCU105 MicroBlaze BSP (https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html).
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Executables generated by this BSP can be run using the following command:
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.. code-block:: none
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$ qemu-system-microblazeel -no-reboot -nographic -M microblaze-fdt-plnx -m 256 \
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-serial mon:stdio -display none -hw-dtb system.dtb -kernel example.exe
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Debugging with QEMU
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-------------------
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To debug an application, add the option ``-s`` to make QEMU listen for GDB
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connections on port 1234. Add the ``-S`` option to also stop execution until
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a connection is made.
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For example, to debug the hello sample and break at ``Init``, first start QEMU.
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.. code-block:: none
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$ qemu-system-microblazeel -no-reboot -nographic -M microblaze-fdt-plnx -m 256 \
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-serial mon:stdio -display none -hw-dtb system.dtb -kernel \
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build/microblaze/kcu105_qemu/testsuites/samples/hello.exe -s -S
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Then start GDB and connect to QEMU.
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.. code-block:: none
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$ microblaze-rtems6-gdb build/microblaze/kcu105_qemu/testsuites/samples/hello.exe
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(gdb) target remote localhost:1234
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(gdb) break Init
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(gdb) continue
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KCU105
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======
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The basic hardware initialization is performed by the BSP. This BSP supports the
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Xilinx AXI Interrupt Controller v4.1.
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This BSP was tested using the Xilinx Kintex UltraScale FPGA KCU105 board
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configured with the default Petalinux KCU105 MicroBlaze BSP. The defaults may
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need to be adjusted using BSP configuration options to match the memory layout
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and configuration of your board.
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Clock Driver
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------------
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The clock driver supports the Xilinx AXI Timer v2.0. It is implemented as a
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simple downcounter.
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Console Driver
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--------------
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The console driver supports the Xilinx AXI UART Lite v2.0.
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Debugging
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---------
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The following debugging procedure was used for debugging RTEMS applications
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running on the Xilinx KCU105 board using GDB.
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First send an FPGA bitstream to the board using OpenOCD.
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.. code-block:: none
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$ openocd -f board/kcu105.cfg -c "init; pld load 0 system.bit; exit"
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After the board has been programmed, start the Vivado ``hw_server`` application
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to serve as the debug server. Leave it running in the background for the rest of
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the process.
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.. code-block:: none
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$ tools/Xilinx/Vivado/2020.2/bin/hw_server
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With the debug server running, connect to the debug server with GDB, load the
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application, and debug as usual. By default the GDB server listens on port 3002.
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.. code-block:: none
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$ microblaze-rtems6-gdb example.exe
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(gdb) target extended-remote localhost:3002
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(gdb) load
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(gdb) break Init
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(gdb) continue
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