mirror of
https://git.rtems.org/rtems-docs/
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docs/user: add docs for riscv/kendrytek210 BSP variant
This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. V3 clarified the multilib variant description, clarified the multilib variant reference platform, and corrected capitalization on SiFive. V4 improves the instructions for running the K210 BSP on the Renode.io simulator. V5 cleaned up the text to be no more than 80 characters per line. V6 applied word wrap to paragraphs and replaced hard coded RTEMS major versions with macros. Closes #4876
This commit is contained in:
Alan Cudmore
Joel Sherrill
parent
1ac52ce798
commit
cbeaec94e1
@ -8,7 +8,8 @@ riscv (RISC-V)
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riscv
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=====
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This BSP offers 12 variants:
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**Each variant in this first group corresponds to a GCC multilib option with
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different RISC-V standard extensions.**
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* rv32i
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@ -30,24 +31,27 @@ This BSP offers 12 variants:
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* rv64imafdc
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* frdme310arty
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Each variant reflects an ISA with ABI and code model choice. All rv64 BSPs have
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medany code model by default, while rv32 BSPs are medlow. The reason is that
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RV32 medlow can access the entire 32-bit address space, while RV64 medlow can
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only access addresses below 0x80000000. With RV64 medany, it's possible to
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perform accesses above 0x80000000. The BSP must be started in machine mode.
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* mpfs64imafdc
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The reference platforms for the rv* variants include the QEMU `virt` and
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`spike` machines and the Spike RISC-V ISA simulator.
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Each rv* variant corresponds to a GCC multilib. A particular variant reflects an
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ISA with ABI and code model choice. All rv64 BSPs have medany code model by
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default, while rv32 BSPs are medlow. The reason is that RV32 medlow can access
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the entire 32-bit address space, while RV64 medlow can only access addresses
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below 0x80000000. With RV64 medany, it's possible to perform accesses above
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0x80000000.
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**The BSP also provides the following variants for specific hardware targets:**
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The BSP must be started im machine mode.
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* frdme310arty - The reference platform for this variant is the Arty FPGA board
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with the SiFive Freedom E310 reference design.
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The reference platform for this BSP is the QEMU `virt` machine.
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The reference platform for the mpfs64imafdc BSP variant is the Microchip
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* mpfs64imafdc - The reference platform for this variant is the Microchip
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PolarFire SoC Icicle Kit.
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* kendrytek210 - The reference platform for this variant is the Kendryte K210
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SoC on the Sipeed MAiX BiT or Maixduino board.
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Build Configuration Options
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---------------------------
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@ -77,33 +81,41 @@ configuration INI file. The ``waf`` defaults can be used to inspect the values.
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The path to the header file containing the device tree blob.
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``BSP_CONSOLE_BAUD``
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The default baud for console driver devices (default 115200).
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The default baud for console driver devices (default is 115200).
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``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS``
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The maximum number of external interrupts supported by the BSP (default
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64).
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is 64).
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``RISCV_ENABLE_HTIF_SUPPORT``
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Enable the Host/Target Interface (HTIF) support (enabled by default).
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``RISCV_CONSOLE_MAX_NS16550_DEVICES``
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The maximum number of NS16550 devices supported by the console driver (2
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by default).
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The maximum number of NS16550 devices supported by the console driver
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(default is 2).
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``RISCV_ENABLE_SIFIVE_UART_SUPPORT``
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Enable the SiFive console UART (disabled by default).
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``RISCV_RAM_REGION_BEGIN``
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The begin of the RAM region for linker command file (default is 0x80000000).
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The begin of the RAM region for linker command file
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(default is 0x80000000).
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``RISCV_RAM_REGION_SIZE``
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The size of the RAM region for linker command file (default 64MiB).
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``RISCV_ENABLE_FRDME310ARTY_SUPPORT``
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Enables support sifive Freedom E310 Arty board if defined to a non-zero
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value,otherwise it is disabled (disabled by default)
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value,otherwise it is disabled (disabled by default).
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``RISCV_ENABLE_MPFS_SUPPORT``
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Enables support Microchip PolarFire SoC if defined to a non-zero
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value, otherwise it is disabled (disabled by default).
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``RISCV_ENABLE_KENDRYTE_K210_SUPPORT``
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Enables support for the Kendtryte K210 SoC if defined to a non-zero
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value, otherwise it is disabled (disabled by default).
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``RISCV_BOOT_HARTID``
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The boot hartid (processor number) of risc-v cpu by default 0.
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@ -123,15 +135,15 @@ The clock driver uses the CLINT timer.
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Console Driver
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--------------
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The console driver supports devices compatible to
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The console driver supports devices compatible to:
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* "ucb,htif0" (depending on the ``RISCV_ENABLE_HTIF_SUPPORT`` BSP option),
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* "ns16550a" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option), and
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* "ns16550a" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option),
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* "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option).
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* "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option), and
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* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option).
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* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option).
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They are initialized according to the device tree. The console driver does not
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configure the pins or peripheral clocks. The console device is selected
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@ -145,43 +157,48 @@ and spike machines. For instance, to run the ``rv64imafdc`` BSP with the
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following "config.ini" file.
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.. code-block:: none
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[riscv/rv64imafdc]
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Run the following QEMU command.
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.. code-block:: shell
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$ qemu-system-riscv64 -M virt -nographic -bios $RTEMS_EXE
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$ qemu-system-riscv64 -M spike -nographic -bios $RTEMS_EXE
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Spike
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----
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All of the BSP variants that start with rv can be run on Spike.
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For instance, to run the ``rv64imafdc`` BSP with the following
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"config.ini" file.
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All of the BSP variants that start with rv can be run on Spike. For instance,
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to run the ``rv64imafdc`` BSP with the following "config.ini" file.
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.. code-block:: none
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[riscv/rv64imafdc]
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Run the following Spike command.
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.. code-block:: shell
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$ spike --isa=rv64imafdc $RTEMS_EXE
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Unlike QEMU, Spike supports enabling/disabling a subset of the imafdc extensions
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and has support for further RISC-V extensions as well. A fault will be triggered
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if an executable built with rv64imafdc RISC-V's -march option run on Spike with
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--isa=rv64i option. If no --isa option is specified, the default is rv64imafdc.
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Unlike QEMU, Spike supports enabling/disabling a subset of the imafdc
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extensions and has support for further RISC-V extensions as well. A fault will
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be triggered if an executable built with rv64imafdc RISC-V's -march option run
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on Spike with --isa=rv64i option. If no --isa option is specified, the default
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is rv64imafdc.
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Microchip PolarFire SoC
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-----------------------
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The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and a 64-bit RISC-V
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E51 monitor core SoC from the Microchip.
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The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and a 64-bit RISC-V E51
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monitor core SoC from the Microchip.
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The ``mpfs64imafdc`` BSP variant supports the U54 cores but not the E51 because
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the E51 monitor core is reserved for the first stage bootloader
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(Hart Software Services). In order to boot from the first U54 core,
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``RISCV_BOOT_HARTID`` is set to 1 by default.
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the E51 monitor core is reserved for the first stage bootloader (Hart Software
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Services). In order to boot from the first U54 core, ``RISCV_BOOT_HARTID`` is
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set to 1 by default.
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The device tree blob is embedded in the ``mpfs64imafdc`` BSP variant by default
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with the ``BSP_DTB_IS_SUPPORTED`` enabled and the DTB header path
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@ -204,14 +221,14 @@ Build RTEMS.
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.. code-block:: shell
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$ ./waf configure --prefix=$HOME/rtems-start/rtems/6
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$ ./waf configure --prefix=$HOME/rtems-start/rtems/@rtems-ver-major@
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$ ./waf
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Convert .exe to .elf file.
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.. code-block:: shell
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$ riscv-rtems6-objcopy build/riscv/mpfs64imafdc/testsuites/smptests/smp01.exe build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf
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$ riscv-rtems@rtems-ver-major@-objcopy build/riscv/mpfs64imafdc/testsuites/smptests/smp01.exe build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf
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Generate a payload for the `smp01.elf` using the `hss-payload-generator <https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator>`_.
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@ -277,14 +294,135 @@ Serial terminal UART1 displays the SMP example messages
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*** END OF TEST SMP 1 ***
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Kendryte K210
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-------------
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The Kendryte K210 SoC is a dual core 64-bit RISC-V SoC with an AI NPU, built in
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SRAM, and a variety of peripherals. Currently just the console UART, interrupt
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controller, and timer are supported.
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The device tree blob is embedded in the ``kendrytek210`` BSP variant by
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default. When the kendrytek210 BSP variant is selected,
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``BSP_DTB_IS_SUPPORTED`` enabled and the DTB header path
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``BSP_DTB_HEADER_PATH`` is set to ``bsp/kendryte-k210-dtb.h``.
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The ``kendrytek210`` BSP variant has been tested on the following simulator and
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boards:
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* Renode.io simulator using the Kendrtye k210 model
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* Sipeed MAiX BiT board
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* Sipeed Maixduino board
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* Sipeed MAiX Dock board
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**Building the Kendryte K210 BSP**
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Configuration file ``config.ini``:
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.. code-block:: none
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[riscv/kendrytek210]
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RTEMS_SMP = True
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Build RTEMS:
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.. code-block:: shell
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$ ./waf configure --prefix=$HOME/rtems-start/rtems/@rtems-ver-major@
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$ ./waf
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**Flash an executable to a supported K210 board**
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Binary images can be flashed to the Sipeed boards through the USB port using
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the ``kflash.py`` utility available from the python pip utility.
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.. code-block:: shell
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$ riscv-rtems@rtems-ver-major@-objcopy -Obinary ticker.exe ticker.bin
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$ kflash.py --uart /dev/ttyUSB0 ticker.bin
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After the image is flashed, the RTEMS image will automatically boot. It will
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also run when the board is reset or powered through the USB cable. The USB port
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provides the power and console UART. Plug the USB cable into a host PC and
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bring up a terminal emulator at 115200 baud, 8 data bits, 1 stop bit, no
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parity, and no flow control. On Linux the UART device is often
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``/dev/ttyUSB0``.
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**Run a RTEMS application on the Renode.io simulator**
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RTEMS executables compiled with the kendrytek210 BSP can run on the renode.io
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simulator using the built-in K210 model. The simulator currently supports the
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console UART, interrupt controller, and timer.
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To install renode.io please refer to the `installation instructions <https://github.com/renode/renode#installation>`_.
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Once installed, save the following file as `k210_rtems.resc`.
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.. code-block:: shell
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using sysbus
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$bin?=@ticker.exe
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mach create "K210"
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machine LoadPlatformDescription @platforms/cpus/kendryte_k210.repl
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showAnalyzer uart
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sysbus Tag <0x50440000 0x10000> "SYSCTL"
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sysbus Tag <0x50440018 0x4> "pll_lock" 0xFFFFFFFF
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sysbus Tag <0x5044000C 0x4> "pll1"
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sysbus Tag <0x50440008 0x4> "pll0"
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sysbus Tag <0x50440020 0x4> "clk_sel0"
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sysbus Tag <0x50440028 0x4> "clk_en_cent"
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sysbus Tag <0x5044002c 0x4> "clk_en_peri"
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macro reset
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"""
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sysbus LoadELF $bin
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"""
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runMacro $reset
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After saving the above file in in the same directory as your RTEMS ELF images,
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start renode and load the `k210_rtems.resc` script to start the emulation.
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.. code-block:: shell
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(monitor) s @k210_rtems.resc
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You should see a renode UART window and the RTEMS ticker example output. If you
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want to run a different RTEMS image, you can edit the file or enter the
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following on the renode console.
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.. code-block:: shell
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(monitor) $bin=@smp08.exe
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(monitor) s @k210_rtems.resc
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The above example will run the SMP08 example instead of ticker.
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**Generating the Device Tree Header**
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The kendrytek210 BSP uses a built in device tree blob. If additional peripheral
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support is added to the BSP, the device tree may need to be updated. After
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editing the device tree source, compile it to a device tree blob with the
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following command:
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.. code-block:: shell
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$ dtc -O dtb -b 0 -o kendryte-k210.dtb kendryte-k210.dts
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The dtb file can then be converted to a C array using the rtems-bin2c tool.
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The data for the device tree binary can then replace the existing device tree
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binary data in the ``kendryte-k210-dtb.h`` header file.
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noel
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====
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This BSP supports the `NOEL-V <https://gaisler.com/noel-v>`_ systems from Cobham
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Gaisler. The NOEL-V is a synthesizable VHDL model of a processor that
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implements the RISC-V architecture. It is part of the open source
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`GRLIB <https://gaisler.com/grlib>`_ IP Library. The following BSP
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variants correspond to common NOEL-V configurations:
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This BSP supports the `NOEL-V <https://gaisler.com/noel-v>`_ systems from
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Cobham Gaisler. The NOEL-V is a synthesizable VHDL model of a processor that
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implements the RISC-V architecture. It is part of the open source `GRLIB
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<https://gaisler.com/grlib>`_ IP Library. The following BSP variants correspond
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to common NOEL-V configurations:
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* noel32im
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@ -296,20 +434,18 @@ variants correspond to common NOEL-V configurations:
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* noel64imafdc
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The start of the memory is set to 0x0 to match a standard NOEL-V system,
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but can be changed using the ``RISCV_RAM_REGION_BEGIN`` configuration
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option. The size of the memory is taken from the information available
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in the device tree.
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The start of the memory is set to 0x0 to match a standard NOEL-V system, but
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can be changed using the ``RISCV_RAM_REGION_BEGIN`` configuration option. The
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size of the memory is taken from the information available in the device tree.
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Reference Designs
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-----------------
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The BSP has been tested with NOEL-V reference designs for
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`Digilent Arty A7 <https://gaisler.com/noel-artya7>`_,
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`Microchip PolarFire Splash Kit <https://gaisler.com/noel-pf>`_,
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and `Xilinx KCU105 <https://gaisler.com/noel-xcku>`_.
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See the accompanying quickstart guide for each reference design
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to determine which BSP configuration to use.
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The BSP has been tested with NOEL-V reference designs for `Digilent Arty A7
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<https://gaisler.com/noel-artya7>`_, `Microchip PolarFire Splash Kit
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<https://gaisler.com/noel-pf>`_, and `Xilinx KCU105
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<https://gaisler.com/noel-xcku>`_. See the accompanying quickstart guide for
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each reference design to determine which BSP configuration to use.
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Build Configuration Options
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---------------------------
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