rtems/rtems-docs
1
0
Fork 0
mirror of https://git.rtems.org/rtems-docs/ synced 2025-05-14 12:49:18 +08:00
Code Issues Packages Projects Releases Wiki Activity

Remove references to SPARC/SIS BSP. Also clean up old ERC32 references.

Browse Source 
updates #2810.
This commit is contained in:
Joel Sherrill 2016-11-15 17:54:47 -06:00
parent 2591ca6390
commit d8beaabd02
3 changed files with 7 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
cpu-supplement/sparc.rst
View File

@ -35,7 +35,7 @@ available from SPARC International, Inc. (http://www.sparc.com):
**ERC32 Specific Information**
The European Space Agency's ERC32 is a three chip computing core implementing a
The European Space Agency's ERC32 is a microprocessor implementing a
SPARC V7 processor and associated support circuitry for embedded space
applications. The integer and floating-point units (90C601E & 90C602E) are
based on the Cypress 7C601 and 7C602, with additional error-detection and
@ -46,28 +46,11 @@ error-detection. The core is designed to work at 25MHz, but using space
qualified memories limits the system frequency to around 15 MHz, resulting in a
performance of 10 MIPS and 2 MFLOPS.
Information on the ERC32 and a number of development support tools, such as the
SPARC Instruction Simulator (SIS), are freely available on the Internet. The
following documents and SIS are available via anonymous ftp or pointing your
web browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
The ERC32 is available from Atmel as the TSC695F.
- ERC32 System Design Document
- MEC Device Specification
Additionally, the SPARC RISC User's Guide from Matra MHS documents the
functionality of the integer and floating point units including the instruction
set information. To obtain this document as well as ERC32 components and VHDL
models contact:
Matra MHS SA
3 Avenue du Centre, BP 309,
78054 St-Quentin-en-Yvelines,
Cedex, France
VOICE: +31-1-30607087
FAX: +31-1-30640693
Amar Guennon (amar.guennon@matramhs.fr) is familiar with the ERC32.
The RTEMS configuration of GDB enables the SPARC Instruction Simulator (SIS)
which can simulate the ERC32 as well as the follow up LEON2 and LEON3
microprocessors.
CPU Model Dependent Features
============================

2
rsb/third-party-packages.rst
View File

@ -46,7 +46,7 @@ To build Net-SNMP the command is:
$ ../source-builder/sb-set-builder --log=log_sis_net_snmp \
--prefix=$HOME/development/rtems/bsps/4.11 \
--with-tools=$HOME/development/rtems/4.11 \
--host=sparc-rtems4.11 --with-rtems-bsp=sis 4.11/net-mgmt/net-snmp
--host=sparc-rtems4.11 --with-rtems-bsp=erc32 4.11/net-mgmt/net-snmp
RTEMS Source Builder - Set Builder, v0.3.0
Build Set: 4.11/net-mgmt/net-snmp
config: net-mgmt/net-snmp-5.7.2.1-1.cfg

2
user/installation/releases.rst
View File

@ -54,7 +54,7 @@ shosted here. It has excellent internet access and performance.
By default all the BSPs for an architecture are built. If you only wish to
have a specific BSP built you can specify the BSP list by providing to the
RSB the option ``--with-rtemsbsp``. For example to build two BSPs for the
SPARC architecture you can supply ``--with-rtemsbsp="erc32 sis"``. This can
SPARC architecture you can supply ``--with-rtemsbsp="erc32 leon3"``. This can
speed the build time up for some architectures that have a lot of BSPs.
Once you have built the tools and kernel you can move to the Packages section