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209 lines
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ReStructuredText
209 lines
6.3 KiB
ReStructuredText
.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. Copyright (C) 1988, 2009 On-Line Applications Research Corporation (OAR)
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ARM Specific Information
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************************
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This chapter discusses the *ARM architecture*
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(http://en.wikipedia.org/wiki/ARM_architecture) dependencies in this port of
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RTEMS. The ARMv4T (and compatible), ARMv7-A, ARMv7-R and ARMv7-M architecture
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versions are supported by RTEMS. Processors with a MMU use a static
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configuration which is set up during system start. SMP is supported.
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**Architecture Documents**
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For information on the ARM architecture refer to the *ARM Infocenter*
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(http://infocenter.arm.com/).
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CPU Model Dependent Features
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============================
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This section presents the set of features which vary across ARM implementations
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and are of importance to RTEMS. The set of CPU model feature macros are
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defined in the file :file:`cpukit/score/cpu/arm/rtems/score/arm.h` based upon
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the particular CPU model flags specified on the compilation command line.
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CPU Model Name
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--------------
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The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
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level of this CPU model. See in :file:`cpukit/score/cpu/arm/rtems/score/arm.h`
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for the values.
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Count Leading Zeroes Instruction
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--------------------------------
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The ARMv5 and later has the count leading zeroes ``clz`` instruction which
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could be used to speed up the find first bit operation. The use of this
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instruction should significantly speed up the scheduling associated with a
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thread blocking. This is currently not used.
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Floating Point Unit
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-------------------
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The following floating point units are supported:
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- VFPv2 (for example available on ARM926EJ-S processors)
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- VFPv3-D32/NEON (for example available on Cortex-A processors)
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- VFPv3-D16 (for example available on Cortex-R processors)
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- FPv4-SP-D16 (for example available on Cortex-M processors)
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- FPv5-D16 (for example available on Cortex-M7 processors)
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Multilibs
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=========
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The following multilibs are available:
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#. ``.``: ARMv4T, ARM instruction set
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#. ``vfp/hard``: ARMv4T, ARM instruction set with hard-float ABI and VFPv2 support
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#. ``thumb``: ARMv4T, Thumb-1 instruction set
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#. ``thumb/armv6-m``: ARMv6M, subset of Thumb-2 instruction set
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#. ``thumb/armv7-a``: ARMv7-A, Thumb-2 instruction set
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#. ``thumb/armv7-a/neon/hard``: ARMv7-A, Thumb-2 instruction set with
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hard-float ABI Neon and VFP-D32 support
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#. ``thumb/armv7-r``: ARMv7-R, Thumb-2 instruction set
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#. ``thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Thumb-2 instruction set with
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hard-float ABI VFP-D16 support
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#. ``thumb/cortex-m3``: Cortex-M3, Thumb-2 instruction set with hardware
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integer division (SDIV/UDIV) and a fix for Cortex-M3 Errata 602117.
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#. ``thumb/cortex-m4``: Cortex-M4, Thumb-2 instruction set with hardware
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integer division (SDIV/UDIV) and DSP instructions
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#. ``thumb/cortex-m4/fpv4-sp-d16``: Cortex-M4, Thumb-2 instruction set with
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hardware integer division (SDIV/UDIV), DSP instructions and hard-float ABI
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FPv4-SP support
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#. ``thumb/cortex-m7/fpv5-d16``: Cortex-M7, Thumb-2 instruction set with
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hard-float ABI and FPv5-D16 support
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#. ``eb/thumb/armv7-r``: ARMv7-R, Big-endian Thumb-2 instruction set
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#. ``eb/thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Big-endian Thumb-2 instruction
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set with hard-float ABI VFP-D16 support
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Multilib 1., 2. and 3. support the legacy ARM7TDMI and ARM926EJ-S processors.
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Multilib 4. supports the Cortex-M0 and Cortex-M1 cores.
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Multilib 5. and 6. support the Cortex-A processors.
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Multilib 7., 8., 13. and 14. support the Cortex-R processors. Here also
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big-endian variants are available.
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Use for example the following GCC options:
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.. code-block:: shell
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-mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
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to build an application or BSP for the ARMv7-A architecture and tune the code
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for a Cortex-A9 processor. It is important to select the options used for the
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multilibs. For example:
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.. code-block:: shell
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-mthumb -mcpu=cortex-a9
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alone will not select the ARMv7-A multilib.
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Calling Conventions
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===================
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Please refer to the *Procedure Call Standard for the ARM Architecture*
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(http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf).
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Memory Model
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============
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A flat 32-bit memory model is supported. The board support package must take
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care about the MMU if necessary.
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Interrupt Processing
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====================
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The ARMv4T (and compatible) architecture has seven exception types:
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- Reset
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- Undefined
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- Software Interrupt (SWI)
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- Prefetch Abort
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- Data Abort
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- Interrupt (IRQ)
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- Fast Interrupt (FIQ)
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Of these types only the IRQ has explicit operating system support. It is
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intentional that the FIQ is not supported by the operating system. Without
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operating system support for the FIQ it is not necessary to disable them during
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critical sections of the system.
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The ARMv7-M architecture has a completely different exception model. Here
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interrupts are disabled with a write of 0x80 to the ``basepri_max`` register.
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This means that all exceptions and interrupts with a priority value of greater
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than or equal to 0x80 are disabled. Thus exceptions and interrupts with a
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priority value of less than 0x80 are non-maskable with respect to the operating
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system and therefore must not use operating system services. Several support
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libraries of chip vendors implicitly shift the priority value somehow before
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the value is written to the NVIC IPR register. This can easily lead to
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confusion.
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Interrupt Levels
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----------------
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There are exactly two interrupt levels on ARM with respect to RTEMS. Level
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zero corresponds to interrupts enabled. Level one corresponds to interrupts
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disabled.
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Interrupt Stack
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---------------
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The board support package must initialize the interrupt stack. The memory for
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the stacks is usually reserved in the linker script.
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Default Fatal Error Processing
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==============================
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The default fatal error handler for this architecture performs the following
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actions:
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- disables operating system supported interrupts (IRQ),
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- places the error code in ``r0``, and
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- executes an infinite loop to simulate a halt processor instruction.
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Symmetric Multiprocessing
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=========================
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SMP is supported on ARMv7-A. Available platforms are
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- Altera Cyclone V,
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- NXP i.MX 7, and
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- Xilinx Zynq.
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Thread-Local Storage
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====================
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Thread-local storage is supported.
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