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148 lines
5.0 KiB
ReStructuredText
.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. Copyright (C) 2015 University of York.
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.. COMMENT: Hesham ALMatary <hmka501@york.ac.uk>
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Blackfin Specific Information
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*****************************
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This chapter discusses the Blackfin architecture dependencies in this port of
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RTEMS.
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**Architecture Documents**
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For information on the Blackfin architecture, refer to the following documents
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available from Analog Devices.
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TBD
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- *"ADSP-BF533 Blackfin Processor Hardware Reference."* http://www.analog.com/UploadedFiles/Associated_Docs/892485982bf533_hwr.pdf
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CPU Model Dependent Features
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============================
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CPUs of the Blackfin 53X only differ in the peripherals and thus in the device
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drivers. This port does not yet support the 56X dual core variants.
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Count Leading Zeroes Instruction
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--------------------------------
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The Blackfin CPU has the BITTST instruction which could be used to speed up the
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find first bit operation. The use of this instruction should significantly
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speed up the scheduling associated with a thread blocking.
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Calling Conventions
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===================
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This section is heavily based on content taken from the Blackfin uCLinux
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documentation wiki which is edited by Analog Devices and Arcturus Networks.
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http://docs.blackfin.uclinux.org/
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Processor Background
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--------------------
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The Blackfin architecture supports a simple call and return mechanism. A
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subroutine is invoked via the call (``call``) instruction. This instruction
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saves the return address in the ``RETS`` register and transfers the execution
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to the given address.
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It is the called funcions responsability to use the link instruction to reserve
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space on the stack for the local variables. Returning from a subroutine is
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done by using the RTS (``RTS``) instruction which loads the PC with the adress
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stored in RETS.
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It is is important to note that the ``call`` instruction does not automatically
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save or restore any registers. It is the responsibility of the high-level
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language compiler to define the register preservation and usage convention.
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Register Usage
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--------------
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A called function may clobber all registers, except RETS, R4-R7, P3-P5, FP and
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SP. It may also modify the first 12 bytes in the caller's stack frame which is
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used as an argument area for the first three arguments (which are passed in
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R0...R3 but may be placed on the stack by the called function).
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Parameter Passing
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-----------------
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RTEMS assumes that the Blackfin GCC calling convention is followed. The first
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three parameters are stored in registers R0, R1, and R2. All other parameters
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are put pushed on the stack. The result is returned through register R0.
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Memory Model
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============
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The Blackfin family architecutre support a single unified 4 GB byte address
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space using 32-bit addresses. It maps all resources like internal and external
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memory and IO registers into separate sections of this common address space.
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The Blackfin architcture supports some form of memory protection via its Memory
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Management Unit. Since the Blackfin port runs in supervisior mode this memory
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protection mechanisms are not used.
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Interrupt Processing
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====================
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Discussed in this chapter are the Blackfin's interrupt response and control
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mechanisms as they pertain to RTEMS. The Blackfin architecture support 16 kinds
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of interrupts broken down into Core and general-purpose interrupts.
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Vectoring of an Interrupt Handler
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---------------------------------
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RTEMS maps levels 0 -15 directly to Blackfins event vectors EVT0 - EVT15. Since
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EVT0 - EVT6 are core events and it is suggested to use EVT15 and EVT15 for
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Software interrupts, 7 Interrupts (EVT7-EVT13) are left for periferical use.
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When installing an RTEMS interrupt handler RTEMS installs a generic Interrupt
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Handler which saves some context and enables nested interrupt servicing and
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then vectors to the users interrupt handler.
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Disabling of Interrupts by RTEMS
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--------------------------------
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During interrupt disable critical sections, RTEMS disables interrupts to level
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four (4) before the execution of this section and restores them to the previous
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level upon completion of the section. RTEMS uses the instructions CLI and STI
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to enable and disable Interrupts. Emulation, Reset, NMI and Exception
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Interrupts are never disabled.
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Interrupt Stack
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---------------
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The Blackfin Architecture works with two different kind of stacks, User and
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Supervisor Stack. Since RTEMS and its Application run in supervisor mode, all
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interrupts will use the interrupted tasks stack for execution.
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Default Fatal Error Processing
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==============================
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The default fatal error handler for the Blackfin performs the following
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actions:
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- disables processor interrupts,
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- places the error code in *r0*, and
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- executes an infinite loop (``while(0);`` to
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simulate a halt processor instruction.
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Symmetric Multiprocessing
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=========================
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SMP is not supported.
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Thread-Local Storage
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====================
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Thread-local storage is not implemented.
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Board Support Packages
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======================
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System Reset
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------------
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TBD
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