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125 lines
3.1 KiB
ReStructuredText
125 lines
3.1 KiB
ReStructuredText
.. SPDX-License-Identifier: CC-BY-SA-4.0
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MIPS Specific Information
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*************************
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This chapter discusses the MIPS architecture dependencies in this port of
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RTEMS. The MIPS family has a wide variety of implementations by a wide range
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of vendors. Consequently, there are many, many CPU models within it.
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**Architecture Documents**
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IDT docs are online at http://www.idt.com/products/risc/Welcome.html
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CPU Model Dependent Features
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============================
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This section presents the set of features which vary across MIPS
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implementations and are of importance to RTEMS. The set of CPU model feature
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macros are defined in the file ``cpukit/score/cpu/mips/mips.h`` based upon the
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particular CPU model specified on the compilation command line.
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Another Optional Feature
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------------------------
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The macro XXX
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Calling Conventions
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===================
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Processor Background
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--------------------
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TBD
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Calling Mechanism
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-----------------
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TBD
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Register Usage
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--------------
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TBD
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Parameter Passing
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-----------------
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TBD
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Memory Model
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============
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Flat Memory Model
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-----------------
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The MIPS family supports a flat 32-bit address space with addresses ranging
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from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a
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32-bit value and is byte addressable. The address may be used to reference a
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single byte, word (2-bytes), or long word (4 bytes). Memory accesses within
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this address space are performed in big endian fashion by the processors in
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this family.
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Some of the MIPS family members such as the support virtual memory and
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segmentation. RTEMS does not support virtual memory or segmentation on any of
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these family members.
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Interrupt Processing
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====================
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Although RTEMS hides many of the processor dependent details of interrupt
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processing, it is important to understand how the RTEMS interrupt manager is
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mapped onto the processor's unique architecture. Discussed in this chapter are
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the MIPS's interrupt response and control mechanisms as they pertain to RTEMS.
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Vectoring of an Interrupt Handler
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---------------------------------
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Upon receipt of an interrupt the XXX family members with separate interrupt
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stacks automatically perform the following actions:
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- TBD
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A nested interrupt is processed similarly by these CPU models with the
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exception that only a single ISF is placed on the interrupt stack and the
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current stack need not be switched.
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Interrupt Levels
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----------------
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TBD
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Default Fatal Error Processing
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==============================
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The default fatal error handler for this target architecture disables processor
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interrupts, places the error code in *XXX*, and executes a``XXX`` instruction
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to simulate a halt processor instruction.
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Symmetric Multiprocessing
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=========================
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SMP is not supported.
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Thread-Local Storage
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====================
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Thread-local storage is not implemented.
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Board Support Packages
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======================
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System Reset
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------------
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An RTEMS based application is initiated or re-initiated when the processor is
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reset. When the processor is reset, it performs the following actions:
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- TBD
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Processor Initialization
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------------------------
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TBD
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